JPH0210646Y2 - - Google Patents
Info
- Publication number
- JPH0210646Y2 JPH0210646Y2 JP19738684U JP19738684U JPH0210646Y2 JP H0210646 Y2 JPH0210646 Y2 JP H0210646Y2 JP 19738684 U JP19738684 U JP 19738684U JP 19738684 U JP19738684 U JP 19738684U JP H0210646 Y2 JPH0210646 Y2 JP H0210646Y2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- ceramic
- electrodes
- lumped constant
- center
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 39
- 239000000919 ceramic Substances 0.000 claims description 36
- 239000004020 conductor Substances 0.000 claims description 16
- 229910000859 α-Fe Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- 229910052742 iron Inorganic materials 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
Description
【考案の詳細な説明】
（産業上の利用分野）
本考案は、VHF、UHFおよびマイクロ波帯で
使用される小型集中定数型アイソレータに関し、
特に無線電話機等に使用され、その小型化を達成
する小型集中定数型アイソレータに関する。[Detailed description of the invention] (Industrial application field) This invention relates to a small lumped constant isolator used in the VHF, UHF and microwave bands.
In particular, the present invention relates to a compact lumped constant isolator that is used in radio telephones and the like to achieve miniaturization.
（従来の技術）
従来例の集中定数型アイソレータの断面図を第
３図に、回路図を第４図に示す。この従来例の集
中定数型アイソレータについて説明する。２枚の
フエライトコア１，２の間に絶縁体１４を介して
３枚の中心導体３，４，５が配置されており、前
記フエライトコアはシールド板８，１９にてシー
ルドされて、上部では鉄板７を介して永久磁石６
が配設され、下部では半田９にて下側金属ケース
１５に固着されている。また、前記フエライトコ
アの回りには、該フエライトコアを中心部の透孔
に挿入せしめた２枚のセラミツク基板１７ａ，１
７ｂが配設されている。このセラミツク基板１７
ａ，１７ｂには、電極１８ａ，１８ｂ，１８ｃ，
１８ｄ，１８ｅ，１８ｆ，１８ｇが設けてあり、
静電容量を形成している。下のセラミツク基板１
７ｂでは、キヤパシタC1，C2，C3を形成し、上
のセラミツク基板１７ａでは、キヤパシタC4，
C5，C6を形成している。また、前記中心導体３，
４，５の各々の一端が両セラミツク基板の電極間
に挾まれている。そして上側金属ケース１６をか
ぶせてある。なお、直流抵抗膜部は図示を省略す
る。(Prior Art) A cross-sectional view of a conventional lumped constant isolator is shown in FIG. 3, and a circuit diagram is shown in FIG. 4. This conventional lumped constant isolator will be explained. Three center conductors 3, 4, 5 are arranged between two ferrite cores 1, 2 with an insulator 14 in between, and the ferrite cores are shielded by shield plates 8, 19, and the upper part is Permanent magnet 6 via iron plate 7
is arranged, and the lower part is fixed to the lower metal case 15 with solder 9. Further, around the ferrite core, there are two ceramic substrates 17a, 1, in which the ferrite core is inserted into a through hole in the center.
7b is provided. This ceramic substrate 17
a, 17b, electrodes 18a, 18b, 18c,
18d, 18e, 18f, 18g are provided,
It forms a capacitance. Lower ceramic substrate 1
7b, capacitors C 1 , C 2 , C 3 are formed, and in the upper ceramic substrate 17a, capacitors C 4 , C 3 are formed.
It forms C 5 and C 6 . Further, the center conductor 3,
One end of each of 4 and 5 is sandwiched between the electrodes of both ceramic substrates. Then, an upper metal case 16 is placed over it. Note that illustration of the DC resistance film portion is omitted.
（考案が解決しようとする問題点）
最近の他のマイクロ波素子の飛躍的な小型化に
ともない全体のマイクロ波装置におけるアイソレ
ータの占める空間はかなり目だつものとなつてお
り、アイソレータの小型化及びマイクロ波装置全
体としての小型化の要求が強い。(Problem to be solved by the invention) With the recent rapid miniaturization of other microwave elements, the space occupied by the isolator in the entire microwave device has become quite conspicuous. There is a strong demand for miniaturization of the entire wave device.
しかし、従来の構造では、小型化に対し限界が
あつた。つまり、セラミツク基板に電極を設けて
静電容量を形成する場合、基板の厚さ１、電極の
面積ｓ、基板の誘電率εとすると、静電容量Ｃ
は、Ｃ＝ε・ｓ／１と表わされ、必要な静電容量
を得るためには、電極面積ｓが必要であり、基板
の面積を従来より小さくすることには、限界があ
つた。 However, the conventional structure has a limit to miniaturization. In other words, when forming a capacitance by providing an electrode on a ceramic substrate, if the thickness of the substrate is 1, the area of the electrode is s, and the dielectric constant of the substrate is ε, then the capacitance C
is expressed as C=ε·s/1, and in order to obtain the required capacitance, an electrode area s is required, and there is a limit to making the area of the substrate smaller than in the past.
本考案は、上記の事を鑑みて、新規な構造によ
る小型な集中定数型アイソレータを提供するもの
である。 In view of the above, the present invention provides a compact lumped constant isolator with a novel structure.
（問題点を解決するための手段）
本考案は、中央部に各々電気的絶縁状態で配列
された中心導体を有し、該中心導体の上下には直
径５〜13mmのフエライトコア及びシールド板が装
荷され、更に永久磁石により直流磁界が印加さ
れ、前記フエライトコアを収納する透孔を持ち、
且つ、厚膜により集中定数回路を形成したセラミ
ツク基板、金属ケースより構成される集中定数型
アイソレータにおいて、前記セラミツク基板は２
枚で構成され、共に透孔を持ち、電極による静電
容量と直流抵抗膜を形成した第１のセラミツク基
板と電極による静電容量を形成した第２のセラミ
ツク基板を重ね、前記中心導体の各々の一端を両
セラミツク基板の非接地側電極間に挾み、直流抵
抗膜を形成した第１のセラミツク基板の接地側電
極を金属ケースに、又第２のセラミツク基板の接
地側電極をシールド板端部に接続し、第１、第２
のセラミツク基板に構成される静電容量を各中心
導体に対し並列に接続するものである。(Means for Solving the Problems) The present invention has central conductors arranged in an electrically insulated manner in the center, and above and below the central conductors, ferrite cores and shield plates with a diameter of 5 to 13 mm are arranged. loaded, further applied with a DC magnetic field by a permanent magnet, and having a through hole for accommodating the ferrite core,
In a lumped constant isolator comprising a ceramic substrate on which a lumped constant circuit is formed with a thick film and a metal case, the ceramic substrate has two parts.
A first ceramic substrate, both having through-holes, on which a capacitance due to electrodes and a DC resistance film are formed, and a second ceramic substrate, on which a capacitance due to electrodes is formed, are stacked on top of each other, and each of the central conductors One end is sandwiched between the non-ground side electrodes of both ceramic substrates, the ground side electrode of the first ceramic substrate on which a DC resistance film is formed is placed in the metal case, and the ground side electrode of the second ceramic substrate is placed on the end of the shield plate. connected to the first and second
The capacitance constructed on the ceramic substrate is connected in parallel to each center conductor.
（作用）
本考案は、２枚のセラミツク基板に形成した各
中心導体に対応する静電容量をそれぞれ並列に接
続することにより、セラミツク基板を小さくし、
電極面積を小さくしても必要とする静電容量を得
ることを可能とした。従つて、アイソレータの小
型化を達成を出来るものである。(Function) The present invention reduces the size of the ceramic substrates by connecting in parallel the capacitances corresponding to each center conductor formed on two ceramic substrates.
This makes it possible to obtain the required capacitance even if the electrode area is reduced. Therefore, it is possible to achieve miniaturization of the isolator.
（実施例）
本考案に係る一実施例の断面図を第１図ａに、
セラミツク基板を第１図ｂ，ｃに、回路図を第２
図に示す。本実施例について説明する。２枚のフ
エライトコア１，２の間に絶縁体１４を介して３
枚の中心導体３，４，５が配置されており、前記
フエライトコア１，２は、シールド板８，１２に
てシールドされており、上部に鉄板７を介して永
久磁石６を有し、下部では半田９により下側金属
ケース１０に固着されている。尚、前記中心導体
３，４，５はシールド板１９と一体物で、120度
の間隔で配置してある。また、前記フエライトコ
アの回りには、透孔２１ａ，２１ｂをもつて２枚
のセラミツク基板１２ａ，１２ｂが配置してあ
り、該セラミツク基板１２ａ，１２ｂの両面には
電極１３ａ〜１３ｈ及び直流抵抗膜２０が印刷し
てある。そして、下のセラミツク基板１２ｂで
は、キヤパシタC7，C9，C11を形成し、上のセラ
ミツク基板１２ａでは、キヤパシタC8，C10，C12
を形成してあり、C7とC8，C9とC10，C11とC12が
それぞれ並列になる様に前記中心導体３，４，５
の各々の一端を両セラミツク基板の電極間に挾
み、上側金属ケース１１をかぶせて集中定数型ア
イソレータを形成する。(Example) A cross-sectional view of an example according to the present invention is shown in Fig. 1a.
The ceramic substrate is shown in Figures 1 b and c, and the circuit diagram is shown in Figure 2.
As shown in the figure. This example will be explained. 3 through an insulator 14 between two ferrite cores 1 and 2.
The ferrite cores 1, 2 are shielded by shield plates 8, 12, and have a permanent magnet 6 via an iron plate 7 in the upper part, and a permanent magnet 6 in the lower part. It is fixed to the lower metal case 10 with solder 9. The center conductors 3, 4, and 5 are integral with the shield plate 19, and are arranged at intervals of 120 degrees. Further, two ceramic substrates 12a, 12b are arranged around the ferrite core with through holes 21a, 21b, and electrodes 13a to 13h and DC resistance films are formed on both surfaces of the ceramic substrates 12a, 12b. 20 is printed. In the lower ceramic substrate 12b, capacitors C 7 , C 9 , C 11 are formed, and in the upper ceramic substrate 12 a, capacitors C 8 , C 10 , C 12 are formed.
The central conductors 3, 4, and 5 are arranged so that C 7 and C 8 , C 9 and C 10 , and C 11 and C 12 are parallel to each other.
One end of each is sandwiched between the electrodes of both ceramic substrates and covered with an upper metal case 11 to form a lumped constant isolator.
この本考案の実施例のアイソレータは、周波数
825〜845MHz用のアイソレータであり、ケース
の大きさは、17mm角で形成できた。これに対し従
来の構造で同等のアイソレータを形成すると、ケ
ースの大きさは、20mm角であつた。また、本考案
の構造を用いることにより、上記と同等のアイソ
レータをケースの大きさ15mm角で製作可能なこと
も確認出来た。 The isolator of this embodiment of the invention has a frequency
It is an isolator for 825-845MHz, and the case size was 17mm square. On the other hand, if an equivalent isolator was formed using a conventional structure, the case size would be 20 mm square. It was also confirmed that by using the structure of the present invention, an isolator equivalent to the above can be manufactured with a case size of 15 mm square.
また、本考案は、上記の集中定数型アイソレー
タに限ることなく、その他の集中定数型アイソレ
ータ及びサーキユレータに対しても利用でき、効
果を発揮するものである。 Further, the present invention is not limited to the lumped constant type isolator described above, but can also be used and effectively applied to other lumped constant type isolators and circulators.
（考案の効果）
本考案は、詳記した様に、２枚のセラミツク基
板に形成された各中心導体に対応する静電容量を
それぞれ並列に接続して用いることにより、アイ
ソレータの小型化を達成するものであり、従つ
て、マイクロ波装置も小型化出来、産業上極めて
有益なものである。(Effects of the invention) As described in detail, this invention achieves miniaturization of the isolator by connecting the capacitances corresponding to each center conductor formed on two ceramic substrates in parallel. Therefore, the microwave device can also be miniaturized, which is extremely useful industrially.
第１図ａは、本考案に係る一実施例の断面図で
あり、第１図ｂ，ｃは、本考案に係る一実施例の
それぞれのセラミツク基板の両平面を示す図であ
り、第２図は、第１図の回路図であり、第３図
は、従来例の断面図であり、第４図は、第３図の
回路図である。
１，２……フエライトコア、３，４，５……中
心導体、６……永久磁石、７……鉄板、８……シ
ールド板、９……半田、１０，１５……下側金属
ケース、１１，１６……上側金属ケース、１２
ａ，１２ｂ……本考案のセラミツク基板、１３ａ
〜１３ｈ……電極、１４……絶縁体、１７ａ，１
７ｂ……従来のセラミツク基板、１８ａ〜１８ｇ
……電極、１９……シールド板、２０……直流抵
抗膜、２１ａ，２１ｂ……透孔。
FIG. 1a is a cross-sectional view of an embodiment of the present invention, and FIGS. 1b and 1c are views showing both planes of each ceramic substrate of the embodiment of the present invention. The figures are the circuit diagram of FIG. 1, FIG. 3 is a sectional view of the conventional example, and FIG. 4 is the circuit diagram of FIG. 3. 1, 2... Ferrite core, 3, 4, 5... Center conductor, 6... Permanent magnet, 7... Iron plate, 8... Shield plate, 9... Solder, 10, 15... Lower metal case, 11, 16... Upper metal case, 12
a, 12b... Ceramic substrate of the present invention, 13a
~13h... Electrode, 14... Insulator, 17a, 1
7b... Conventional ceramic substrate, 18a to 18g
... Electrode, 19 ... Shield plate, 20 ... DC resistance film, 21a, 21b ... Through hole.
Claims (1)
導体を有し、該中心導体の上下には直径５〜13mm
のフエライトコア及びシールド板が装荷され、更
に永久磁石により直流磁界が印加され、前記フエ
ライトコアを収納する透孔を持ち、且つ、厚膜に
より集中定数回路を形成したセラミツク基板、金
属ケースより構成される集中定数型アイソレータ
において、前記セラミツク基板は２枚で構成さ
れ、共に透孔を持ち、電極による静電容量と直流
抵抗膜を形成した第１のセラミツク基板と、電極
による静電容量を形成した第２のセラミツク基板
を重ね、前記中心導体の各々の一端を両セラミツ
ク基板の非接地側電極間に挾み、直流抵抗膜を形
成した第１のセラミツク基板の接地側電極を金属
ケースに、又第２のセラミツク基板の接地側電極
をシールド板端部に接続し、第１、第２のセラミ
ツク基板に構成される静電容量を各中心導体に対
し並列に接続したことを特徴とする集中定数型ア
イソレータ。 It has a central conductor arranged in an electrically insulated manner in the center, and above and below the central conductor there are conductors with a diameter of 5 to 13 mm.
A ferrite core and a shield plate are loaded, a direct current magnetic field is applied by a permanent magnet, a ceramic substrate has a through hole for accommodating the ferrite core, and a lumped constant circuit is formed with a thick film, and a metal case. In the lumped constant type isolator, the ceramic substrate is composed of two ceramic substrates, each having a through hole and a first ceramic substrate having a capacitance formed by electrodes and a DC resistance film, and a first ceramic substrate forming a capacitance by electrodes. A second ceramic substrate is stacked, one end of each of the center conductors is sandwiched between the non-ground electrodes of both ceramic substrates, and the ground electrode of the first ceramic substrate on which a DC resistance film is formed is placed in a metal case. A lumped constant characterized in that the ground side electrode of the second ceramic substrate is connected to the end of the shield plate, and the capacitances formed on the first and second ceramic substrates are connected in parallel to each center conductor. type isolator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19738684U JPH0210646Y2 (en) | 1984-12-25 | 1984-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19738684U JPH0210646Y2 (en) | 1984-12-25 | 1984-12-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61111205U JPS61111205U (en) | 1986-07-14 |
| JPH0210646Y2 true JPH0210646Y2 (en) | 1990-03-16 |
Family
ID=30755647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19738684U Expired JPH0210646Y2 (en) | 1984-12-25 | 1984-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0210646Y2 (en) |
-
1984
- 1984-12-25 JP JP19738684U patent/JPH0210646Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61111205U (en) | 1986-07-14 |
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