JPH02105941A - Microprocessor for evaluation - Google Patents

Abstract

PURPOSE:To obtain strict standards with small variance between an internal control signal and an external control signal by adding an internal buffer circuit which inputs an external hardware control signal to a buffer part and outputs an internal hardware control signal. CONSTITUTION:Two-phase reference clocks phi1 and phi2 for control which are generated by a clock generator 3 are inputted to the external buffer circuit 4 of the buffer part 6 and outputted as two-phase reference clocks CLK1 and CLK2 for in-circuit emulator design and also supplied to an instruction fetching unit 8 with an internal instruction queue through an internal buffer circuit 5. The strict specification of an operation display signal SB indicating the operation of an instruction queue obtained at an output terminal TB through an output buffer 11 is therefore calculated for the design clocks CLK1 and CLK2. Consequently, the strict specification is obtained between signals having mutual casual relation with a control signal for respective hardware control signals in the device which are sent out.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an evaluation microprocessor.

[Conventional technology]

The evaluation microprocessor operates in exactly the same way as the microprocessor to be evaluated, and is furthermore equipped with a debugging function for outputting various control signals and operation status inside the device to the outside of the device.

Therefore, by operating such an evaluation microprocessor on a target system and monitoring the above debugging functions, it is possible to grasp the internal operation of the device and easily analyze the execution process of the device. It becomes possible.

This type of evaluation microprocessor is not actually used by being directly incorporated into a target system, but is usually used in a microprocessor development support device called an in-circuit emulator.

In addition to the evaluation microprocessor, an in-circuit emulator basically includes a program storage device that stores an evaluation program that runs on the target system and allows the evaluation program to be executed by the evaluation microprocessor. It is equipped with a break circuit that stops the execution of the microprocessor according to specific conditions specified in advance, and a trace device that stores the execution process of the processor.

That is, the evaluation microprocessor executes the evaluation program within an in-circuit emulator, and direct interface with the target system is performed via a cable called a probe.

In reality, this probe is connected to the location on the target system where the microprocessor to be evaluated is originally installed.

On the other hand, the evaluation microprocessor supplies various internal device control signals and operation status necessary for analyzing the execution process of the processor itself to the tracing device in the in-circuit emulator at the same time as the evaluation program is executed. .

For example, in a processor with an instruction queue, prefetched instructions are not necessarily executed.

That is, due to the occurrence of execution 1 interrupt processing of a branch instruction, etc., the instruction may be discarded before being fetched from the instruction queue to the execution unit.

In other words, simply monitoring the operation of the bus of the microprocessor that fetches instructions using the tracing device of the in-circuit emulator cannot determine whether or not the fetched instructions have actually been executed.

Therefore, it becomes necessary to trace the operation of the instruction queue inside the device itself.

In this way, the in-circuit emulator uses the evaluation processor to execute the evaluation program, and traces the bus cycles that occur at that time, the control signals inside the device, the operation status, etc.・Be able to evaluate the validity of system evaluation programs and hardware.

Now, the performance of microprocessors has improved dramatically in recent years, and some of the most advanced microprocessors have even reached an operating frequency of 20 MHz.

One cycle corresponds to 50 ns, and various hardware functions in units of this cycle.

Moreover, since the hardware inside the device normally operates using a two-phase signal as a reference clock, the control signal inside the device operates at twice the operating frequency of the actual processor.

One cycle corresponds to 25 ns, and internal control signals and the like operate in units of this cycle.

In in-circuit emulators, with the advent of the above-mentioned high-level microprocessors, it has become necessary to design hardware using control signals and the like inside devices that operate at such high operating frequencies.

When designing hardware, it is essential to specify specifications, which are the standards of the signals to be used.

In particular, since the control signals inside the device change in synchronization with the two-phase reference clock mentioned above, when dealing with signal systems that function at high frequencies as mentioned above, strict specifications for this two-phase reference clock have not been established before. has become increasingly important.

Therefore, as an example, an example of calculating specs of an operation display signal inside a device indicating the operation of the above-mentioned instruction queue with respect to this two-phase reference clock will be described as an example of the conventional technology.

FIG. 4 is a block diagram of a first example of a conventional evaluation microprocessor.

Two-phase reference clocks φ1 and φ2 are input from an external clock generator 2 to the evaluation microprocessor 1b.

In this case, the specifications of the operation display signal SB indicating the operation of the instruction queue at the output terminal T can be calculated based on the reference clock φ1 or φ2.

This is because the hardware section 1 in the microprocessor
0 because it operates in synchronization with this reference clock.

That is, the reference clock φ1. The delay of φ2, the delay of the signal SQ generated by the reference clock considering this delay, and the output buffer 11 for outputting this operation signal SQ to the outside.
By simply adding the delay due to the output terminal Ta
The spec of the operation display signal SR in is obtained.

Therefore, the specifications of the internal control signal monitored at the output terminal TB are based on the reference clock φ1. Since it is based on φ2,
In-circuit emulator using this control signal
Similarly, the hardware section 10 of
It is possible to design based on φ2.

As described above, the method of inputting the reference clock of a microprocessor from the outside is relatively common in multi-chip microprocessors.

On the other hand, in single-chip microprocessors that incorporate various peripheral hardware such as memory devices, interrupt controllers, and counter controllers on a single chip, in many cases the clock generator is also incorporated inside the device. It has become.

Furthermore, among multi-chip microprocessors, this method is often used in products that incorporate peripheral hardware such as interrupt controllers on one chip.

A microprocessor like this with a built-in clock generator can control the stopping and restarting of the supply of the reference clock, and can easily realize a standby mode that operates with extremely low current consumption by stopping the clock. have advantages.

Also, since no external clock generator is required,
It is also possible to reduce the number of system parts and reduce the cost.

FIG. 5 is a block diagram of a second example of a conventional evaluation microprocessor.

The two-phase reference clocks φl and φ2, which are not generated by the clock generator 3 inside the evaluation microprocessor 1c, are generated by each unit 7. of the hardware section 10 inside the device.
8 and 9, and a reference clock CLK for in-circuit emulator design via an external buffer circuit 4.

and output to the outside of the device as CLK2.

[Problem to be solved by the invention]

When evaluating a microprocessor having an internal clock generator, the conventional evaluation microprocessor described above uses two-phase reference clocks φ1 . Between φ2 and two-phase reference clocks CL K r and CL K2 for in-circuit emulator design that are output to the outside of the device,
A phase difference corresponding to the delay of the external buffer circuit occurs.

The specifications of the SR of the operation display signal indicating the operation of the instruction queue described in the example of the prior art are based on the two-phase reference clock φ1. φ
It can be calculated strictly as a specification for 2.

However, in the specifications of the above-mentioned operation display signal S8 for the two-phase reference clocks CLKl and CLK2 for in-circuit emulator design, it is necessary to consider the delay with a certain variation width of the external buffer circuit 4. Therefore, it is difficult to calculate the specifications, and the reference clock φ1. There was a problem that the specifications had to be more redundant than the specifications for φ2.

FIG. 6 is a timing diagram of signals of various parts for explaining the operation of the circuit of FIG. 5.

That is, the reference clock φ1. The specification of the operation display signal SR at point B with respect to φ2 is 40 to 50 ns as the addition of delay values generated in each phase, but the design clock CLK1. For CLK2, a delay of 20 to 30 ns by the external buffer circuit 4 is
Since it acts in a negative direction relative to the delay component mentioned above, subtracting this component will result in a relative value of 10 to 30 ns,
The variation is as large as 20 ns.

Also, in the device external buffer circuit, a large capacity buffer is used in consideration of driving externally connected hardware, so the delay due to this buffer is due to the output buffer 11. This is relatively larger than the delay amount, which prevents calculation of exact specifications.

This means that when designing an in-circuit emulator using a microprocessor for evaluation of a high-level microprocessor that operates at a high frequency as described in the conventional technology,
A problem has arisen in which the redundancy of the already strict design creates further constraints.

The above-mentioned problems are not limited to the relationship between the two-phase reference clock for in-circuit emulator design and internal control signals of the evaluation microprocessor mentioned in the conventional example, but also the relationship between the in-circuit emulator and the internal control signals output to the outside of the device. The same problem applies to all signal systems where there is a phase difference between the hardware control signal inside the device for design and the signal actually handled inside the device due to the buffer section for outputting to the outside of the device. is happening.

SUMMARY OF THE INVENTION An object of the present invention is to provide an evaluation microprocessor that can obtain strict specifications with less variation between internal control signals and external control signals.

[Means to solve the problem]

The evaluation microprocessor of the present invention has a buffer section having an external buffer circuit that inputs internal signals and outputs an external hardware control signal, and an instruction queue, and is controlled by the internal hardware control signal. In the evaluation microprocessor, the evaluation microprocessor has an instruction fetch unit and outputs an operation display signal indicating the operation of the instruction queue, wherein the external hardware control signal is input to the buffer section to control the internal hardware. It is configured with an additional internal buffer circuit that outputs signals.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of the present invention.

The evaluation microprocessor 1 has a buffer unit 6 between the output terminal of the reference clocks φ1 and φ2 of the clock generator 3 and the common input terminal of the execution unit 7, the instruction fetch unit 8, and the bus control unit 9. The evaluation microprocessor 1c is the same as the conventional evaluation microprocessor 1c except that the buffer section 6b in FIG. 5 is replaced.

The buffer unit 6 inputs the design clocks CLK and CLK2 to the conventional output buffer circuit 4 which inputs the reference clocks φl and Φ2 and outputs the design clocks CLK and CLK2, and outputs the design clocks CLK and CLK2 to the hardware unit 10. It is constructed by adding an internal buffer circuit 5 that provides an internal control signal.

FIG. 2 is a timing chart of signals of various parts for explaining the operation of the circuit of FIG. 1.

The crystal oscillator 2 supplies an oscillation clock Sc to the clock generator 3 via a buffer.

2 for control generated by clock generator 3
Phase reference clock φ1. φ2 is inputted to the external buffer circuit 4 of the buffer section 6 and outputted to the outside as a two-phase reference clock CLK and CLK for in-circuit emulator design, while it is outputted to the outside as an internal command via the internal buffer circuit 5. The instructions are supplied to an instruction fetch unit 8 having a queue.

Therefore, the exact specifications of the operation display signal SR indicating the operation of the instruction queue obtained at the output terminal T8 via the output buffer 11 can be calculated for the design clocks CLK1 and CLK2.

In other words, the design clock C by the internal buffer circuit 5
LK1. The specifications take into account the delay of CLK2, the delay of the operation signal Sq indicating the operation of the instruction queue generated by the reference clocks φl and φ2 that take this delay into consideration, and the delay caused by the output buffer 11.

That is, the operation display signal SR at the output terminal TB is generated at the rising time t of the design clock CL K l. 45-55 against
Since the delay is about ns and the variation thereof is 1 ons, it is reduced to half of the conventional 20 ns, making it possible to significantly reduce redundancy in the design of the in-circuit emulator.

FIG. 3 is a block diagram of a second embodiment of the invention.

This embodiment is an example in which the present invention is applied to correcting the phase relationship between a hardware reset signal inside the device that is input from outside the device and the same reset signal that is output outside the device.

The reset signal SR is an initialization signal for the hardware section inside the device that is output from peripheral hardware outside the device, and is input to the reset control circuit 13 inside the device.

In the reset control circuit 13, the input reset signal S
Noise removal processing using an analog delay or the like is performed on R, and a valid reset signal SRR is output for a signal that conforms to specified specifications.

The valid reset signal SRR is sent to an external reset signal SRO of external hardware via an external buffer circuit 4.
At the same time, an internal reset signal SRI is supplied to each hardware inside the device via the internal buffer 5.

Therefore, the reset signal SRO and the reset signal SRI
Strict specifications can be defined between control signals inside various devices that have a causal relationship with

This is particularly important when, for example, the evaluation microprocessor itself is composed of two or more chips.

That is, in recent microprocessors, particularly single-chip microprocessors, a method of expanding the product lineup by providing variations in peripheral hardware built into the microprocessor has become mainstream.

It is not a good idea to create evaluation microprocessors in one-to-one correspondence for each of these types of microprocessors.

Therefore, the CPU core section, which is a common part, is usually placed on one chip, and the peripheral hardware section, which is subject to variation, is placed on a separate chip.

In other words, by replacing the peripheral hardware chips, it can support multiple types of microprocessors.

The above-mentioned reset signal is a signal system that is valid for a plurality of devices at the same time, and requires strict mutual specifications of control signals generated within each device by this signal system.

In this way, not only the reset signal shown in this example, but also signal systems that function via multiple devices are at risk of losing synchronization between devices due to the transmission delay. have sex.

Therefore, it is essential to calculate the exact specifications of the signal system, and this embodiment is highly effective.

〔Effect of the invention〕

As explained above, the evaluation microprocessor according to the present invention creates a phase difference between the hardware control signal inside the device that is output to the outside of the device and the control signal that is supplied to each hardware inside the actual device. Since this does not occur, there is an effect that strict specifications can be obtained between each hardware control signal inside the device that is output to the outside and signals that have a causal relationship with each other.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a timing diagram of signals of each part to explain the operation of the circuit of FIG. 1, and FIG. 3 is a block diagram of a second embodiment of the present invention. Block diagram of
FIGS. 4 and 5 are block diagrams of first and second examples of conventional evaluation microprocessors, and FIG. 6 is a timing diagram of signals of various parts for explaining the operation of the circuit shown in FIG. 5. 1.11...Evaluation microprocessor, 3...Tarlock generator, 4...External buffer circuit,
5... Internal buffer circuit, 6, 6a... Buffer section, 8... Instruction fetch unit,
9...Bus control unit, CLKl, CLK
2... Design clock, Ss... instruction queue operation display signal, φl, φ2... reference clock.

Claims (1)

[Claims] It has a buffer section having an external buffer circuit that inputs an internal signal and outputs an external hardware control signal, and an instruction fetch unit that has an instruction queue and is controlled by the internal hardware control signal. In the evaluation microprocessor that outputs an operation display signal indicating the operation of the instruction queue, the buffer section includes an internal buffer circuit that inputs the external hardware control signal and outputs the internal hardware control signal. An evaluation microprocessor featuring additional features.