JPH02105743A - Ring type lan connecting device - Google Patents

Abstract

PURPOSE:To connect or disconnect a processor without resending data with a simple circuit configuration by proving two transmitting routes having the same delay time. CONSTITUTION:Signals fetched by a 1st connecting device 21 from one end (a) of a transmission line are outputted to the other end (b) of the transmission line through the 1st data path which inputs the signals to a 1st processor 31 and outputs the output signal of the processor 31 to the other end (b). When the processor 31 is disconnected or does not operate normally, the signals fetched to the connecting device 21 are outputted to the other end (b) through the 2nd data path into which a delay circuit 4 is inserted. The delay circuit 4 has the same delay time as the delay time produced at the processor 31 for processing signals and the delay time on the 2nd data path becomes equal to that on the 1st data path. Therefore, connection or disconnection of the processor can be performed without resending data with a simple circuit configuration.

Description

[Detailed Description of the Invention] [Summary] Connecting a processing device without interrupting a call on a ring,
Regarding a ring type LAN connection device that can be disconnected.

Its purpose is to connect or disconnect processing devices without retransmitting data, using an hour wheel circuit configuration.

In a ring-type LAN connection device that is inserted between one end of a transmission path and the other end to form a closed ring-shaped transmission path, a signal taken in from one end of the transmission path is input to a processing device, and a first data path for outputting an output signal of the processing device delayed by a predetermined time from the input to the other end of the transmission path; and one end and the other end of the transmission path. It is a data path that short-circuits the

and a second data path formed by inserting a delay circuit having a delay time substantially equal to the delay time in the processing device.

[Industrial application field]

The present invention relates to a ring-type LAN connection device, and more particularly to a ring-type LAN connection device that allows processing devices to be connected and disconnected without interrupting communication on the ring.

Processing distribution using multiple processing devices is becoming common,
In this case, a ring-type LAN (Local Area Network) is often used as an interconnection method between processing devices.
work ) is used.

In this ring-type LAN, when a processing device is connected or disconnected from the LAN, it is necessary to reconfigure five rings (a closed ring-shaped transmission path).

[Conventional technology]

In a ring-type LAN, a connecting device is inserted into a ring-shaped transmission path to form a ring. A signal transmitted on the ring flows in the order of transmission path (upstream side) - connection device - processing device - connection device - transmission path (downstream side) in each connection device. Therefore, when the processing device is disconnected from the LAN due to a failure occurring in the processing device, for example, the ring will be disconnected. Therefore, in order to prevent this, the connecting device is activated. New processing equipment on LAN
The same applies when connecting to.

FIG. 5 is an explanatory diagram of the prior art, showing the configuration of a conventional connection device.

In the connection device 2 shown in FIG. 5(A), the detection circuit 10 detects a connection request message from the processing device, and the switching circuit 9 connects the processing device to the LAN in response to a switching signal formed based on this. Connect or disconnect. As a result, the signal transmitted on the ring can flow as follows: transmission line (upstream side) - switching circuit 9 - transmission line (downstream side), or transmission line (upstream side) - switching circuit 9 - processing device - switching circuit. 9 - Transmission line (downstream side).

In the connection device 2 shown in FIG. 5(B).

The relay 11 is operated by the drive current from the processing device,
Connect or disconnect the processing device and LAN.

Thus, upon connection or disconnection of the processing device.

The connection device 2 reconfigures the ring by switching the signal flow as described above so that the ring is not disconnected.

[Problem to be solved by the invention]

According to the prior art described above, although the ring can be reconfigured, there are problems as follows.

When the connecting device 2 is equipped with a function of connecting to a LAN in response to a connection request from each processing device, as in the connecting device 2 shown in FIG. 5(A), the circuit configuration within the connecting device 2 becomes complicated. turn into. Therefore, the cost of the connecting device 2 increases and the reliability decreases.

On the other hand, according to the connecting device 2 shown in FIG. 5(B), although the device is simplified and the cost is reduced, the message (data) passing through the connecting device 2 is destroyed when connecting or disconnecting. It ends up. For example, when transmitting at a transmission rate of IMbp, s, if the transmission line is disconnected for a period of several 100 m5ec due to connection, several 100 kbits of data will be lost. Therefore, it becomes necessary to retransmit data, and the throughput of the transmission path decreases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a ring-type LAN connection device that has a simple circuit configuration and is capable of connecting and disconnecting processing devices without retransmitting data.

[Means to solve the problem]

FIG. 1 is a diagram illustrating the principle of the present invention and shows a connecting device and a ring type LAN according to the present invention.

In FIG. 1, 1 is a closed ring-shaped transmission line, 21 to 24 are first to fourth connection devices, and 3.
34 are first to fourth processing devices, 4 is a delay circuit,
5 is a switch circuit.

Ring l is inserted between transmission lines such as coaxial cables or optical fibers to connect the transmission lines, thereby configuring one closed ring-shaped transmission line. It consists of connecting devices 21 to 24. For example, the contact Vt device 21 is connected to one end (upstream side) of the transmission path.
It is inserted between a and the other end (downstream side) b.

The connection device 21 takes in the signal transmitted on the ring 1 from one end a of the transmission path, and inputs it to the processing device 31 connected to the connection device 21.

The processing device 31 outputs a signal according to the input signal. This output signal is a signal obtained by delaying the input signal by a predetermined time from the input.

The delay circuit 4 takes in the signal transmitted on the ring 1 from one end a of the transmission path, delays it by a predetermined time, and outputs it. The delay time of the signal in the delay circuit 4 is made substantially equal to the delay time of the output signal with respect to the input signal in the processing device 31.

The switch circuit 5 outputs either the output signal from the processing device 31 or the output signal from the delay circuit 4 to the other end of the transmission line according to the switching signal.

It should be noted that the second to fourth connection devices 22 to 24 are the same as the first connection device 21, so a description thereof will be omitted (the same applies below).

[Effect]

When the processing device 31 is connected and operating normally, the output signal of the processing device 31 is outputted to the other end of the transmission line by the switch circuit 5. That is, a signal taken into the connection device 21 from one end a of the transmission path is transferred to the processing device 3.
Enter 1 and gah.

The corresponding output signal of the processing device 31 is output to the other end of the transmission line via the first data path.

On the other hand, when the processing device 31 is disconnected but not operating normally, the output signal of the delay circuit 4 is outputted to the other end of the transmission line by the switch circuit 5.

That is, the signal taken into the connection device 21 from one end a of the transmission path is connected to a second data path in which the delay circuit 4 is inserted, which is a data path that short-circuits one end a and the other end of the transmission path. The signal is output to the other end via the .

Here, since the delay circuit 4 has a delay time substantially equal to the delay time of the signal in the processing device 31, the first
and the delay times in the second data path are substantially equal.

Therefore, by utilizing this, for example, during signal transmission using the first data path, the processing device 31 is disconnected in response to a failure in the processing device 31, and the switch circuit 5 is used to disconnect the second data path.
Switch the transmission path to use the data path. Alternatively, while the second data path is in use, the processing device 31 that has issued the connection request is connected, and the transmission path is switched to use the first data path.

Even if the transmission path is switched or the processing device 31 is disconnected or connected, the connection device 21 will not be connected to the other end of the transmission path.
will output the correct signal.

That is, since the delay times are the same, no matter what timing the switching is performed, data continuity is maintained and the data is not destroyed. Therefore, cutting of ring 1 is prevented,
Data on ring 1 is always guaranteed.

As a result, the processing device 31 can be connected or disconnected even while the ring-type LAN is in operation (signal transmission), and there is no need to retransmit data accordingly.

Furthermore, since the circuit configuration is simple in that the delay circuit 4 is inserted between one end a and the other end of the transmission path, deterioration in reliability can be prevented.

〔Example〕

2 and 3 are configuration diagrams of the embodiment, and in these figures, 41 is a shift register, and 51 and 52 are AND
The gate and 6 are switching signal generation circuits.

61 is a comparison circuit, 62 is a timer, 63 is a gate circuit, 6
4 is an OR gate, 71 and 72 are level conversion circuits, and 8 is a connector.

The delay circuit 4 is configured as a shift register 41. What is the number of stages (number of bits) of the shift register 41?

The delay time of the output signal with respect to the input signal is the processing device 3
The delay time is determined to be substantially equal to the delay time due to serial/parallel conversion, etc. performed within 1.

Therefore, the delay time in the shift register 41 can be easily and correctly set to a desired value.

In addition to the output of the shift register 41, the output of the processing device 31 is supplied to the switch circuit 5 via the connector 8 and the level conversion circuit 72. Prior to this, the same human input signal to the shift register 41 is input to the processing device 31 via the level conversion circuit 71 and the connection coster 8, and the processing device 3I performs serial/parallel conversion.
After predetermined processing such as parallel/serial conversion, it is output.

Switching of the transmission line by the switch circuit 5 is performed in accordance with a switching signal from a switching signal generating circuit 6. This switching signal is formed as follows.

The comparison circuit 61 compares the output of the shift register 41 and the output of the processing device 31 (two outputs to be selected by the switch circuit 5).
A one-defeat/mismatch signal is output as a result. This coincidence/mismatch signal is sent to the switch circuit 5 so as to select the output of the processing device 31 when there is a coincidence, and to select the output of the shift register 41 when there is a mismatch.
This is a signal that instructs the That is, when there is a mismatch, the output of the shift register 41 is passed downstream from the connecting device 21. Note that the -defeat/mismatch signal is 1, for example.

It is set at a high level (“1”) when there is a loss, and set at a low level (“0”) when there is a disagreement.

The gate circuit 63 invalidates the output of the comparison circuit 6I when the 5 processing device 31 is transmitting a message (transmission). When the processing device 3I sends a message, the comparison circuit 6
An output of 1 indicates a mismatch.

However, the gate circuit 63 invalidates this output and instructs the switch circuit 5 to select the output of the processing device 31 instead of the output of the shift register 41.

The timer 62 sends out a signal that causes the gate circuit 63 to invalidate the output of the comparison circuit 61 only while the processing device 31 is outputting the transmission request. Further, the timer 62 measures the time during which the transmission request is output (the time during which the message is sent), and when this exceeds a specified time, it is determined that an abnormality has occurred, and the comparison circuit 61 outputs the output again. Sends a signal to enable the As a result, instead of the output of the processing device 31, the output of the shift register 41 is output from the connection device 21. Here, the specified time is 1, for example, the sum of the maximum message time and the delay time in ring 1. In addition,
The timer 62 outputs a high level when invalidating the output of the comparison circuit 61, and outputs a low level when validating the output. The gate circuit 63 is composed of an OR gate 64 and an
The D gate 51 is supplied with an inverted signal of the output of the OR gate 64 . By configuring the gate circuit 63 and the switch circuit 5 in this manner, it is possible to switch the transmission path at a speed sufficiently higher than the signal transmission speed on the ring I.

Next, the operation of the connecting device 21 will be explained in detail using the waveform diagrams shown in FIGS. 4(A) to 4(D). Incidentally, in FIG. 4, signals ``■'' to ``■'' indicate signals appearing in the portions marked ``■'' to ``■'' in the circuit shown in FIG.

(A) When transmitting a message from the processing device 34 to the processing device 32; frame reception status (Fig. 4 (8)) The message is as follows:
The data is input from the processing device 34 to the connection device 21 via the connection device 24. This human power (signal ■) is the shift register 4
1 and sent to the processing device 31. When the processing device 31 is connected to the LAN and is operating normally (repeating the received signal correctly), its output is delayed from the signal ■ by the processing time in the processing device 31 (signal ■). On the other hand, the output of the shift register 41 (signal ■) is also a signal delayed by the same amount of time from the signal ■.

Therefore, the output of the comparison circuit 61 (signal ■) indicates a match.
On the other hand, since there is no transmission request from the processing device 31 (signal ■ - "0"), the output of the timer 62 (signal ■
) is set to “0”. As a result, the output (signal ■) of the OR gate 64 is set to "1".

As a result of the above, the output of the AND gate 52 is validated, so the switch circuit 5 selects the signal ■ and outputs it as its output (signal ■).

Furthermore, if signals ■ and ■ match before this.

The switch circuit 5 has already selected the signal ■. Also, normally, the processing devices 31 to 34 are in a frame receiving state.

(B) When transmitting a message from the processing device 31 to the processing device 32; frame transmittal letter B (FIG. 4(B)) processing device 31
outputs a transmission request (signal ■=“1”) and transmits a message (signal ■ is output).

Since there is no signal ■ input, signal ■ is not output.

Therefore, the signal ■ is set to "0" indicating a mismatch.

However, since the timer 62 sets the signal ■ to "1" based on the "1" of the signal ■, the "0" of the signal ■ is invalidated.
The signal ■ is set to "1".

As a result of the above, the signal ■ is outputted from the switch circuit 5 as the signal ■.

The processing device 31 waits for a delay time A to elapse after the output of the signal ■ is finished so that the signal ■ is not output as the signal ■.
Set the signal ■ to “0”. As a result, the signal (2) is set to '1'. Therefore, the delay time A is the sum of the delay time in the ring 1 and the delay time in the shift register 41.

As described above, the processing device 31 is connected to the LAN in a frame receiving state in which the received signal can be repeated.

(C) When the connection connector 8 is disconnected while a message from another device is passing through the connection device 21 (Fig. 4 (C)) In the same way as in the case (A) above, the signal ■ connects to the first data path. It is output as a signal ■ via the signal.

If the connector 8 is disconnected from the connection device 21 (cutting the cable) at an arbitrary timing in this state, the signal (2) is interrupted at this point, and the connection device 21 is no longer powered by the signal. That is, the processing device 31 is separated from the ring 1.

As a result, the signal ■ becomes "0" indicating a mismatch.

The signal ■ becomes 10”.

This makes AND gate 5, which has been valid up until this point,
The output of AND gate 51 is made invalid, while the output of AND gate 51 is made valid. Therefore, the switch circuit 5 selects the signal ■ instead of the signal ■.

This is output as a signal ■. Since the delay times of the signals ■ and ■ with respect to the signal ■ are equal, data continuity is maintained, and there is no change in the message on the ring 1 as seen from the downstream device.

The above can be similarly applied when an abnormality occurs in the processing device 31 other than the cable being disconnected, and the signal (2) cannot be correctly repeated. That is, at the point when the signal is no longer being repeated correctly, the signal (2) changes to "0", and the switch circuit 5 operates so that the signal (2) is selected, thereby guaranteeing the transmission on the ring 1.

Conversely, the message is sent to the shift register 41 (second data path)
Similarly, when the connection connector 8 is connected to the connection device 21 (the processing device 31 is connected to the ring 1) while passing through the connection device 21 via the connection device 21, the message on the ring l can be guaranteed. That is, after the delay time in the processing device 31 has elapsed since the connection, the processing device 31 starts outputting the signal ■ which is a correct repeat of the signal ■. At this point, the signal ■ changes to "L", and the signal ■ is selected instead of the signal ■, and is output as the signal ■.

(D) When the processing device 31 has been transmitting for longer than the specified time (Fig. 4 (D)) In the same manner as in the case (B) above, the processing device 31 first transmits the message (signal ■). conduct.

In this state, if the signal ■ is kept at “1” for more than the specified time,
The timer 62 detects this as a timeout and outputs the signal ■
The output of the comparison circuit 61 (signal ■) is made valid by setting the signal {circle around (2)} to "0" regardless of the "l" level.

At this time, the signal (2) is delayed from the signal (2) by the sum of the delay time in the ring 1 and the delay time in the shift register 41. Therefore, the signal (2) remains at "0", and as a result, the signal (2) becomes "0".

As a result of the above, the signal ■ is selected and output as the signal ■, but this is treated as invalid data. Therefore, the processing device 3
1 is separated from Sing 1 as an abnormality has occurred,
Returns to Ring 1 after being repaired.

The same applies when an abnormality occurs in the connection request signal line between the processing device 3I and the connection device 21 and the signal ■ remains at "1 degree."

〔Effect of the invention〕

As explained above, according to the present invention, a ring type LAN
By providing two transmission paths with equal delay times in connection devices, when a processing device is connected to or disconnected from a ring, there is no effect on the ring, that is, other processing devices.
Since the data on the ring can always be guaranteed, there is no reduction in throughput due to data retransmission.
It is possible to prevent the reliability of N from decreasing.

FIGS. 2 and 3 are configuration diagrams of the embodiment.

Figure 4 is a waveform diagram.

FIG. 5 is an explanatory diagram of the prior art.

■ is a closed ring-shaped transmission line (ring), 21 or 2
4 is the first to fourth connection devices, 31 to 34 are the first to fourth processing devices, and 4 is the delay circuit 5 is a switch circuit.

Patent applicant BFF Co., Ltd. Attorney Mori 1) Hirugu and 2)

[Brief explanation of drawings]

Figure 1 is a diagram of the principle configuration of the present invention. Principle configuration diagram of the present invention Figure 1 Meishetsu tank precept (?) Figure 2 Practical example configuration diagram (a) East map 3 Conventional four-branch explanation diagram Chart 5 (A) Wave shape diagram Figure 4 (I)

Claims (1)

[Claims] A ring-type LAN connecting device (
In 21 to 24), the signal taken in from one end of the transmission path is input to a processing device (31 to 34), and the corresponding output signal of the processing device (31 to 34) is output from the input. a first data path for outputting a signal delayed by a predetermined time to the other end of the transmission path; and a data path short-circuiting one end and the other end of the transmission path, the data path comprising: a delay circuit (4) having a delay time substantially equal to the delay time in 34);
and a second data path formed by inserting a ring-type LAN connection device.