JPH02105615A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To control a rise time and a fall time and to suppress the generation of overshoot and undershoot by sampling an output signal by a shift register and an oscillator, and driving an output circuit by a sampling signal. CONSTITUTION:Sampling is performed by applying a signal from a terminal A and by using the shift register 3 and the oscillator 2. The title circuit is controlled by switching the output circuit 1 sequentially by a sampled input signal, and controlling the peak value of a transient current that flows at the time of switching by controlling the frequency of the oscillator 2. In such a way, the rise time and the fall time can be controlled and furthermore, fast driving capacity can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor integrated circuits, and in particular, to semiconductor integrated circuits connected in series.
The present invention relates to a semiconductor integrated circuit having a plurality of output circuits consisting of channel MoS transistors and N-channel MOS transistors.

[Conventional technology]

Conventionally, this type of semiconductor integrated circuit has a plurality of output circuits 11 connected in parallel, each including a P-channel type MOS transistor QP2 and an N-channel type MOS transistor QN2 connected in series, as shown in FIG. 3. Alternatively, as shown in Fig. 4, a plurality of output circuits 1, each consisting of a series-connected P-channel type MOS transistor Qpt and an N-channel type MOS transistor Qst, which are slow in rising and falling, are connected in parallel. , the gate input of each output circuit 1 is configured to delay the rise and fall times by providing signals sequentially delayed by a delay block 7 having a predetermined amount of delay.

[Problem to be solved by the invention]

The conventional semiconductor integrated circuits described above are designed not only to achieve high-speed driving, but also to delay the rise and fall times by connecting a fixed amount of delay, making it impossible to control the rise and fall times. Na. Therefore, there is a drawback that countermeasures against the occurrence of overshoot, undershoot, etc. are insufficient.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a plurality of output circuits, each of which is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in series, each of which is connected in parallel, an oscillation circuit that generates a timing pulse, and a timing pulse. A plurality of flip-flops shifted by a pulse are connected in series, and the output of each of the flip-flops is supplied to a gate input of the output circuit, and an external input signal is supplied to a data input terminal of the first stage of the flip-flop. It is configured to include a shift register.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

As shown in FIG. 1, the first embodiment includes a plurality of output circuits in which a P-channel MOS transistor QPI and an N-channel MOS transistor QN+ are connected in series, each of which is connected in parallel and has slow rise and fall. 1, an oscillation circuit 2 that generates a timing pulse, and an output circuit 1 that outputs each of the flip-flops in which a plurality of flip-flops sampled by the timing pulse are connected in series.
A shift register 3 is supplied with an input signal from a terminal A, which is supplied to the gate/input of the flip-flop, and the output of the internal circuit of the semiconductor integrated circuit is supplied to the data input terminal of the first stage of the flip-flop; It is configured to include an attached resistor 4 and a capacitor 5.

In the first embodiment, a signal is applied from the terminal A and sampled by the shift register 3 and the oscillator 2. The output circuit 1 is sequentially switched by the sampled input signal, and the peak value of the transient current flowing during switching is determined. is controlled by controlling the frequency of the oscillator 2. This controls the rise and fall times and provides even higher speed drive capability.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

As shown in FIG. 2, in the second embodiment, the output circuits 1 connected in parallel are sequentially driven by an output signal from a shift register 36 sampled by an oscillator 2 and a shift register 31. However, the output circuit 1 to be driven last is driven by the previous stage drive signal through the delay block 7 having a predetermined delay amount.

Also in the second embodiment, the sampling period is controlled by controlling the frequency of the oscillator 2, so the rise and fall times can be controlled.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by sampling the output signal using a shift register and an oscillator and driving the output circuit with the sampling signal, the rise and fall times can be controlled, and even higher drive capability can be achieved. There is. Furthermore, this has the effect of suppressing the occurrence of overshoot and undershoot.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIGS. 3 and 4 are a circuit diagram of a conventional semiconductor integrated circuit, respectively. FIG. 3 is a circuit diagram of a second example. 1.1. ...output circuit, 2...oscillation circuit, 3,3゜...shift register, 4...external resistor, 5...
Capacitor, 6... Inverter block that makes signals in phase, 7, 7. ...delay block, QPI, QNI・
...delayed rise and fall MOS transistor, QP21
QN2... MOS transistor with fast rise and fall.

Claims (1)

[Claims] A plurality of output circuits connected in parallel are each constructed by connecting a P-channel MOS transistor and an N-channel MOS transistor in series, an oscillation circuit that generates a timing pulse, and a plurality of flip-flops that are shifted by the timing pulse. a shift register in which flip-flops are connected in series, each output of the flip-flop is supplied to a gate input of the output circuit, and an input signal from the outside is supplied to a data input terminal of the first stage of the flip-flop. Semiconductor integrated circuit.