JPH02105238A - Microcomputer - Google Patents

Abstract

PURPOSE:To perform program loading with an initial program loader (IPL) ROM with bit width smaller than that of data and to realize cost reduction by providing an address generation circuit and plural registers, etc. CONSTITUTION:In the case of loading an application program with the IPL ROM 3 with bit width of eight bits on a RAM 5 with bit width of 16 bits, the address generation circuit 2 generates the address A of the ROM 3, and makes access to the address A of the ROM 3. The data '0' of eight bits at the address A is read out of the ROM 3, and it is latched at the registers 4a(D15-D8) by the output of a strobe *0 from the circuit 2. Next, the circuit 2 generates an address (A+1), and makes access to the ROM 3, and the data 1 with bit width of eight bits is read out from the ROM 3, and it is latched at the registers 4b(D7-D0) by the output of a strobe *1 from the circuit 2. In such a way, the data D15-0 with bit width of 16 bits are arranged, and an IPL processing with bit width of 16 bits can be performed by the ROM 3 with bit width of eight bits, which reduces a cost.

Description

Detailed Description of the Invention (Field of Industrial Application) This invention relates to microcomputers (hereinafter abbreviated as microcomputers), and in particular, even as the data bit width of microcomputers increases to 16 bits, 32 bits, and 64 bits, This invention relates to a microcomputer that can use an IPL (initial program loader) ROM with a smaller bit width.

(Prior Art) In recent years, the data bit width of microcomputers has increased from the conventional 8 bits to 16 bits, 32 bits, and 64 bits.

The microcomputer system is a disk (HDD).

When the computer has an external storage device such as an FDD (FDD, etc.), the application program is usually stored in the disk. The microcomputer executes the application program during operation, but before starting operation, such as when the power is turned on, the application program is transferred from the external storage device to the memory (RAM) in the microcomputer, and the program is stored in the memory. The application program is used to perform the necessary operations.

When transferring this application program from the external storage device to the RAM in the microcomputer, the
OM, I stored in (EFROM%FROM etc.)
PL is used. In other words, when the power is turned on, the RO
The IPL stored in M is read out, and the CPU operates in accordance with the IPL, thereby reading out the application program from the external storage device and loading it into the RAM.

(Problem to be Solved by the Invention) The ROM is a program (IP
Since it is sufficient to store the number L), a memory with a walking capacity of divisors, tens of paitors, and bytes is sufficient.

However, as mentioned above, the data bit width of the microcontroller is
As the size of the ROM (hereinafter referred to as IPL) increases from the conventional 8 bits to 16 bits, 32 bits, and 64 bits,
In order to match the data bit width of 8-bit IPL ROMs (referred to as ROMs), for example, two, four, or
There is a problem in that a large number of 8 pieces are required, and there is a storage area that is not used in the IPL ROM, resulting in a large amount of waste. Furthermore, this also led to the problem of increased costs. Note that, at present, 8-bit ROMs are often used as IPLROMs.

The purpose of the present invention is to eliminate the problems of the prior art described above,
IPL with a bit width smaller than the data bit width of the microcontroller
By providing a system that can use a ROM, it is possible to eliminate waste of the storage area of the IPL ROM and thereby reduce costs.

(Means and Effects for Solving the Problems) In order to achieve the above object, the present invention stores an IPL in a ROM having a data bit width smaller than the data bit width of the microcomputer, and stores the IPL when the microcomputer is powered on. The feature is that the IPL is run and the application program stored in the external storage device is loaded into the RAM in the microcomputer.

According to the present invention, since the IPL ROM uses a memory that has enough capacity to load the IPL from the external storage device to the RAM, the unused storage area can be kept to a minimum, resulting in large waste. It can be expected that this will not occur. Also, IPL R
Since the number of OMs can be reduced, costs can be reduced.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, 1 is, for example, a 16-bit wide CPU.

2 is an address generation circuit that receives an address signal from the CPUI, and 3 is, for example, an 8-bit wide IPL ROM 54.
a is the 8-bit data (I
The first register, 4b, holds the PL program).
is the second register.

Further, 5 is a RAM having a width of, for example, 16 bits, in which application programs, data, etc. are stored. 6 is an external storage device interface, and 7 is an external storage device consisting of a disk or the like.

FIG. 2 shows a conceptual diagram of data stored in the IPL ROM 3. As shown, IPL
ROM3 has a data bit width of 8 bits and stores an IPL program.

As mentioned above, in this embodiment, even though the data bit width of the microcontroller is 16 bits, the IPL
ROM3 has a data bit width of 8 bits.

Next, the operation of this embodiment will be explained with reference to FIGS. 1 and 2.

When the power is turned on, the CPU of the microcomputer executes IPL and loads the application program stored in the external storage device 7 into the RAM 5. Specifically, when the CPUI accesses the address generation circuit 2, the address generation circuit 2 generates the address A of the IPL ROM 3, and accesses the address A (see FIG. 2) of the IPL ROM 3. The IPL
8-bit data 0 at address A is read from ROM3. At this time, the address generation circuit 2 outputs strobe *0, so the first register 4a (D15 to
The data 0 is latched in D8). Next, the address generation circuit 2 generates the address A+1, and the IPL ROM
3 accesses address A+1. For this reason, I
8-bit width data 1 is read from the PL ROM 3, and a strobe*1 is output from the address generation circuit 2. As a result, the second register 4b (D7 to D
Data 1 is latched in O).

IPL R to the first and second registers 4as4b
When the data from OM3 is latched, the address generation circuit 2 returns a DTACK signal to the CPUI, notifying it that the 16-bit wide data D15 to DO are complete. C.P.
When the UI receives the DTACK signal, it reads this data and executes one step of IPL.

Next, when the address signal is output from the CPUI to the address generation circuit 2 again, the address generation circuit 2 generates the address A+2. With this, IPL ROM3
8-bit width data 2 is read from. At this time, since the strobe value 0 is output from the address generation circuit 2, the data 2 is latched in the first register 4a. Next, address generation circuit 2 generates address A+3. As a result, from IPL ROM3, 8
Bit width data 3 is read out. At this time, since the strobe *1 is output from the address generation circuit 2, the data 3 is latched into the second register 4b.

When the data 2.3 is latched into the first and second registers 4a14b, the address generation circuit 2 sends the DTA to the CPUI.
Returns the CK signal and sends 16-bit wide data D15 to DO
Let me know when the items are complete.

When the CPUI receives the DTACK signal, it reads this data and executes the next step of IPL.

The above operations are sequentially repeated, and the application program stored in the external storage device 7 is loaded into the RAM 5 through the external storage device interface 6. When all of the application programs are loaded into the RAM 5, the CPUI executes the application programs on the RAM.

As described above, according to this embodiment, although the microcontroller is configured with a 16-bit width, one 8-bit wide I/O
It is possible to use a PL ROM, eliminate waste of storage area, and reduce costs.

Note that in the above embodiment, two registers are used, but the present invention is not limited to this, and only one register may be used.

That is, only the first register 4a may be provided and the second register 4b may be removed.

In this case, data D15 to D are stored in the first register 4a.
8 is latched, and data D7 to DO are IPL ROM3.
Of course, it is possible to read it directly from .

Furthermore, in the above embodiment, the microcontroller is configured with a width of 16 bits, but the microcontroller is configured with a width of 32 bits,
It is clear that the present invention can also be applied to a case where the data is configured with a width of 64 bits or the like.

In the case of a 32-bit wide microcontroller, an 8-bit wide IP
One L ROM and three or four 8-bit wide registers for temporarily storing data read from the IPL ROM are used. or 16-bit wide IPL
One ROM is used, and one or two 16-bit wide registers are used to temporarily store data read from the IPL ROM.

In addition, in the case of a 64-bit wide microcontroller, there is one 8-bit wide IPL ROM and seven 8-bit wide registers for temporarily storing data read from the IPLROM.
Use 1 or 8 pieces.

Alternatively, one 16-bit wide IPL ROM is used, and three or four 16-bit wide registers are used to temporarily store data read from the IPL ROM.

Generally speaking, in the case of an M-bit wide microcontroller,
Using one IPL ROM with a data width of N bits smaller than this, M/N (-integer) or ((M/N)-
Eleven N-bit data width registers are used.

Furthermore, depending on the type of CPU, the address generation circuit 2 may output a WAIT release signal or response ACK signal suitable for the CPU instead of outputting the DTACK signal. Of course, the following effects can be obtained.

(Effects of the Invention) According to the present invention, even if the data bit width of microcontrollers increases from 16 bits to 32 bits to 64 bits, one IPL ROM with a small bit width can be used. , IPL is a program with a relatively small capacity, so it has the effect of not creating a wasted storage area in the IPLROM and helping to reduce the cost of the microcomputer.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a conceptual diagram of data stored in the IPL ROM shown in FIG. 1...CPU, 2...Address generation circuit, 3-RO
M, 4 a, 4b--first and second registers, 5...
・RAM, 7...External storage device agent Patent attorney Michito Hiraki and 1 other person 7 ν V country

Claims (1)

[Claims] (1) CPU, RAM, external storage device and IPLRO
In a microcomputer having a data width of M bits (M is an integer), the CPU and the RA
An IPLROM with a data width of N bits (N is an integer) smaller than M data bit width M, and M/N (=integer) or {(M/N)-1} IPLROMs with the same data bit width as the IPLROM. A microcomputer characterized by comprising a register.