JPH02104445U - - Google Patents
Info
- Publication number
- JPH02104445U JPH02104445U JP1383989U JP1383989U JPH02104445U JP H02104445 U JPH02104445 U JP H02104445U JP 1383989 U JP1383989 U JP 1383989U JP 1383989 U JP1383989 U JP 1383989U JP H02104445 U JPH02104445 U JP H02104445U
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- interrupt request
- mask information
- request
- mask register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 1
Description
第１はこの考案の一実施例による割込要求処理
回路の構成を示すブロツク図、第２図は同実施例
の動作を示すタイムチヤート、第３図は従来の一
般的な割込マスク機能を有するプロセツサの動作
を説明するブロツク図、第４図は割込要求信号を
レベルセンスするタイプのプロセツサの動作を示
すタイムチヤート、第５図は割込要求信号をエツ
ジセンスするタイプのプロセツサの動作を示すタ
イムチヤートである。
ＩＲＱ１〜ＩＲＱｎ……割込要求信号、ＭＡＳ
Ｋ１〜ＭＡＳＫｎ……割込マスク情報、１１……
割込マスクレジスタ、１２……スタツクレジスタ
、１３……割込要求認識プログラム、１４……割
込要求処理プログラム。
1 is a block diagram showing the configuration of an interrupt request processing circuit according to an embodiment of this invention, FIG. 2 is a time chart showing the operation of the same embodiment, and FIG. 3 is a diagram showing the conventional general interrupt masking function. 4 is a time chart showing the operation of a type of processor that senses the level of an interrupt request signal, and FIG. 5 shows the operation of a type of processor that senses the level of an interrupt request signal. It is a time chart. IRQ1 to IRQ n ...Interrupt request signal, MAS
K1~MASK n ...Interrupt mask information, 11...
Interrupt mask register, 12...Stack register, 13...Interrupt request recognition program, 14...Interrupt request processing program.
Claims (1)
応した記憶領域を有し、前記各記憶領域には当該
割込要求を拒否するか否かを示す割込マスク情報
が記憶される割込マスクレジスタを備え、前記割
込要求信号が所定のレベル変化をし、かつ、当該
割込マスク情報が割込要求を許可することを示す
場合に、当該割込処理を実行するプロセツサにお
いて、 前記割込マスクレジスタの割込マスク情報の一
時退避用のスタツク手段と、 前記割込要求信号を検知する割込要求検知手段
と、 前記割込要求信号のレベル変化が検知された場
合に当該割込処理を起動し、該割込処理が完了し
た時点で、前記割込マスクレジスタ内の割込マス
ク情報を一旦前記スタツク手段に退避させた後、
前記割込マスクレジスタに割込要求を拒否する割
込マスク情報を書き込み、次いで前記退避された
割込マスク情報を前記割込マスクレジスタに再度
書き込む割込要求処理手段と を具備することを特徴とする割込要求処理回路
。[Claims for Utility Model Registration] It has a storage area corresponding to each of the interrupt request signals from a plurality of interrupt causes, and each storage area has an interrupt signal indicating whether or not to reject the interrupt request. An interrupt mask register is provided in which mask information is stored, and when the interrupt request signal changes a predetermined level and the interrupt mask information indicates that the interrupt request is permitted, the interrupt processing is performed. A processor that executes the above comprises: a stack means for temporarily saving interrupt mask information in the interrupt mask register; an interrupt request detecting means for detecting the interrupt request signal; and a change in level of the interrupt request signal. when the interrupt processing is completed, and once the interrupt mask information in the interrupt mask register is saved in the stack means,
Interrupt request processing means writes interrupt mask information for rejecting an interrupt request in the interrupt mask register, and then writes the saved interrupt mask information in the interrupt mask register again. interrupt request processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1383989U JPH074669Y2 (en) | 1989-02-08 | 1989-02-08 | Interrupt request processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1383989U JPH074669Y2 (en) | 1989-02-08 | 1989-02-08 | Interrupt request processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02104445U true JPH02104445U (en) | 1990-08-20 |
| JPH074669Y2 JPH074669Y2 (en) | 1995-02-01 |
Family
ID=31224499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1383989U Expired - Lifetime JPH074669Y2 (en) | 1989-02-08 | 1989-02-08 | Interrupt request processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH074669Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008129668A (en) * | 2006-11-17 | 2008-06-05 | Meidensha Corp | Interrupt control system of cpu |
-
1989
- 1989-02-08 JP JP1383989U patent/JPH074669Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008129668A (en) * | 2006-11-17 | 2008-06-05 | Meidensha Corp | Interrupt control system of cpu |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH074669Y2 (en) | 1995-02-01 |
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