JPH02104070A - Television receiver - Google Patents

Abstract

PURPOSE:To reduce the movement of a main signal on a television screen by providing a variable delay circuit, a reference synchronizing signal generating circuit and a time difference detection circuit, detecting a time difference between the synchronizing signal in a television signal and a reference synchronizing signal and controlling the delay in the variable delay circuit. CONSTITUTION:The receiver is provided with a variable delay circuit 104 retarding a television signal detected at a video detection circuit 104 variably and giving an output to a next stage, a reference synchronizing signal generating circuit 106 generating a reference synchronizing signal synchronously with the synchronizing signal included in the television signal and a time difference detection circuit 105 detecting a time difference between the reference synchronizing signal and a synchronizing signal having a maximum amplitude when plural synchronizing signals are included in one period of the synchronizing signal of the television signal and controlling a delay of the variable delay circuit 104 in response to the time difference. Thus, the reception is implemented smoothly without being attended with movement of picture and disturbing the synchronization and an excellent picture is maintained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a television receiver. Regarding a television receiver suitable for in-vehicle use, which allows the screen to be displayed properly without confusing the screen even if a situation occurs where the ghost appears stronger than the original main signal due to It is something.

(Prior Art) Conventionally, as an in-vehicle television receiver, an example disclosed in Japanese Patent Application Laid-Open No. 56-10780 has been known.

In this conventional example, four guivacity antennas mounted on a mobile body are selected, and any one of the outputs of these antennas is selected to create an antenna input circuit for a television receiver mounted on the mobile body. a switching circuit that switches the switching circuit so as to be connected to the antenna, and a sampling switching control signal generated within the vertical retrace period of the television video signal to switch the switching circuit in a time-sharing manner, and compare the levels of the detection output of each antenna; A control circuit is provided so that the antenna with the highest level is connected to the antenna input circuit of the television receiver, and thereafter maintains this state until the next vertical retrace period. It is designed to always maintain optimal reception conditions even if the reception environment changes.

[Problem to be solved by the invention] This type of conventional technology can select and receive the input wave with the maximum electric field strength by switching the antenna at any time, so it works well when the reception environment is relatively good. images can be seen on the screen. However, in an environment where there are many buildings in the center of a city and where ghosts occur frequently, there is a problem that the effect cannot be fully demonstrated for the following reasons.

If a ghost exists, the ghost situation generally changes as the car moves. Therefore, as a result of the amplitude level of the ghost becoming very large, the ghost becomes the main signal, and the main signal up to that point may be regarded as a ghost. This means:

In other words, when switching from the previous main signal to a signal that was a ghost signal and will now become the main signal and display it on the screen, there will naturally be a time difference between the previous main signal and the future main signal. A discrepancy occurs. The synchronization circuit of the receiver always follows the currently input main signal in synchronization, but if there is a time lag between the previous main signal and the next main signal, the receiver's synchronization circuit will instantly follow the main signal that is currently being input. cannot follow, and operates with a certain time constant. Therefore, during this time, a discrepancy occurs between the video signal and the synchronization signal created by the synchronization circuit, resulting in video distortion.

An object of the present invention is to solve the drawbacks of the prior art, and to solve the problem that the ghost becomes stronger than the original main signal due to changes in the reception environment, and the ghost becomes the main signal from now on instead of the previous main signal. It is an object of the present invention to provide a television receiver particularly suitable for use in a vehicle, which enables appropriate display without disturbing the screen even if a situation in which images are captured occurs.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a tuner for the received signal.
In a television receiver that converts a video intermediate frequency signal through a frequency conversion circuit and detects it in a video detection circuit to obtain a television signal and display it on a screen, a variable delay circuit, a reference synchronization signal generation circuit, , and a time difference detection circuit.

[Function] The present invention provides a television receiver that converts a received signal into a video intermediate frequency signal through a tuner and a frequency conversion circuit, and detects it in a video detection circuit to obtain a television signal and display it on a screen. , the variable delay circuit variably delays the television signal detected in the video detection circuit and outputs it to the next stage, and the reference synchronization signal generation circuit generates a reference synchronization signal synchronized with a synchronization signal included in the television signal. When a plurality of synchronization signals are included in one period of the synchronization signal in the television signal, the time difference detection circuit detects the time difference between the synchronization signal having the maximum amplitude among the synchronization signals and the reference synchronization signal. is detected, and the amount of delay in the variable delay circuit is controlled according to the time difference.

As a result, a ghost with a larger amplitude level than the previous main signal appears, and when this ghost is taken in as a future main signal instead of the previous main signal, the phenomenon in which the main signal moves on the TV screen is reduced. be able to.

〔Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 101 is an antenna, 102 is a tuner circuit, 108 is a frequency conversion/amplification circuit, 103 is a video detection circuit, 104 is a variable delay circuit, 105 is a time difference detection circuit,
106 is a reference synchronization signal generation circuit, and 107 is a video signal output terminal.

FIG. 2 is a schematic diagram of various signals in the circuit of FIG. 1. In FIG. 2, 201 is the output signal (TV signal) of the video detection circuit 103, and 202 is the reference synchronization signal generation circuit 10.
6 is the output signal (reference synchronization signal), 203 is the output signal of the time difference detection circuit 105, and 204 is the output signal of the variable delay circuit 104.

The circuit operation will be explained with reference to FIGS. 1 and 2.

The received signal input from the antenna 101 is sent to the tuner circuit 1.
021 Frequency conversion/amplification circuit 108. Video detection circuit 10
3 in order to obtain a television signal 201. TV signal 2
01, the solid line is the original signal (main signal), and the broken line is the ghost signal added due to the ghost phenomenon. Here, a human image M, its ghost Ma, and a synchronization signal SY and its ghost SYa are shown.

The synchronization period T between the signal 202 generated by the reference synchronization signal generation circuit 106 to be synchronized with the synchronization signal included in the television signal 201 and the output signal 201 of the video detection circuit 103
A time difference detection circuit 105 detects the time difference between the maximum level of the synchronization signal and a signal 203. During the synchronization period A, the synchronization signal SYa is the ghost of the synchronization signal S
The level is higher than Ya, and in the synchronization periods B and C, the level of the synchronization signal 5YaO, which is a ghost of the synchronization signal SY, is higher than that of the synchronization signal SY. Therefore, the synchronization signal targeted for time difference detection is SY in period A, and SY in periods B and C.
It is a.

Further, if the variable delay circuit 104 delays the input signal 201 only during the period when the control signal 203 is ``high'', the signal 204 can be obtained as an output.

Conventionally, the detection output signal 201 was output as a video signal, so the original signal was stronger than the ghost signal A.
At the switching point from the region to the B region where the ghost signal is stronger than the original signal, a time lag occurs between the synchronization signal SY of the original signal and the synchronization signal SYa of the ghost. The synchronization circuit of the receiver always follows the currently input synchronization signal in synchronization, but when the synchronization signal SY is switched to the ghost synchronization signal SYa, SYa
It cannot follow instantaneously, but follows with a certain time constant. Therefore, during this time, there will be a discrepancy between the video signal and the synchronization signal created by the synchronization circuit, and the video will be distorted.

However, according to this embodiment, the reference synchronization signal generation circuit 106
Since the timing of the synchronization signal having the highest level among the synchronization signals within the synchronization period T is matched with the synchronization signal generated in the synchronization period T, the synchronization is not disturbed.

Furthermore, if the synchronization signal is simply used as the timing of the signal 202, when switching from area A to area B in FIG.
In the A area, the image based on the original main signal is considered as the main signal, and in the Bnl area, the image based on the ghost signal is considered as the main signal, so the phenomenon that the image appears to move on the TV screen occurs, but in this example, the entire TV signal is Since the delay is controlled by the variable delay circuit 104, this type of image movement phenomenon is also reduced.

FIG. 3 is a block diagram showing another embodiment of the present invention.

Each component circuit in the figure is the same as that in FIG. 1. The difference from the embodiment shown in FIG. 1 is that the delay correction is of a feedforward type, whereas the synchronization signal generation circuit 1
The point is that the television signal on which the time difference is detected between the output signal of 06 and the output signal of 06 is a feedback type television signal that has been delayed by the variable delay circuit 104.

The embodiment shown in FIG. 3 has the effect of reducing synchronization disturbances and image movement phenomena at the time of switching, similar to the embodiment shown in FIG.

FIG. 4 is a block diagram showing a specific example of the time difference detection circuit 105 in FIG. 1. In the figure, 401 is an input terminal for the output signal of the video detection circuit 103 in FIG.
2 is an input terminal for the output signal of the reference synchronization signal generation circuit 106 in FIG. 1, 403 is a horizontal synchronization signal detection circuit, 404 is a differentiation circuit, 405 is a level comparison circuit, 406 is a maximum level storage circuit, 407 is an output terminal, It is.

FIG. 5 is a schematic diagram of signals of each part in the circuit of FIG. 4. In FIG. 5, 501 is the output signal (input signal to the input terminal 401) of the video detection circuit 103 of FIG. Output signal of synchronization signal generation circuit 106 (input terminal 4
02 input signal), 503 is a horizontal synchronization detection circuit 403
504 is the output signal of the level comparison circuit 405, 505 is the maximum level output signal of the maximum level storage circuit 406, and 506 is the time difference output signal of the maximum level storage circuit 406.

The circuit operation will be explained with reference to FIGS. 4 and 5.

Video detection circuit 1 of FIG. 1 inputted from input terminal 401
From the output signal 501 of 03, only the horizontal synchronization signal is extracted by the horizontal synchronization detection circuit 403 to obtain the signal 503. A differentiation circuit 404 extracts only the falling edge of the signal 503. A level comparison circuit 405 compares the level of the output signal of the differentiating circuit 404 and the level of the signal stored in the maximum level storage circuit 406, and only when the level of the output signal of the differentiating circuit 404 is high, the output signal of the differentiating circuit 404 is compared. is output, and a signal 504 is obtained.

The maximum level storage circuit 406 is reset at the falling edge of the output signal 502 of the reference synchronization signal generation circuit 106 shown in FIG. The signal level of the output signal 504 of the circuit 405 and the input time are stored,
The input signal level is held until a new input signal is input, and the signal 505 is output to the level comparison circuit 405.

Further, a time difference signal 506 corresponding to the time at which the maximum signal level is input within the -horizontal scanning period is outputted from the output terminal 407 to the variable delay circuit 104 in FIG. 1.

Note that this time difference signal 506 is output after being delayed by -horizontal scanning period with respect to the input signal 501, so that the variable delay circuit 104 in FIG. A delay circuit for the scanning period is required.

Further, in FIG. 5, there may be a case where the horizontal synchronization signal of the input signal 501 is corrupted by noise due to the addition of a ghost, etc., and the horizontal synchronization signal cannot be detected by the horizontal synchronization detection circuit 403 in FIG. In such a case, always monitor the time of the maximum horizontal synchronization signal level for a certain number of horizontal scanning periods, and detect the time when the maximum horizontal synchronization signal level occurs the most among those times,
If the time difference signal 506 is generated based on this, it is possible to make it resistant to disturbances such as noise.

FIG. 6 is a 1-bronch diagram showing another specific example of the time difference detection circuit 105. In the figure, 601 is a vertical synchronization signal detection circuit, 602 is a timing recovery circuit, 603, 60
4 is a gate circuit. Also, the same reference numerals as in FIG. 4 indicate the same functions.

The difference between the example shown in FIG. 6 and the example shown in FIG. The point is that the gate circuits 603 and 604 are controlled so that the input signal passes only during the blanking period.

That is, since the video signal within the vertical blanking period does not include image information and is only a synchronization signal, even if a ghost is added, the image information will not interfere with the synchronization signal. Therefore, according to this example, the maximum signal level of the horizontal synchronization signal can be easily detected.

In addition, in this example, since the horizontal synchronization signal within the vertical retrace period is used, the time axis correction of the horizontal synchronization signal is performed with a vertical interval of 3tlI.
It will be for each period.

FIG. 7 is a diagram showing another specific example of the time difference detection circuit 1050. In the figure, 701 is a character multiplex signal detection L (waste 1 path). The same reference numerals as in FIGS. 4 and 6 indicate the same functions.

The difference between the example shown in FIG. 7 and the example shown in FIG. This is a character multiplexed signal (a character signal that is multiplexed within the vertical retrace period of the television signal, regardless of the television image).

FIG. 8 is an explanatory diagram of the operation of the specific example shown in FIG.

As shown in FIG. 8, the character multiplex signal is used for the 20th horizontal scanning line in odd fields within the vertical blanking period of the video signal.
In the even field, the 283rd line is multiplexed, and since the time τQ from the horizontal synchronization signal to the start position of the character multiplex signal is constant, even in this example where the character multiplex signal is used as the reference signal. , can perform the function of time difference detection similarly to the example of FIG.

For teletext signals, please refer to the Special Publication Publication No. 63-9437.
Publication No. 1 and the Technical Report of the Society of Television Engineers published on May 25, 1988, ``Study of C36i-3r character code broadcasting system''
etc. are listed.

FIG. 9 is a block diagram showing still another specific example of the time difference detection circuit 105. In the figure, 901 is a time difference correlation detection circuit. Figures 4 and 6.

The same reference numerals as in FIG. 7 indicate the same functions.

(The subscript aL(b) is used to indicate route distinction.

The difference from the specific example shown in Fig. 4 is that there are two types of standard A words, a horizontal synchronization signal and a character multiplex signal, and two types obtained from the maximum level storage circuit 4.06 (a) and (b). The time difference correlation detection circuit 901 outputs the most suitable time difference signal to the output terminal 407 by using the time difference No. 8 having different periods.

According to this example, a more stable time difference signal can be output, and a more stable image can be obtained.

Next, a specific example of the iJ variable delay circuit 104 in the embodiment of FIG. 1 is shown in FIG. In Figure 10, 100
1 is an input terminal to which the output signal of the video detection circuit 103 shown in FIG. 1 is input, 1002 is an input terminal to which the output signal of the time difference detection circuit 105 of FIG.
Delay circuit for delaying the signal input from 01, 1004
1005 is a switching circuit, 1005 is a switching control circuit, and 1006 is a delay signal output terminal.

A detected output signal input from input terminal 1001 is input to delay circuit 1003. The delay circuit 1003 is provided with taps for each fixed amount of delay, and each of the taps is connected to a switching circuit 1004. Switching control circuit 100
5 selects an appropriate number of taps of the switching circuit 1004 according to the time difference signal inputted from the input terminal 1002, extracts an appropriately delayed video signal, and outputs it from the output terminal 1006.

FIG. 11 is a block diagram showing another specific example of the variable delay circuit 104. 1101 is the detection circuit 1 of the embodiment shown in FIG.
1102 is an input terminal to which the output signal of the time difference detection circuit 105 shown in FIG. 1 is input; 1103 is an A/D converter; 1104 is a delay circuit;
05 is a D/A converter, 1106 is a switching circuit, 1107 is a switching control circuit, and 110 is a video signal output terminal.

The detection output signal input from the input terminal 1101 is A/D
The signal is converted into a digital signal by a converter 1103 and inputted to a delay circuit 1104 composed of a tapped shift register. The switching control circuit 1107 selects an appropriate number of taps for the switching circuit 1106 in accordance with the time difference signal input from the input terminal 1102, and takes out an appropriately delayed digital signal.

The extracted delayed digital signal is sent to the D/A converter 110.
5, it becomes an analog video signal and outputs it to the output terminal 11.
It will be output from day 0.

Note that it is also possible to use a memory instead of the delay circuit 1104 and to vary the amount of delay by controlling read/write addresses.

Next, a specific example of the reference synchronization signal generation circuit 106 in FIG. 1 is shown in FIG. 12. In FIG. 12, 1201
1 is an input terminal for inputting the output signal of the variable delay circuit 104 in FIG. 1, 1202 is a synchronous separation circuit, 1203 is a gate circuit, 1204 is a burst gate circuit, 1205 is a burst lock PLL circuit, 1206 is a timing generation circuit, and 1207 is a It is an output terminal.

A horizontal synchronization signal including a color burst is separated and extracted by a synchronization separation circuit 1202 from the output video signal of the variable delay circuit 104 in FIG. 1 inputted from an input terminal 1201. The gate circuit 1203 outputs the output signal of the sync separation circuit 1202 only when the timings of the horizontal sync signal obtained by the sync separation circuit 1202 and the horizontal sync signal obtained by the timing generation circuit 1206 match. A burst gate circuit 1204 extracts a color burst signal from the output signal of the gate circuit 1203 and outputs the color burst signal to the burst lock PLL circuit 12.
05, a PLL is applied to the color burst signal taken out by the burst gate circuit 1204 as a reference, and a clock signal of, for example, 4 fsc (fsc is the color burst frequency) is obtained as an output. A timing generation circuit 1206 generates and outputs a horizontal synchronization signal based on the clock signal obtained by the burst lock PLL circuit.

According to this example, since a PLL loop is formed using the output video signal, a more stable synchronization signal can be generated. Furthermore, since the gate circuit 1203 prevents unstable reception synchronization signals from passing through, a stable synchronization signal can be generated.

In addition, by controlling the gate circuit 1203 within the vertical blanking period in accordance with the maximum level vertical synchronization signal of the received signal and passing the first maximum level horizontal synchronization signal as it is, the PLL circuit can be pulled in more quickly. It becomes possible. Furthermore, since the horizontal synchronization disturbance at this time occurs during the vertical retrace period, it is possible to prevent it from appearing on the television screen.

Still another embodiment of the present invention is shown in FIG.

In the figure, 1301 is an image signal separation circuit, 1302
is a synthetic circuit. The same reference numerals as in FIG. 1 indicate the same functions.

The difference between the embodiment shown in FIG. 13 and the embodiment shown in FIG.
301 and a combining circuit 1302 are provided. Image signal separation circuit 1301 removes the synchronization signal from the output video signal of variable delay circuit 104 and outputs only the image signal. The synthesis circuit 1302 combines the image signal from which the synchronization signal has been removed, obtained from the image signal separation circuit 1301, and the synchronization generation circuit I.
The synchronization signals obtained from 06 are synthesized and a video signal is output.

In the embodiment of FIG. 1, the reference synchronization signal generation circuit 10
The highest level synchronization signal of the received signal is detected every cycle of the synchronization signal obtained in step 6, and the timing of the detected maximum level synchronization signal and the synchronization signal obtained by the reference synchronization signal generation circuit 106 match. The received signal was delayed using a variable delay circuit. Therefore, since the synchronization signal level of the output video signal changes each time, the operation of the synchronization circuit of the display may become unstable.

However, in this embodiment, since the synchronization signal of the output video signal is obtained from the synchronization generation circuit 106, it is easy to keep the level constant, and the operation of the synchronization circuit of the display is stabilized. can be done. Therefore, according to this embodiment, synchronization can be further stabilized.

Still another embodiment of the present invention is shown in FIG.

In the figure, 1401 is an AGC (automatic gain control) circuit. The same reference numerals as in FIG. 1 indicate the same functions.

The difference from the embodiment shown in FIG. 1 is that the AGC circuit 1401 is provided before the variable delay circuit 104.

In the time difference detection circuit 105, the reference synchronization signal generation circuit 10
The reference signal generation circuit 106 detects the maximum level of the reference signal (horizontal synchronization signal, character multiplex signal) for detecting the time difference of the received signal within one period of the synchronization signal obtained from the reference synchronization signal generation circuit 106.
The time difference between the maximum level reference signal and the synchronization signal obtained from the synchronization signal is detected, and the time difference signal is output to the variable delay circuit 104, and at the same time, the level of the maximum level reference signal is output to the AGC circuit 1401.

The AGC circuit 1401 controls the level of the input maximum level reference signal to an optimal constant value.

In this embodiment, the time difference detection signal of the output video signal has a constant level, and the level of the synchronization signal also has a constant level, so that the operation of the synchronization circuit of the display is stabilized. Therefore, according to this embodiment, synchronization can be stabilized.

Still another embodiment of the present invention is shown in FIG.

In the figure, 1501 is a switching circuit controlled by a switching control circuit 1502, 1502 is a switching control circuit, and 1503 is a vertical synchronizing signal level detection circuit.

The same reference numerals as in FIGS. 1, 4, 11, and 12 indicate the same functions.

The difference from the embodiment shown in FIG. 1 is that it is used in combination with antenna diversity using a plurality of antennas. During the period of the vertical synchronization signal of the video signal of the received signal, the timing generation circuit 1206 outputs an antenna switching signal to the switching control circuit 1502, and the switching control circuit 1502 outputs the antenna switching signal to the switching circuit 1501.
is controlled to sequentially switch the four antennas 101 a to d within the vertical synchronization signal period. A vertical synchronization signal level detection circuit 1503 stores the level of the vertical synchronization signal obtained from each antenna, outputs a signal for selecting the antenna with the highest level among them to the switching control circuit 1502, and outputs a signal to select the antenna with the highest level among them to select the next vertical synchronization signal. During this period, connect the antenna with the highest vertical synchronization signal level.

According to this embodiment, since the antenna that provides the highest level signal can be selected from a plurality of antennas, a more stable video signal can be obtained than when a single antenna is used. Furthermore, since the antennas are switched during the vertical synchronization signal period, that is, within the vertical retrace period, it is possible to prevent image disturbances caused by antenna switching from appearing on the television screen.

Note that in this embodiment, the vertical synchronization signal level detection circuit 150
Although the input of No. 3 is the output of the A/D converter 1103, the same effect can be obtained by using the output of the detection circuit 103 or the output of the D/A converter 1105 as the input signal.

〔Effect of the invention〕

According to the present invention, when a television receiver is mounted in a car and moves, the ghost becomes stronger than the original main signal due to changes in the reception environment, and the ghost signal replaces the previous main signal. Even if a situation arises in which a ghost is captured as the main signal in the future, the switching can be done without causing image movement or disrupting synchronization.
It has the advantage of being able to perform smoothly and maintain a good screen.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a schematic diagram of various signals in FIG. 1, FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. A block diagram showing a specific example of the time difference detection circuit in Figure 1, and Figure 5 is a block diagram showing a specific example of the time difference detection circuit in Figure 4.
6 and 7 are block diagrams showing other specific examples of the time difference detection circuit in FIG. 1, and FIG. 8 is a specific example of the time difference detection circuit shown in FIG. 7. 9 is a block diagram showing yet another specific example of the time difference detection circuit, FIGS. 10 and 11 are block diagrams showing a specific example of the variable delay circuit in FIG. 1, and FIG. 1 is a block diagram showing a specific example of the reference synchronization signal generation circuit in FIG. 1, and FIGS. 13 to 15 are block diagrams showing still other embodiments of the present invention. Explanation of symbols 101... Antenna, 102... Tuner, 103
...Video detection circuit, 104...Variable delay circuit, 10
5... Time difference detection circuit, 106... Reference synchronization signal generation circuit, 107... Video signal output terminal, 108...
Frequency conversion/amplification circuit agent Patent attorney Akio Namiki 11 Prisoner π 23 □ Time 13 Step 4 F 5th Master 6 ■ 1) (J4 6 g 9th Figure 10 π117 @12v!J Shi-1 11111～1207 (110 mouths of candy ÷

Claims (1)

[Claims] 1. A television receiver that converts a received signal into a video intermediate frequency signal through a tuner and a frequency conversion circuit, and detects it in a video detection circuit to obtain a television signal and display it on a screen. A variable delay circuit that variably delays the television signal detected in the video detection circuit and outputs it to the next stage, and a reference synchronization signal generation circuit that generates a reference synchronization signal synchronized with a synchronization signal included in the television signal. , when a plurality of synchronization signals are included within one period of the synchronization signal in the television signal,
A time difference detection circuit detects a time difference between the synchronization signal having the maximum amplitude among the synchronization signals and the reference synchronization signal, and controls the amount of delay in the variable delay circuit according to the time difference. television receiver. 2. In a television receiver that converts a received signal into a video intermediate frequency signal through a tuner and a frequency conversion circuit, and detects it in a video detection circuit to obtain a television signal and display it on a screen, in a video detection circuit. a variable delay circuit that variably delays the detected television signal and outputs it to the next stage; a reference synchronization signal generation circuit that generates a reference synchronization signal synchronized with a synchronization signal included in the television signal; When a plurality of synchronization signals are included in one period of the synchronization signal in the output television signal, detect the time difference between the synchronization signal with the maximum amplitude among them and the reference synchronization signal, and adjust the time difference according to the time difference. A television receiver comprising: a time difference detection circuit that controls the amount of delay in the variable delay circuit. 3. The television receiver according to claim 1 or 2, wherein the time difference detection circuit receives a detected television signal and detects and outputs a horizontal synchronization signal therein; a differentiating circuit that inputs, differentiates, and outputs the synchronizing signal output from the horizontal synchronizing signal detection circuit; and a level comparing circuit that compares signal levels in the output of the differentiating circuit within each horizontal period. , and a maximum level storage circuit that stores the resulting maximum amplitude level. 4. In the television receiver according to claim 3, the horizontal synchronization signal detection circuit detects and outputs the horizontal synchronization signal only during the vertical retrace period of the television signal, and the level comparison circuit detects and outputs the horizontal synchronization signal only during the vertical retrace period of the television signal. A television receiver characterized in that level comparison is performed only during the retrace period. 5. The television receiver according to claim 1 or 2, wherein the time difference detection circuit receives a detected television signal and multiplexes characters from the detected television signal on a horizontal scanning period within a vertical retrace period. a character multiplex signal detection circuit that detects and outputs a signal, a differentiation circuit that receives and differentiates the character signal output from the character multiplex signal detection circuit and outputs the same, and a differentiation circuit that differentiates the character signal within each vertical retrace period. A television receiver comprising: a level comparison circuit that compares signal levels in the outputs of the circuit; and a maximum level storage circuit that stores the maximum amplitude level obtained as a result. 6. The television receiver according to claim 1 or 2, wherein the time difference detection circuit comprises: a horizontal synchronization signal detection circuit that receives a detected television signal and detects and outputs a horizontal synchronization signal therein; a differentiating circuit that inputs, differentiates, and outputs the synchronizing signal output from the horizontal synchronizing signal detection circuit; and a level comparing circuit that compares signal levels in the output of the differentiating circuit within each horizontal period. , a maximum level storage circuit for storing the resulting maximum amplitude level; A character multiplex signal detection circuit detects and outputs a multiplexed character signal, a differentiation circuit receives and differentiates the character signal output from the character multiplex signal detection circuit, and outputs the differentiated signal. a second time difference detector comprising a level comparison circuit that compares signal levels in the outputs of the differentiating circuit within a period, and a maximum level storage circuit that stores the maximum amplitude level obtained as a result; 1. A television receiver comprising: a correlation detection circuit that receives the detection output of the first time difference detector and the detection output of the second time difference detector, performs a correlation calculation, and outputs the result. 7. The television receiver according to claim 1 or 2, wherein the variable delay circuit comprises a variable analog delay circuit. 8. The television receiver according to claim 1 or 2, wherein the variable delay circuit includes an analog/digital conversion circuit that takes in a detected television signal and converts it into analog/digital, and a digital signal from the analog/digital conversion circuit. a plurality of shift registers with intermediate taps that input and delay digital output signals; and a switching circuit that selects and outputs one of the plurality of intermediate taps of the shift registers;
A television receiver comprising: a digital/analog conversion circuit that converts the output of the switching circuit into an analog signal. 9. The television receiver according to claim 1 or 2, wherein the variable delay circuit includes an analog/digital conversion circuit that takes in a detected television signal and converts it into analog/digital, and a digital signal from the analog/digital conversion circuit. A television receiver comprising: a memory circuit that inputs and stores digital output signals; and a digital/analog conversion circuit that converts read output from the memory circuit into analog signals. 10. The television receiver according to claim 1 or 2, wherein the reference synchronization signal generation circuit includes a PLL circuit that extracts a color burst signal from a detected television signal and phase-locks it, and a signal obtained from the PLL circuit. A television receiver comprising: a timing generation circuit that generates a horizontal synchronization signal based on a clock signal synchronized with a color burst signal. 11. The television receiver according to claim 1 or 2, wherein an image separation circuit receives the output signal of the variable delay circuit and separates and outputs only the image signal, leaving a synchronization signal. A television receiver further comprising: a synthesis circuit that adds a reference synchronization signal generated in the reference synchronization signal generation circuit to the image output signal from the image separation circuit and outputs the resultant signal. 12. The television receiver according to claim 1 or 2, wherein an automatic gain control circuit is provided on the input side of the variable delay circuit, and the maximum amplitude signal level input to the variable delay circuit is controlled to a constant value. A television receiver characterized by: 13. The television receiver according to claim 1 or 2, including a plurality of antennas having different directivity, and an antenna for switching and selecting any one of the plurality of antennas and inputting the selected antenna to the tuner. A television further comprising a switching circuit and an antenna switching control circuit that controls the operation of the antenna switching circuit so that the antenna switching circuit performs a switching selection operation during a vertical retrace period of a television signal. Receiving machine.