JPH0210367B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dual beam spectrophotometer.

A dual-beam spectrophotometer of the ratio-recording type, i.e., a type of dual beam spectrophotometer that determines the transmittance of the sample material by calculating the ratio of the radiation received through the sample path to the radiation received through the reference path. A beam spectrophotometer uses the signal extracted from the detector to
a first signal representing radiation received at the detector minus background radiation coming from the radiation source through a first path including the sample cell; and a second path from the radiation source including the reference cell. and a second signal representative of the radiation received by the detector minus background radiation. The radiation incident on the detector via the first and second paths is in the form of discretely generated interlaced pulses, and between these pulses, the radiation passing through the first and second paths is detected. It is separated by a dark signal period that prevents it from entering the detector. The detector also outputs a composite electrical signal representative of the magnitude of the radiation received by the detector.

In such spectrophotometers, the radiation received by the detector is in a time-multiplexed form, so that the output of the detector due to the background radiation (which has passed through the first and second paths) is The output of the detector (considered the output of the detector during the period in which radiation is prevented from entering the detector) is measured at a different time than when the radiation passing through the first and second paths is measured. Therefore, if the magnitude of the background radiation varies, this will cause an error in the determined transmittance value. Changes in the background level occur, for example, when scanning in the infrared region step by step, because absorption by water vapor in the atmosphere exhibits different selectivity with respect to wavelength.

Prior art spectrophotometers measure the background radiation level (i.e., dark level) immediately before measuring the radiation received through the first path (i.e., the sample level) and subtract from these to determine the first signal. (i.e. sample-dark signal). Second
The signal (i.e., the reference-dark signal) is created in the same way. Since the detector is usually AC coupled to a signal processing circuit, the sample-dark signal and the reference-dark signal are separated during a period during which neither radiation passing through the first path nor radiation passing through the second path is incident on the detector (hereinafter referred to as the dark signal). may be generated by clamping the signal level to ground potential or some other reference potential during periods (referred to as periods). Another known circuit for generating the first and second signals comprises three sample-and-hold circuits, which generate signals at the detector during the period during which the radiation passes through the first path (hereinafter referred to as the sample signal period). The signal generated by the detector during the period during which the radiation passes through the second path (hereinafter referred to as the reference signal period), and the signal generated by the detector during the dark signal period are sampled, respectively. The output terminal of this sample-hold circuit is connected to the input terminals of two subtraction circuits, the first subtraction circuit produces a sample-dark signal, and the second subtraction circuit produces a reference-dark signal. In this circuit, as the level of background radiation changes, the sample-dark signal and reference-dark signal magnitudes are updated to the latest in each dark signal period, i.e., the dark signal periods on either side of the respective sample or reference period. be done. However, neither of these circuits can prevent dynamic break through on the first and second signals resulting from sudden changes in background radiation levels.

An object of the present invention is to provide a spectrophotometer in which the influence of background radiation level fluctuations on measurements is reduced.

To achieve this purpose, according to the invention, a signal generated in a detector is received and background radiation is subtracted from the radiation received by the detector from the radiation source through a first path containing the sample cell. and a second signal representative of the radiation received by the detector from the radiation source through the second path including the reference cell, minus background radiation. interlaced pulses, wherein the radiation received by the detector is separated by a dark signal period during which neither the radiation coming through the first path nor the radiation coming through the second path is prevented from entering the detector. in a continuous wavelength scanning dual beam spectrophotometer having the form of
The signals generated by the detector during successive dark signal periods are successively averaged, and the successive dark signal periods are
a signal generated by the detector when radiation is received through the first path, including at least one dark signal period on each side of each period corresponding to signals from the first and second paths; The average value is subtracted from the signal generated by the detector when radiation is received through the second path to produce the first and second signals, respectively. Also, the sequential dark signal periods may include only one dark signal period on each side of the respective period corresponding to signals from the first and second paths.

This averaging of the signals generated during successive dark signal periods not only reduces the effect of fluctuations in background radiation levels on the measurement, but also reduces the effects of fluctuations in background radiation levels on the measurement. Nonlinearity in transmittance measurements can be reduced when having a thermal time constant of frequency. This is true for typical infrared detectors such as pyroelectric or Goray-neumatic detectors.

The signal processing circuit includes four sample-and-hold circuits in the signal processing circuit, a first sample-and-hold circuit storing a signal representative of the radiation received through the first path, and a second sample-hold circuit storing a signal representative of the radiation received through the first path. - storing in a hold circuit a signal representative of the radiation received through the second path, and storing in a third and fourth sample-hold circuit a signal representative of radiation received in successive dark signal periods; Furthermore, means are provided for averaging the outputs of the third and fourth sample-and-hold circuits, the first input terminal is connected to the output terminal of the first sample-and-hold circuit, and the second input terminal is connected to the output terminal of the first sample-and-hold circuit. a first subtracter connected to the output terminal of the averaging means; a first input terminal connected to the output terminal of a second sample-and-hold circuit; and a second input terminal connected to the output terminal of the averaging means. A second subtracter connected to the subtractor is provided, and the outputs of the first and second subtracters are used as first and second signals, respectively.

The present invention will be explained in detail by way of examples with reference to the drawings.

The spectrophotometer shown in Fig. 1 includes a radiation source S, means for creating two radiation beams, means for combining the paths of these two radiation beams, a monochromator MO, a detector D, and a signal processor. Equipped with a device PC.

The radiation emitted by the radiation source S (which can be in the infrared, visible and ultraviolet regions of the spectrum) is reflected by the mirror M ₁ and travels along the path SB through the sample cell in the measuring chamber MC. let

The radiation traveling along this path SB is further reflected by two mirrors M2 and M3 towards a rotating sector mirror assembly M4.
Then, this sector mirror assembly M4 is connected to the passage SB.
The mirror M8 alternately transmits the radiation traveling along the
Drop it upwards and reflect it with mirror M8. The radiation emitted by the radiation source S is further reflected by a mirror M5 and travels along a second path RB passing through a reference cell RC, which is also located in the measurement chamber MC. The radiation traveling along this second path RB passes through two further reflectors M6 and M7.
The beam is reflected by the beam and directed toward the rotating sector mirror assembly M4. This sector mirror assembly M4 then alternately reflects the radiation traveling along the second path RB onto mirror M8, where it is reflected. Sector mirror assembly M4 thus produces a composite radiation beam CB comprising a pulse of radiation which has traveled along the first path SB and a pulse of radiation which has traveled along the second path interposed therebetween.
is formed. The rotatable sector mirror M4 includes a sector that transmits radiation, a sector that absorbs radiation, a sector that reflects radiation, and a sector that absorbs radiation that are sequentially arranged in series,
Therefore, in the composite radiation beam CB, the first path SB
The pulse of radiation that has traveled along the path and the second path
Pulses of radiation traveling along the RB are repeated alternately, and between these pulses there are periods in which no radiation reaches from the radiation source. The composite radiation beam CB is reflected by the mirror M8 and enters the entrance slit SL1 of the monochromator MO. Monochromator MO has entrance slit SL
1. Concave mirror M9, diffraction grating G and injection slit
SL2, which is used to select radiation with a narrow wavelength band from the wide-bandwidth radiation present in the input slit SL1. The narrow band radiation extracted from the exit slit SL2 is reflected by the mirror M10 and enters the detector D. The output signal of the detector D is supplied to the display I through the signal processing device PC.

Place the sample in the measurement chamber to measure the transmittance of the sample
The sample beam is passed through the sample cell MC, and the signal processing device PC calculates the ratio of the magnitude of the radiation appearing from the sample cell SC to the magnitude of the radiation appearing from the reference cell RC. If the magnitude of the radiation emitted from the radiation source S is small, the output signal of the detector D will be small, and therefore the influence of noise in the system will be large. Since the total noise appearing at the output terminal of the signal processing device PC is proportional to the square root of its bandwidth,
When reducing the magnitude of the radiation traveling along the second path RB and reaching the detector D, the bandwidth can also be narrowed, thereby reducing the influence of noise. This means can be rephrased as increasing the response time of the signal processing device PC. This is because the lid is closed and the amount of radiation is reduced. This increased response time,
In other words, due to the decrease in bandwidth, the system is
This limits the rate of change in wavelength that occurs in the monochromator MO in order to make meaningful measurements.

Furthermore, the radiation detected by the detector D during the sample (measurement) period is the radiation emitted from the radiation source and passed through the sample cell plus the background radiation, so the radiation that passes through the sample cell,
In order to extract only the signal due to the radiation incident on the detector, it is necessary to subtract the dark signal from the sample signal. Similarly, before determining the transmittance (which is the ratio of the sample signal to the reference signal), it is necessary to subtract the dark signal from the reference signal. For this purpose, a signal processing device PC is provided for the purpose of performing the necessary subtraction and division.

This signal processing device PC is further provided with a device for averaging the dark signals generated at both ends of the sample signal or the reference signal, and this average signal is used as the dark signal to be subtracted from the sample signal or the reference signal. This makes it possible to reduce the influence that fluctuations in the amplitude of the dark signal have on the sample signal or the reference signal. Another advantage obtained by averaging the dark signals occurring at the ends of the sample or reference period is when the detector D is AC coupled to the signal processing device PC or the detector D
This reduces the degree of nonlinearity of the transmitted signal when the detector itself is an AC detector.

A typical display device I is a chart recorder, in which a chart is advanced in synchronization with the wavelength change of a monochromator. However, other displays can also be used, for example video display devices. Alternatively, it is also possible to supply the output of the signal processing device PC to a computer, store the information in the computer, or drive a printer to print the transmittance value for the wavelength.

FIG. 2 is a block diagram of one embodiment of a signal processing device PC suitable for use in the spectrophotometer of FIG. The signal from the detector D is applied from terminal 1 to a first input terminal of the decoder 2 and to a first input terminal of the control logic circuit 7. Four timing signals taken from a device for detecting the position of the rotatable sector mirror assembly M4 are connected to terminals 3, 4, 5 and 6.
to another input terminal of the decoder 2 and the control logic circuit 7. The first output terminal of decoder 2 is
Connect to the integrator 20 via FET8. The integrator 20 includes a resistor R1, a capacitor C1, and an operational amplifier A1.
It consists of Connect FET9 to both ends of capacitor C1. The output terminal of the integrator 20 is connected to a sample-and-hold circuit 22. This sample-hold circuit 22 includes a FET 10, a resistor R2, a capacitor C2, and an operational amplifier A2. Connect the output terminal of operational amplifier A2 to output terminal 1 of signal processing circuit RC.
Connect to 1. The second output terminal of decoder 2
It is connected to the second integrator 21 via the FET 12.
The second integrator 21 comprises a resistor R3, a capacitor C3 and an operational amplifier A3. Connect FET13 to both ends of capacitor C3. The output terminal of the second integrator 21 is connected to the resistors R4 and R5 and the high speed comparator A.
Connect to one input terminal of a comparator circuit consisting of 4. The other input terminal of high-speed comparator A4 is set to the reference potential.
Connect to VR. The output terminal of this comparison circuit is connected to another input terminal of the control logic circuit 7. The control logic circuit 7 has three output terminals.
The output terminal i is connected to the gate electrodes of FETs 8 and 12, the second output terminal f is connected to the gate electrodes of FETs 9 and 13, and the third output terminal m is connected to the gate electrodes of FETs 8 and 12.
10 gate electrodes.

Figure 3 shows the signal processing circuit (device) shown in Figure 2.
FIG. 3 is a waveform diagram showing waveforms occurring at various points on the PC. Waveform a shows a composite waveform applied from detector D to terminal 1. The four periods T1, T2, T3 and T4 are respectively a first period during which the radiation beam is absorbed by the mirror system, a period during which the radiation beam passes through the reference cell and then enters the detector D, and a period during which the radiation beam is absorbed by the mirror system. and the period during which the radiation beam passes through the sample cell and then enters the detector D. The waveforms b, c, d and e are in the period T1, respectively.
Four timing signals are shown applied to the decoder 2 and the control logic circuit 7 at T2, T3 and T4. By using these timing signals, the decoder 2 outputs at its first output terminal the nearest periods T1 and T from the detector output signal at period T4, hereinafter referred to as "Sample-Dark".
3 and outputs a signal obtained by subtracting the average value of the detector output signals in the period T2, and outputs a signal obtained by subtracting the average value of the detector output signals in the period T2 to its second output terminal. T1 and T3
and a control logic circuit in the period between the end of period T2 and the start of period T3 and the period between the end of period T4 and the start of period T1. 7 is the waveform f
Outputs the signal. This signal f is FET9 and 1
3 to the gate electrode of capacitor C1 and C
3 to reset the two integrators 20 and 21. At the beginning of periods T1 and T3, the control logic circuit 7 outputs an output signal shown in waveform i. Thereby, integrators 20 and 21 integrate the outputs from the first and second output terminals of decoder 2, respectively. Integrator 21 integrates the reference-dark signal, and when its output, indicated by waveform g, reaches reference potential VR, changes the output signal of the comparator to that indicated by waveform h. This in turn causes the control logic circuit 7 to terminate the integral pulse i.
Thus, integrator 20 (whose output signal is as shown by waveform j) now holds a representation of the sample-dark signal as part of the reference-dark signal. Control logic circuit 7 outputs a signal represented by waveform m. This switches on FET 10 and connects the output terminal of integrator 20 to sample-and-hold circuit 22. The sample pulse of waveform m rises at the end of integral pulse i, and its pulse length depends on the magnitude of the output of the detector during period T2, that is, the magnitude of the radiation reaching detector D via the second path RB. do. As this magnitude increases, the sampling time also increases, allowing the signal at the output terminal 11 to more quickly follow changes in the magnitude of the received radiation.

Since the noise output of the system is proportional to the square root of the bandwidth, it is preferable to make the sampling time proportional to the square of the signal energy. This way, the noise
Bandwidth is kept constant. In order to make the sampling time proportional to the square of the signal energy, the control logic circuit 7 is provided with a squaring circuit that squares the signal of the detector D during the period T2. In this way, the control logic circuit 7
uses this value to determine the length of pulse m, thereby determining the sampling time of sample-hold circuit 22.

FIG. 4 shows the waveform n of the sample-hold circuit 22.
The response to the step input shown in is shown. FET
10 continues to be turned on one by one, the output from the output terminal 11 takes the form shown by the waveform P, and the response time depends on the time constant CR determined by the resistor R2 and the capacitor C2. However, if the FET 10 is switched on for 25% of the time CR, the output at the output terminal 11 will take the form shown by waveform q. Obviously, in this case, the speed at which the output of the sample-and-hold circuit 22 follows changes in the value of the signal at the input terminal is FET 10.
depends on the time the switch is turned on.

The amplifier shown in Figure 5 has an input terminal 1 and a decoder 2.
and the control logic circuit 7. This amplifier consists of an operational amplifier A501, a capacitor C501, a resistor R501, a resistor R502, and a capacitor C50.
a preamplification stage 502 comprising: 2; After this preamplification stage 502, there is a differentiator 503 including an operational amplifier A502, a resistor R503, a resistor R504, a capacitor C503, and a capacitor C504. The output of the differentiator 503 is supplied to the control logic circuit 7 via a line 701, and then via a capacitor C505 and a resistor R505 to a variable attenuator/buffer stage 504.
supply to. The variable attenuator/buffer stage 504 includes an operational amplifier A503, a capacitor C506, and a resistor R.
506 and a resistor R507, and outputs an output signal on line 601. This output signal is sent to decoder 2
is supplied to This variable attenuator and buffer stage is controlled by an automatic gain comparison and amplification stage 505. This automatic gain comparison and amplification stage 505 has a line 501.
The output of the decoder 2 is supplied through the . The signal on line 501 is connected to two resistors R508, R50
Operational amplifier A50 via series connection of 9
4 positive input terminal. Resistors R510 and R5 of a voltage divider comprising resistors R510 and R511 connected between the positive power supply line and the negative power supply line.
11 is connected to the negative input terminal of operational amplifier A504 via resistor R512. Resistor R5
Two diodes D are connected between the connection point of 08 and resistor R509 and the connection point of resistor R510 and resistor R511.
501 and D502 are connected in parallel with their polarities reversed. The output terminal of operational amplifier A504 is connected to the negative input terminal of operational amplifier A501 via resistor R513 and resistor R514. Resistance R
Connect the connection point between 513 and resistor R514 to FET T501
Connect to the gate electrode of The source and drain electrodes of FET T501 are connected to both ends of resistor R515. Resistor R515 is connected between the negative power supply line and the positive input terminal of operational amplifier A503. A capacitor C507 is connected between the positive input terminal of operational amplifier A504 and the negative power supply line. A capacitor C508 is connected between the output terminal of operational amplifier A504 and the negative power supply line. A capacitor C509 is connected between the output terminal and the negative input terminal of operational amplifier A504. This automatic gain comparison/amplification stage 505 controls the variable attenuator/buffer stage 504 to keep the reference-dark signal substantially constant even if the signal level received by detector D varies.

The waveforms of FIG. 10 illustrate the response of a signal processing circuit to a composite signal having a negative drift that may be attributable to, for example, variations in the level of background radiation.

In the first type of prior art system described above, the dark signal level is determined in the dark signal period immediately before each sample signal period and the reference signal period, and this is the sample signal level determined in the sample signal period and the reference signal period, respectively. and the reference signal level to yield a sample-dark signal and a reference-dark signal, respectively.
Thus, as shown by the waveform d, in the period Ta, the standard -
The dark signal is given by Ra-D1a, and the sample-dark signal is given by
Sa--Given by D2a. Here, Ra is the reference signal level in the period Ta, Sa is the sample signal level in the period Ta, D1a is the first dark signal level in the period Ta, and D2a is the second dark signal level in the period Ta. be. However, because the background radiation level drifts as shown in waveform d, the true dark signal level is
D1a+D2a/2 and D2a+D1b/2, so the true reference signal level is Ra-D1a+D2a/2 and the true sample signal level is Sa-D2a+D1b/2. Since the background radiation level drifts towards the negative as shown in waveform d, D1a is more positive than D1a + D2a/2, and D2a is more positive than D2a + D1b/2, so the calculated reference - dark Signal and Sample - The dark signal is lower than the true value by an amount that depends on the rate of drift of the background radiation level. Conversely, if the background radiation drifts in the positive direction, the reference-dark signal and the sample-dark signal are higher than the true level.

Waveforms e and f are the second waveforms of the prior art circuit described above.
This type of response is shown below. In this case, the sample-dark signal and the reference-dark signal are not only defined at the end of the reference signal period and the sample signal period, but are also modified as each dark signal level is established. Thus, in the case of the sample-dark signal shown as waveform e in the period Tb, the value of the sample-dark signal is Sa-D2a in the first dark signal period, and Sa-D2a in the reference signal period and the second dark signal period. D1b, and Sa-D2b during the sample signal period. By applying this waveform, a nearly constant output can be given. However, as is clear from waveform e, the true sample - dark level S
-Not symmetrical about D. The reference dark signal changes in the same way as the sample dark signal, as shown by waveform f. Thus, in this circuit, the calculated sample-dark signal and reference-dark signal are greater than the true value if the background radiation drifts in the negative direction, and are larger than the true value if the background radiation drifts in the positive direction. is smaller than the true value.

Waveforms g and h represent the response of a signal processing circuit that averages the dark signal level during two successive dark signal periods and subtracts it from the reference or sample signal. The calculated value of the sample-dark signal shown as waveform g in period Tb is
Sa-D1a+D2a/2, Sa-D2a+D1b/2 during the reference signal period and second dark signal period, and Sa-D1b+D2b/2 during the sample signal period. Therefore, the average value over the period Tb is Sa − D1a + D2a / 2 + 2 [Sa − D2a + D1b
/2〕+Sa-D1b+D2a/2/4 =Sa-3/4・D1b+D2a/2-1
Equal to /4・D1a+D2b/2.

The dark signal level is thus primarily defined by the average of the dark signal levels in the dark signal periods on either side of the sample signal period, but the additional component due to the dark signal level next further away from the sample signal period also accounts for 1/3. Added with weight.

The complex waveform shown in FIG. 11 is generated by a detector that is AC coupled to a signal processing circuit or a detector commonly used in infrared spectroscopy, such as a pyroelectric detector or a Goray-neumatic detector. It is taken from. Figure 11a shows the energy received at the detector and Figure 11b shows the generated signal coupled to the signal processing circuit. The amount of decrease σx of each level is proportional to the magnitude (x) of the signal regarding its average level, and if τ≫t, t/
It is given by τ. τ is the AC coupling time constant, in other words the low frequency thermal time constant of the infrared detector. To obtain good noise wave characteristics, it is necessary to take the average level over as long a time as possible, preferably over the entire reference signal period or sample signal period, rather than determining the instantaneous value of the signal. be. The measured transmittance is expressed as in the case of the first prior art circuit.
Sa, Ra, D1a, and D2a are the average signal levels of the sample, reference, and dark signal periods, respectively (Sa−D2a)/
(Ra - D1a), and when it is set to a few percent, the measured value of transmittance is given by Tm = Ta + σ/4 (1 - Ta ² ). Here, Tm is the measured value of transmittance and Ta is the true value of transmittance.

As is clear from FIG. 12, this gives a zero offset of σ/4 and a maximum deviation from linearity of σ/16 when Ta=1/2. If σ=5%, σ/4=
At 1.25%, σ/16=0.31%.

However, if the measured transmittance value is calculated as Sa−D1b+D2a/2/Ra−D1a+D2a/2, then the transmittance measurement is Tm=Ta+
It is given by (1-Ta ² )σ ² /8.

As can be seen in FIG. 5, this gives a zero offset of σ ² /8 and a maximum deviation from linearity of σ ² /32. Taking σ=5%, this gives a zero offset of 0.31% and a maximum deviation from linearity of 0.0078%.

Thus, by averaging the dark signal levels during the dark signal periods on either side of each sample and reference signal period, a significant improvement in linearity and offset from the true value of the transmittance measurements is obtained. It can be achieved.

FIG. 6 shows a decoder 7 capable of performing this averaging. The signal processing circuit includes four sample-hold circuits 604, 605, 606 and 607 and two subtraction circuits 608 and 609.

Sample-hold circuit 606 is FET T60
4. The sample-hold circuit 605 includes a resistor R604, a capacitor C604, and an operational amplifier A604; the sample-hold circuit 605 includes a FET T605, a resistor R605, a capacitor C605, and an operational amplifier A605;
A sample-and-hold circuit 60 comprising a resistor R606, a capacitor C606 and an operational amplifier A606.
7 includes a FET T607, a resistor R607, a capacitor C607, and an operational amplifier A607.

The subtraction circuits 608 and 609 have the same shape,
Subtraction circuit 608 includes operational amplifier A608, whose positive input terminal is connected to resistors R608 and R60.
9 (with capacitor C608 connected across them), and a resistor network comprising R610 and R611. A resistor R612 and a capacitor C612 connected in parallel are connected between the output terminal and the negative input terminal of operational amplifier A608. The first input terminal of the subtraction circuit 608 is connected to a resistor R.
613 to the negative input terminal of operational amplifier A608, and its second input terminal is connected to the positive input terminal of operational amplifier A608 through resistor R614. The subtraction circuit 609 has the same shape and has a resistor R618.
R623, capacitors C618 and C622, and operational amplifier A609.

Composite waveform a, after being appropriately processed by the amplifier shown in FIG. 5, is applied on line 601 to sample-and-hold circuits 604-607. Timing signals e, d, c and b are applied to sample-and-hold circuits 604-607 from terminals 3, 4, 5 and 6, respectively. As a result, during the period T1, ie, the first dark signal period, the sample-hold circuit 607 samples the composite waveform when the timing signal b makes the FET 607 conductive and stores the magnitude of the composite waveform at that time in the capacitor C607. In this way, a representation of the radiation falling on the detector D during the first dark signal period, ie the period when the radiation beam leaves the detector D, is stored. Similarly, the value of the reference signal is stored in capacitor C606, the value of the sample signal is stored in capacitor C604, and the signal of the second dark signal period is stored in capacitor C605. The output terminals of sample-and-hold circuits 605 and 607 are connected together through resistors R630 and R631, respectively, and the average value of the composite signal during the last two dark signal periods is applied to one of each of subtraction circuits 608 and 609. so that it is applied to the input terminal of sample-
The output of the hold circuit 604 is applied to the other input terminal of the subtraction circuit 608 and the output of the sample-and-hold circuit 606 is applied to the other input terminal of the subtraction circuit 609 as well as to the automatic gain comparator and amplifier 505 via line 501. (Figure 5).

Subtraction circuit 608 connected to line 602
A subtraction circuit 609 is connected to line 603, from the output terminal of which provides a sample-dark signal which is applied to the input terminal of integrator 20 (FIG. 2) under the control of integrator circuit i as described above. From the output terminal of the integrator 21 (second
Provides a reference-dark signal applied to the input terminal in Figure).

Subtraction circuit 608 receives the most recent sample signal at its first input terminal and the average value of the two most recent dark signals at its second input terminal. Subtraction circuit 6
09 receives at its first input the latest reference signal and at its second input the average value of the two latest dark signals. As a result, the output of the subtraction circuit 608 appearing on line 602 has a waveform g shown in FIG. 3, and the output of the subtraction circuit 609 appearing on line 603 has a waveform h. By applying appropriate waves to these waveforms and taking the ratio, the transmittance value can be obtained.

The control logic circuit 7 is shown in detail in FIGS. 7 and 8 and comprises an energy level detector 703, a squaring circuit 704, an energy level comparator 705 and the logic elements shown in FIG. There is also a comparator 706 shown in FIG. 7, which replaces the comparator 706 shown in FIG.

The input terminal of the energy level detector 703 is connected to the differential amplifier stage 503 (FIG. 5) via the line 701.
is connected to the output terminal of FET T703,
A sample-and-hold circuit is provided having a resistor R703, a capacitor C704, and an operational amplifier A703.

This sample-hold circuit has a capacitor C
A signal is input via 703. FET T703
is switched by waveform C, resulting in period T2
The radiation falling on the detector at is retained. Connect resistor R723 and FET T7 between the connection point of capacitor C703 and FET T703 and the negative power supply line.
23 are connected in series. FET
Waveform b is supplied to the gate of T723, and period T2
The capacitor C703 should be discharged before. The output terminal of the sample-hold circuit is connected to two resistors R.
704 and R705 are connected to the negative power supply line via a series-connected branch. Resistors R704 and R70
A connection point 5 constitutes an output terminal of an energy level detector 703, and a squaring circuit 704 is connected to the end thereof.

The squaring circuit 704 includes an operational amplifier A704 whose positive input terminal is connected to the connection point between resistors R704 and R705. The output terminal of operational amplifier A704 is connected to the negative input terminal of operational amplifier A704 via a resistor R706. A series connection of two diodes D701 and D702 and a resistor R708 is connected between the negative input terminal of operational amplifier A704 and the negative power supply line. Also diodes D701 and D702
The connection point of is connected to the negative power supply line via resistor R707.

This squaring circuit has a gain of 1 until diode D701 begins to conduct, that is, until the input voltage rises above about 625 mV. Then the gain is
It is expressed as R706+R708/R708. Let this be equal to 3. When the input voltage reaches 1.25V, diode D702 also conducts, and the gain is calculated by the formula R706+R707×R708/R707+R708/R707×R708/R707+
Represented by R708. This can be equal to 6. FIG. 9 shows the response of the squaring circuit to an input signal varying between 0V and 2.5V. This response can be approximated by a broken line that is correct at 25%, 50%, and 100% of the maximum input signal. In reality, the diode gradually turns on at the bending point, so the curve becomes smooth. The output voltage of the square circuit is 1.6 (Vin) ² .

Energy level comparator 705 is capacitor C
705, a comparator, and a switch controlled by a reference level comparator 706, which takes the form of a modification of the reference level comparator of FIG. The constant current source comprises a pnp transistor T705, the emitter of which is connected to the positive power line through a resistor R710, and the base of which is connected to a resistor R711 between the positive and negative power lines.
and preset potentiometer R712.
Connect to a voltage divider with transistor T7
The connection point between the collector of 05 and capacitor C705 is connected to the negative input terminal of high-speed comparator A705 via resistor R713. The high speed comparator A705 has its associated elements, namely the diode D703 and the low resistance R71.
4 and R715 form one comparator.
A switch equipped with FET T704 is a square circuit 70
The output terminal of No. 4 is connected to the connection point between the capacitor C705 and the collector of the transistor T705.
FET T704 is diode D704 and resistor R7
09 by the output of the reference level comparator 706.

The reference level comparator comprises an operational amplifier A706, the negative input terminal of which is connected between two resistors R7 between the positive and negative power lines.
16 and R717. Input line 7 connected to the output terminal of integrator 21
02 and the positive input terminal of operational amplifier A706. Operational amplifier A706
A diode D706 is connected between the positive and negative input terminals of . Also operational amplifier A706
A resistor R7 is connected between the positive input terminal of
Connect 19. The output terminal of operational amplifier A706 is connected to the positive power supply line through a resistor R720, and the output terminal of operational amplifier A706 is connected to the positive power supply line through a diode D707.
Connect to 7. Connect output line 707 to resistor R721
Connect to the positive power line through.

In operation, the energy level detector 703
samples the magnitude of composite waveform a during period T2 and holds this value in capacitor C704, thereby providing a signal representing the magnitude of the radiation transmitted through the reference cell to the input terminal of squaring circuit 704. The output of the squaring circuit is the reference level comparator 706
is fed to the energy level comparator via FET T704 controlled by the output of . This discharges capacitor C705, producing a negative voltage at the junction of capacitor C705 and resistor R713 proportional to the square of the magnitude of the radiation transmitted through the reference cell when the output of the reference comparator is positive. When the output of the reference comparator goes negative, FET T704 is switched off;
Capacitor C705 is linearly charged by a constant current source. This effect is illustrated by waveform k in FIG. A signal having the waveform l shown in FIG. 3 is outputted from the output terminal of the comparator A705 due to the signal having the waveform k. As is clear from FIG. 3, the mark/space ratio of waveform l depends on the magnitude of the output of squaring circuit 704. The output of comparator A705 is modified by control logic as described below to generate a control signal for sample-and-hold circuit 22 of FIG.

FIG. 8 is a circuit diagram of a logic circuit that produces waveforms i, f, and m of FIG. OR input terminals 4 and 6
Connect to the input terminal of gate 800 and OR gate 8
Connect the output terminal of 00 to monostable multivibrator 80
Connect to input terminal 1. The rising edge of a pulse during period T1 or T3 will then cause monostable multivibrator 801 to generate a pulse that sets two bistable circuits 802 and 803. The output terminal of bistable circuit 803 is connected to output line 805 via inverter 804 . A waveform i controlling the operation of integrators 20 and 21 shown in FIG. 2 is output from this output terminal. The bistable circuit 803 operates such that when the output of the reference comparator on the line 707 connected to the reset input terminal of the bistable circuit 803 becomes negative, that is, the output of the reference integrator 21 reaches a preset value. When reached or next period T2 or T
It is reset at the end of 4. Input terminals 3 and 5 are connected to the input terminals of NOR gate 806.
The output terminal of NOR gate 806 is connected to the input terminal of monostable multivibrator 807. The output terminal of monostable multivibrator 807 is connected to the clock input terminal of bistable circuit 803. In this way, the falling edge of waveform c or e causes bistable circuit 8
03 changes state. Thus period T2 or T4
The integral pulse i disappears at the end of the cycle or when the output of the integrator 21 reaches a preset value. The Q output terminal of the bistable circuit 803 is connected to the inhibit input terminal of the monostable circuit 807, and when the integration is completed, the monostable circuit 807 outputs an output pulse and the bistable circuit 8
03 should not be clocked. Therefore, the bistable circuit 803 is reset via line 707 before the end of the reference signal period or sample signal period T2 and T4.

The output terminal of the reference level comparator 706 connected to line 707 is
Connect to one input terminal of NAND gate 809. The other input terminal of NAND gate 809 is connected to energy level comparator 7 via line 708.
Connect the output terminal of 05. NAND gate 80
The output terminal of 9 is connected to an output line 811 via an inverter 810. This NAND gate 80
9, the waveforms h and l are combined so that the pulse length is proportional to the output of the squaring circuit 704, so that the period T2,
That is, it generates a sample-and-hold pulse m that is proportional to the square of the energy received by the detector D when radiation passing through the reference cell is incident on the detector.

The output of NOR gate 806 is also during periods T2 and T4.
It is applied to one input terminal of NAND gate 812 while resetting bistable circuit 802 at the beginning of . The other input terminal of NAND gate 812 is connected to the output terminal of bistable circuit 802. The output terminal of NAND gate 812 is connected to inverter 813. The output terminal of NAND gate 809 is connected to inverter 814, which in turn is connected to inverter 815. Inverters 813 and 815 are combined to output line 81
6 and supplies a zero clamp signal, waveform f, to integrators 20 and 21 of FIG. 2 at the end of output line 816. Thus, the zero clamp signal occurs only between periods T2 and T3 and between T4 and T1.

In an alternative embodiment, a signal representative of the level of radiation falling on the detector during each of time periods T1-T4 is measured with an integrating digital voltmeter and the data is stored in memory. Next, the difference between the sample-dark signal and the reference-dark signal and the ratio of the former to the latter are calculated by a calculation device. The response time can be varied by averaging the results over a period that depends on the magnitude of the signal in period T2. Using this technique, it is also possible to weight the measurement results during the averaging period, for example, giving greater weight to the most recent measurements.

It is also possible to calculate the sample-dark signal and the reference-dark signal using signals representing the dark level averaged over any desired number of cycles in the arithmetic unit of the central processing unit. This allows the magnitude of the measured dark signal to be weighted to take into account the effects of variations other than those in immediately adjacent dark periods.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of the dual beam spectrophotometer of the present invention;
Fig. 2 is a circuit diagram of a signal processing circuit for use in the spectrophotometer shown in Fig. 1, Fig. 3 is a waveform diagram for explaining the operation of the signal processing circuit shown in Fig. 2, and Fig. 4 is a circuit diagram of a signal processing circuit used in the spectrophotometer shown in Fig. 1. Figure 5 is a diagram showing the response to the step input of the sample-hold circuit in Figure 5. Figure 5 is a circuit diagram of an amplifier inserted between the radiation detector and the input terminal of the signal processing circuit in Figure 2. A detailed circuit diagram of the decoding circuit in FIG. 2, FIGS. 7 and 8 are detailed circuit diagrams of the control logic circuit in FIG. 2, and FIG. 9 is a diagram showing the response of the square circuit of the control logic circuit. FIG. 10 is a diagram showing the response of various processing circuits to the complex signals generated as the level of background radiation varies; FIG. 11 is a diagram showing the response of certain types of detectors to radiation incident thereon. 12 is a graph plotting the measured transmittance against the actual transmittance when using the processing circuit of the prior art, and FIG.
This is a diagram equivalent to Figure 2. S... Radiation source, SC... Sample cell, RC... Reference cell, MC... Measurement chamber, MO... Monochromator, D...
Detector, PC...signal processing circuit, I...indicator, M1
~M10...mirror, G...diffraction grating, SL...slit,
SB, RB, CB...Radiation path, 1...Input terminal,
2...Decoder, 3-6...Terminal, 7...Control logic circuit, 8-10...FET, 12, 13...FET, 11
...Output terminal, 20, 21...Integrator, 22...Sample-hold circuit, 502...Preamplifier, 503
... Differentiator, 504 ... Variable attenuator and amplification stage, 505
...Automatic gain comparison and amplification stage, 604-607...Sample-hold circuit, 608, 609...Subtraction circuit, 703...Energy detector, 704...Squaring circuit, 705...Energy level comparator, 706...
Comparator.

Claims (1)

Claims: 1. A first radiation source receiving a signal generated at a detector and representing radiation received at the detector from a radiation source through a first path including a sample cell, minus background radiation. a signal processing circuit for producing a signal and a second signal representative of the radiation received by the detector from the radiation source through the second path including the reference cell, minus background radiation; The radiation received at the detector is in the form of interlaced pulses separated by a dark signal period during which both the radiation passing through the first path and the radiation passing through the second path are prevented from entering the detector. , in a wavelength continuous scanning double beam spectrophotometer which outputs a composite electrical signal representative of the magnitude of the radiation received by the detector, in which the signals generated by the detector during successive dark signal periods are successively averaged. and wherein the sequential dark signal periods include at least one dark signal period on each side of each period corresponding to signals from the first and second paths, and wherein the radiation passes through the first path. The signal generated by the detector when the radiation is received and the signal generated by the detector when the radiation is received through the second path are subtracted by the above average value to obtain the first signal and the second signal, respectively. A dual-beam spectrophotometer characterized by making. 2. The sequential dark signal periods include only one dark signal period on each side of each period corresponding to signals from the first and second paths. Dual beam spectrophotometer as described. 3. The signal processing circuit includes four sample-and-hold circuits, a first sample-and-hold circuit stores a signal representative of the radiation received through the first path, and a second sample-and-hold circuit stores a signal representative of the radiation received through the first path. A third and fourth sample-and-hold circuit stores signals representative of radiation received during successive dark signal periods; means for averaging the output of the sample-and-hold circuit, a first input terminal connected to the output terminal of the first sample-and-hold circuit, and a second input terminal connected to the output terminal of the averaging means; 1 subtractor,
a second subtracter having a first input terminal connected to the output terminal of the second sample-and-hold circuit and a second input terminal connected to the output terminal of the averaging means; 2. The spectrophotometer according to claim 1, wherein the spectrophotometer has two signals. 4. A spectrophotometer according to claim 3, characterized in that said averaging means comprises a resistive network.