JPH02103625A - Decimal multiplication system - Google Patents

Abstract

PURPOSE:To minimize production of futile multiples to improve the calculating speed of decimal multiplication by finding combinations of numerals used in a multiplier after checking each digit of the multiplier and producing multiples of a multiplicant used for the decimal multiplication by the minimum number including the combinations. CONSTITUTION:This decimal multiplication system is constituted of registers 1 and 2, a decimal adder/subtractor 3, register file 4, address register 5, address adder 6, digit shifter 7, operand register 8, decoder 9, and control circuit 10. Then combinations of numerals used in a multiplier are found by checking each digit of the multiplier and multiples of a multiplicant used for decimal multiplication are produced by the minimum number including the combinations. Therefore, futile unused multiples of a multiplicant are not found and the calculating speed of decimal multiplication can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic method for decimal multiplication, and particularly to a decimal multiplication method for realizing a method for generating multiples of a multiplicand.

[Conventional technology]

Conventionally, decimal multiplication has been carried out by repeating addition using a decimal adder, but as a means of increasing speed, nine sets of multiples from 1 to 9 times the multiplicand are calculated and stored in advance. A method has been considered in which multiplication is performed by reading out the multiple value of the multiplicand corresponding to the decimal number of each digit of the multiplier and adding the digits together for each digit of the multiplier.

[Problem to be solved by the invention]

In the conventional decimal multiplication method described above, it is necessary to always calculate a multiple of the multiplicand from 1 to 9 times prior to the multiplication process. In other words, even if the set of decimal numbers for each digit of the multiplier does not contain one or more numbers from 1 to 9, it will not be used in the process of adding multiples of the multiplicand in the multiplication process. There was a problem that multiples of the multiplicand were being calculated in vain.

[Ninth means to solve the problem]

The decimal multiplication method of the present invention includes a decimal adder/subtractor that can obtain an n±1 or 2n times value for an n-fold (n: integer) value of the multiplicand, and a calculation result of the decimal adder/subtractor. A register file that has the function of storing the value at the address indicated by the multiple value after the calculation, and a register file that has the function of storing the multiplier at the address indicated by the multiple value after the calculation, and a register file that examines each digit of the multiplier to determine the type of number actually used among the numbers 1 to 9. It is comprised of a decoder that selects a multiple generation sequence that generates the smallest combination of multiples that include all combinations, and a control circuit that controls the multiple generation operation of the decimal adder/subtractor according to instructions from the decoder.

[Effect]

In the present invention, each digit of the multiplier is examined to determine the combination of numbers used, and the minimum number of multiples of the multiplicand used in decimal multiplication that includes this combination is generated.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 is the A register, 2 is the B register, 3 is a decimal adder/subtractor that can calculate n±1 times or 2n times the value of the multiplicand (n: integer), and 4 is the decimal adder/subtractor A register file having a function of storing the operation result of this decimal adder/subtractor 3 at an address indicated by the multiple value after the operation, 5 is an address register, 6 is an address adder, T is a digit thick,
8 is an operand register, and 9 is a multiple generation sequence that examines each digit of the multiplier to find out the types of numbers actually used among numbers 1 to 9, and generates the smallest combination of multiples that includes all the numbers found. A decoder 10 is a control circuit that controls the multiple generation operation of the decimal adder/subtractor 3 according to instructions from the decoder 9.

2, 3, and 4 are diagrams showing the operation sequence to explain the operation in Figure 1, and Figures 5, 6, 7, and 8 are diagrams explaining the operation of the multiple generation sequence. be.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 to 8.

The operation of the circuit of the embodiment shown in FIG. 1 is roughly divided into three parts, and each operation will be explained below.

First, the multiplicand held in B register 2 is added to the triple value of the multiplicand held in A register 1, and the (n+1) times value of the multiplicand is output as a result.
and send it to register file 4. Since the address register 5 holds the value n, and the address adder 6 is instructed to add +1, the value (n+1) times the multiplicand is stored at address n+1 of the register file 4. . Further, the address register 5 stores the output of the address adder 6, that is, the value "n+1". The above operation sequence is shown in FIG.

Next, the second operation is to add the triple value of the multiplicand held in the A register 1 into both inputs of the decimal adder/subtractor 3, and output the value 2.3 times the multiplicand as the result. It is returned to register 1 and sent to register file 4. Since the address register 5 holds the value "n" and the address adder 6 is instructed to add n+n, the value 2.3 times the multiplicand is stored at addresses 2 and n in the register file 4. Stored. Further, the address register 5 stores the output of the address adder 6, that is, the value "2·n". The above operation sequence is shown in FIG.

The third operation is to subtract the multiplicand held in B register 2 from the triple value of the multiplicand held in A register 1 using decimal adder/subtractor 3, and use (n-1) times the multiplicand as the result. It is output and returned to A register 1 and sent to register file 4. The address register 5 holds the value rnJ, and the address adder 6 is instructed to subtract n-1 from (n-1) of the register file 4.
1) (n-1) times the multiplicand is stored at the address.

Simply, the address register 5 stores the value (n-1). The above operation sequence is shown in FIG.

Furthermore, a digit thick 7 having the function of shifting one digit to the left is provided on the input side of A register 1, and A register 1
By making it possible to store multiples and combining the above-mentioned 3f1 type operations, combinations of multiples of multiplicands as shown in the table below can be generated.

Then, the value of each digit of the multiplier held in the operand register 8 is input to the decoder 9, where the value of each digit is checked and the type of number actually used among the numbers 2 to 9 is determined. Accordingly, a multiple generation sequence that generates the smallest combination of multiples including all of those numbers is selected and the control circuit 10 is instructed to control the sequence.

Next, the operation of the multiple generation sequence will be explained using two multipliers as an example.

When the 8-digit multiplier r19291114J shown in FIG. 5, which is an explanatory diagram of the operation of the multiple generation sequence, is given, the numbers used in the multiplier are 4al, 1, 2, and 4.9. The least set of numbers in the above table that includes these numbers is the 21st combination, which calculates five multiples of 1°2.4, 8.9.

This multiple generation sequence becomes a sequence as shown in FIG.

Then, the multiplicand "10.b" multiplied by 10 is input to the A register 1 from the operand register 8 via the digit digit T and is held there. Further, the multiplicand rbJ is also input to the B register 2 from the operand register 8 and held there. Further, “0” is set in the address register 5. (
cycle ■) Next, the decimal adder/subtractor 3 has B register 2.
The output mode of the address adder 6 is set to +1 mode, and the data rbJ of the B register 2 output from the decimal adder/subtracter 3 is stored in the A register 1, and at the same time, the output mode is set to the address adder 6. It is also stored at address 1 of the register file 4 designated by the value "1". The address register 5 has an address adder 6.
The output "1" of is stored. (Cycle ■) Next, the decimal adder/subtractor 3 is set to the (A register 10 A register 1) addition mode, and the address adder 6 is set to the (address register 5 + address register 5) addition mode. The output of adder/subtractor 3 [2・bJ is the value “2” output from A register 1 and address adder 6
The data is stored in location 2'jtr of the register file 4 designated by . Further, the output "2" of the address adder 6 is stored in the address register 5 (cycle ■), and tickles ■ and ■ operate in the same manner as cycle ■, and the multiples "4・b" and "8・b '' are obtained and stored at addresses 4 and 8 of register file 4, respectively.

In cycle ■, decimal adder/subtractor 3 receives (A register 1 + B
Register 2) addition mode is +1 for address adder 6
Each mode is set, the data "9.b" output from the decimal adder/subtractor 3 is stored in the A register 1, and at the same time, the register file 409 output from the address adder 6 and designated by the procedure "9" The address is also stored.

This ends the multiple generation sequence.

Then, the 8-digit multiplier r 64668946 shown in FIG.
Multiples are also generated for J in the sequence shown in FIG.

Then, in the same way as above, "10・b" is stored in A register 1.
However, the B register 2 holds rbJ. (Cycle ■) Next, the decimal adder/subtractor 3 is set to the subtraction mode (A register 1 - B register 2), and the address adder 6 is set to the 11 mode, and the data output from the decimal adder/subtractor 3 is set to "9 fist b" is stored in the A register 1, and at the same time, it is also stored at address 9 of the register file 4 designated by the value "9" output from the address adder 6. Then, the output of the address adder 6 is stored in the address register 5.
9" is stored. (Cycle ■) Then, it operates in the same way from cycle ■ to cycle ■, and the multiples ``8・bJ , r7・bJ , [s・bJ
.

``4・bJ is calculated, ``8'' in register file 4.

They are stored at addresses r7J, r6j, r5J, and r4J, respectively.

Note that in the present invention, A register 1. B register 2.
Decimal adder/subtractor 3. Register file 4゜Address register 5. The multiplicand multiple generation circuit composed of the address adder 6 and digit shifter 7 is mostly used in multiplication processing, and the decoder 9 also outputs invalid decimal data for each digit to the multiplier held in the operand register 8. The illegal decimal data detection circuit that checks can be used,
The amount of hardware added by the present invention is small.

〔Effect of the invention〕

As explained above, the present invention examines each digit of the multiplier to determine the combination of numbers used, and generates the minimum number of multiples of the multiplicand used in decimal multiplication that include this combination. This is effective in minimizing the generation of multiples and speeding up decimal multiplication.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
3 and 4 are diagrams showing operation sequences for explaining the operation of FIG. 1, and FIGS. 5, 6, 7, and 8.
The figure is an explanatory diagram of the operation of the multiple generation sequence. 1...A register, 2...IIIB register, 3
・・・ψ・Decimal adder/subtractor, 4@・・・Register file,
5...φ address register, 6...Q address adder, 7...@-digit shifter, 8...number-operand register, 9. ..., decoder, 10... control circuit. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 77 Text Ikure II II[lI[[1JVlW 5e8Figure

Claims (1)

[Claims] A decimal adder/subtractor that can calculate n±1 times or 2n times the value of the multiplicand (n: an integer), and a decimal adder/subtracter that stores the operation result of this decimal adder/subtracter at the address indicated by the multiple value after the operation. A register file that has a storage function, and a multiple that examines each digit of the multiplier to determine the types of numbers actually used among numbers 1 to 9, and generates the smallest combination of multiples that includes all the numbers found. a decoder for selecting a generated sequence;
A decimal multiplication system comprising: a control circuit that controls multiple generation operations for the decimal adder/subtractor according to instructions from the decoder.