JPH02100354U - - Google Patents

Info

Publication number
JPH02100354U
JPH02100354U JP890589U JP890589U JPH02100354U JP H02100354 U JPH02100354 U JP H02100354U JP 890589 U JP890589 U JP 890589U JP 890589 U JP890589 U JP 890589U JP H02100354 U JPH02100354 U JP H02100354U
Authority
JP
Japan
Prior art keywords
input circuit
high frequency
frequency receiver
circuit
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP890589U
Other languages
English (en)
Other versions
JPH087705Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989008905U priority Critical patent/JPH087705Y2/ja
Publication of JPH02100354U publication Critical patent/JPH02100354U/ja
Application granted granted Critical
Publication of JPH087705Y2 publication Critical patent/JPH087705Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)
  • Filters And Equalizers (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】
第1図乃至第4図は本考案の一実施例を示し、
第1図はBSチユーナの入力回路を示すブロツク
図、第2図はアンプのトランジスタに接続した直
列共振トラツプ回路を示す解説図、第3図は直列
共振トラツプ回路の特性を表すグラフ、第4図は
入力回路の回路パターンに設けたインダクタ部を
示す一部切欠平面図であり、第5図は従来例を示
すBSチユーナの入力回路を示すブロツク図であ
る。 14…入力回路、15…アース、16…コンデ
ンサ、17,21,22…直列共振トラツプ回路
、18…トランジスタ、19…コレクタ、20…
コイル、23…IF妨害信号抑圧回路。

Claims (1)

    【実用新案登録請求の範囲】
  1. 高周波受信機の入力回路に於て、該入力回路に
    配設したアンプのトランジスタのコレクタに接続
    されたコイル等の、信号経路に介装した複数のイ
    ンダクタ素子にコンデンサを夫々直列に接続し、
    アースに接地させて複数の直列共振トラツプ回路
    を構成したことを特徴とする高周波受信機のIF
    妨害信号抑圧回路。
JP1989008905U 1989-01-28 1989-01-28 高周波受信機のif妨害信号抑圧回路 Expired - Lifetime JPH087705Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989008905U JPH087705Y2 (ja) 1989-01-28 1989-01-28 高周波受信機のif妨害信号抑圧回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989008905U JPH087705Y2 (ja) 1989-01-28 1989-01-28 高周波受信機のif妨害信号抑圧回路

Publications (2)

Publication Number Publication Date
JPH02100354U true JPH02100354U (ja) 1990-08-09
JPH087705Y2 JPH087705Y2 (ja) 1996-03-04

Family

ID=31215181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989008905U Expired - Lifetime JPH087705Y2 (ja) 1989-01-28 1989-01-28 高周波受信機のif妨害信号抑圧回路

Country Status (1)

Country Link
JP (1) JPH087705Y2 (ja)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275910A (en) * 1975-12-20 1977-06-25 Hitachi Ltd Vhf tuner input circuit
JPS6030626U (ja) * 1983-08-04 1985-03-01 アルプス電気株式会社 トラツプ回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6030626B2 (ja) * 1982-10-09 1985-07-17 幸晴 松下 布類の折曲方法と折曲装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5275910A (en) * 1975-12-20 1977-06-25 Hitachi Ltd Vhf tuner input circuit
JPS6030626U (ja) * 1983-08-04 1985-03-01 アルプス電気株式会社 トラツプ回路

Also Published As

Publication number Publication date
JPH087705Y2 (ja) 1996-03-04

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term