JPH0197883A - Apparatus for integrating moving target image - Google Patents

Abstract

PURPOSE:To integrate a moving target images, by performing the reading of frame memories at addresses, to which offsets are applied in correspondence with the moving speeds of a target. CONSTITUTION:The relative moving speed of a target is detected as components in the directions (x) and (y) with a detector 5. Converted values K and L of said detected values at addresses on a screen are subtracted from outputs I and J of an X address counter 4a and a Y address counter 4b in an X adding and subtracting device 6a and a Y adding and subtracting device 6b. The offset addresses are obtained, and a frame memory A 2a and a frame memory B 2b are accessed. Then, a target position gN-1 of the image of the (N-1)th frame is inputted into another input of an operator 1. An output at every corresponding point, which agrees with the target position, is obtained. Therefore the integrated value of the moving target signals is obtained as the output of the operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for integrating a target signal in nine images.

[Conventional technology]

FIG. 2 is a block diagram showing an example of a conventional device.
In the figure, (l) is an arithmetic unit that performs weighted addition of two sets of video signals, (2) is a frame memory for storing the arithmetic unit output and reapplying it to the arithmetic unit input, and (31
is a 7-frame timing generator for generating addresses for frame memory (2).

(4a) is the X address 0 address counter 4. which counts the X direction address of the frame memory (2). (4b) is the Y7 address counter that counts the X-direction address 0 address of frame memo I+ +21. (9a) and (9b) are the signals that reset the X and Y address counters (4a) and (4b), respectively. (toa ), (1ab) is
, Y7t"l/Xcow/J (4a), (4b) clocks.

Next, I will explain the operation. Original video signal fN (Eng., J
) is input to one input terminal of the computing unit (1), and the video signal gN-1 (1, J) from the frame memo 1/2) is input to one input terminal of the computing unit (1).
Weighted addition is performed inside the arithmetic unit (1), and the output g
N (engineering, J) is obtained. The relationship between gN (work + J), fN (work, J) and gN-1 (work tJ) as shown in Fig. 2 is usually used. In addition, I and J represent the addresses in the X direction and X direction of the screen, and mean that the calculation is performed between corresponding pixels on one screen.
N, (N 1) are the Nth frame, (N-
1) It is a subscript indicating the th frame. Also, the frame memory (address 21 is X I + upper set 9a from the frame timing generator (3)), the X clock (1
oa) and Y I+ upper set 9+), Y clock (1ob5) and the X address counter (
4a) and a Y address counter (4b).

[Problem that the invention seeks to solve]

Since the conventional device is configured as one or more, if the target is stationary at the same coordinate point (CXIJ).

The signals of the (N-1)th frame and the Nth frame can be added in correspondence, and an integral effect can be obtained, but when the target is moving, it is only possible to add disparate points, and the integral There were problems such as reduced effectiveness and poor use.

This invention was made to improve the above-mentioned problems, and aims to obtain an integral effect on a moving target.

[Means for solving problems]

The image integrating device according to the present invention reads the address of the frame memory, which is the input signal of the arithmetic unit, at a value corresponding to the speed of the target, so that the targets overlap when performing calculations between the pixels of the arithmetic unit. be.

[Effect]

In this invention. In the frame memory, when the arithmetic unit output signal is written, it is stored at the same address position as the 1M video signal, but when read, the signal is read from the offset X and Y address positions according to the target speed.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.
D, +11~(4! has the same function as the conventional device. (51 is a target relative speed detector -(
6a) and (6h) are X and Y adder/subtractors, respectively, and X and Y address counters (4a), respectively. (4b)
and the output of the target relative speed detector (5). (7a) and (7b) are memory inputs, respectively.

This is a memory output switch.

With the image integration device configured as described above, the relative moving speed of the target can be determined by the relative speed detector + 51!
: D, VEI, o(X), VmLo(Y), X,
Detects each Y direction component and converts this value into an on-screen address K, LfX address counter 41 (4a).

Y address counter (4b) each output, J to X adder/subtractor (6a), Y adder/subtractor (6b) subtract knee K, J-L 1) Obtain, 1st. When you access the second frame memory (2a) (2b), it's K! the law of nature, (
Target position B-1(1-) of the image of the N-1)th frame
K, J-L) to the other input of the arithmetic unit (1).

By applying fN (work, J) to one input, an output for each corresponding point whose target position coincides can be obtained as gN (work, tJ).

In the example shown in FIG. 1, two frame memories A and B are used, and the configuration is such that there is no conflict between writing and reading.

As above, K, the output of the arithmetic unit is gN (engineering, J) =
−fm(E′) + W 1 ge−, (I
-K, J--I,), it becomes possible to integrate the moving target signal.

Also, based on the frame start signal allK generated by the frame timing generator (3), the memory output switch (7a), memory input switch (7b), ! Switch (8a), ! The switch (8b) is alternately and synchronously switched, and in one combination, the address (I-K, J--L) of the second frame memory B (2b)
K, X switch (8a), Y switch (8a) so that
b) is connected, and the output of the second frame memory B (2b) is taken out from the memo 11 output switch (7a).

In addition, the K, X switch (8a), Y
The switch (8b) is connected and the first frame memory A (
Writing is performed to the input of 2a) through the memory input switch (7b). In the other remaining combination, the above operation is performed with frame memory A and frame memo IJB swapped.

Through these, two frame memories are written and read in parallel, ensuring independence of memory contents and preserving old and new data.

Continue running the signal processing algorithm.

In the above embodiment, only a single moving target was described, but it is clear that by providing circuits in parallel, integration can be performed for moving targets at multiple speeds.

〔Effect of the invention〕

As described above, according to the present invention, the reading of the frame memory is configured to be accessed at an address with an offset according to the moving speed of the target. This has the effect of allowing the integration of

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an image integrating device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a conventional device. In the figure, (1) is an arithmetic unit, and (2) is a frame memory. (3) is a frame timing generator, (4a) is
X address counter J, (4b) is Y address counter, (5) is 4-get relative speed detector,
(6a) is an X adder/subtractor, ((51)) is a Y adder/subtractor,
(7,a) is the memory output switch, C7111) is the memory input switch, (8a) is the X switch, (8 is the Y switch, (9a) is the g I+ upper set (9b) is the Y
Reset, (10a) is X clock, (1ob
) is the X clock, and a9 is the frame start signal. Note that the same reference numerals in the two figures indicate the same or corresponding parts.

Claims (1)

[Claims] an arithmetic unit that performs weighted addition of an input image signal and a stored image signal; first and second frame memories that store the output of the arithmetic unit; and a first and second frame memory that stores the output of the arithmetic unit; a memory input switch for switching the input to the second frame memory, a memory output switch for switching the output of the first frame memory and the second frame memory, and inputting the output to one input terminal of the arithmetic unit;
The X and Y address counters create the Y addresses I and J from the clock, and the X and Y direction components of the relative movement speed of the target are detected, and the conversion values K and L of the X and Y direction components to on-screen addresses are calculated. a target relative speed detector that generates;
The X address I of the above X address counter is converted to the above converted value K
The X adder/subtractor obtains the subtraction I-K with
A Y adder/subtracter that obtains L, the X, Y address counter, and a Y adder/subtracter between the X, Y adder/subtracter and the first and second frame memories, and an address of the first frame memory (
I, J) or (I-K, J-L), and the address of the second frame memory (I-K, J-L).
or (IJ), and a frame timing generator that generates the timing and clock necessary for each of the above-mentioned switches and the counter. Device.