JPH0194762A - Image processor - Google Patents

Abstract

PURPOSE:To execute various kinds of image processing at a high speed without complicating the constitution of circuits by executing editing together with image recognizing after executing the shading correction of photoelectrically converted image data, and recording the image of the data through a buffer circuit. CONSTITUTION:A CCD 103 receives light from an original and outputs an analog signal to indicate the density of each picture element serially. This analog signal is converted sequentially into an 8-bit digital signal for each picture element by an 8-bit AD converter 201, and further, this digital signal is corrected by a shading correcting circuit 202. This circuit 202 carries an optical system out of an original setting area, irradiates a fitted white color board, accumulates data for one main scanning at the time of reading scanning with the CCD 103, and adds correction to actual data. These corrected data is sent to an image recognizing part 204 and an editing circuit part 203 in parallel, and the image is recognized and edited. The output is sent to a picture recording part 210 of an can be executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image processing apparatus that processes and converts read image data in correspondence with a document image.

[Prior art]

A conventional image reading device that processes and converts a read image in accordance with a document image has a microcomputer,
This microcomputer performs the above processing and conversion. However, since there is a limit to the processing speed of microcomputers, it has been difficult to quickly output information that has been edited and processed in real time for each pixel.

Therefore, the present applicant proposed an image processing apparatus that enables high-speed, real-time image processing in Japanese Patent Laid-Open No. 59-62885 and other publications. The devices disclosed in these applications collectively preset processing information for one main scanning line or a plurality of main scanning lines in hardware, and perform processing corresponding to each pixel using hardware.

That is, the address of the changing point of the processing conditions in each editing process is stored, the address of the changing point and the main scanning address are constantly compared by a comparator, and when the results of this comparison match, the desired editing process is started. I am trying to execute it.

However, in any device, there is a problem that when the number of areas and types of processing in a main scanning cycle are large, the number of change points increases, and the number of comparators increases by the increase in the number of change points.

For example, if 8 types of processing are performed per main scanning cycle (5000 pixels) and each type of processing has 10 change points, 8x10 = 80 comparators and registers (13 bits) are required. , there is a problem that the hardware circuitry increases rapidly.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an image processing device that can perform various image processing on image data at high speed and without complicating the configuration. .

Another object of the present invention is to provide an image processing device that can efficiently execute arbitrary processing for each region of an image.

Another object of the present invention is to provide a means for inputting image data representing each of a plurality of pixels, and a plurality of image processing conditions corresponding to each pixel or a plurality of consecutive pixels of the image data inputted from the input means. The present invention provides an image processing device comprising means for forming processing data, and processing means for processing image data input from the input means for each pixel based on the processing data formed by the forming means. .

Another object of the present invention is to provide an image processing apparatus that is capable of specifying a desired area of a document image and performing desired image processing within and outside the area with a simple configuration.

These and other objects of the present invention, as well as the effects of the present invention, will become clear from the following description.

〔Example〕

FIG. 1 is an external view of the image reading device.

This device includes a document table 101, a document presser 102, a line sensor CCDIO3 consisting of approximately 5000 light receiving elements arranged in a line for image reading, a fluorescent lamp 104 for illuminating the document, mirrors 105, 106, 107 and an imaging lens 108. Fluorescent lamp 104 and mirror 105
A first optical unit equipped with mirrors 106 and a second optical unit equipped with mirrors 106 and 107 scan the document in the Y direction by moving at a speed ratio of 2:1, and the document images are sequentially focused on the CCD 103. Image.

FIG. 2 is a block diagram showing the overall circuit configuration of the image reading device shown in FIG.

CCD103 (for example, Toshiba TCD 106C, 50
00 pixel) receives light from the original and serially outputs an analog signal indicating the density of each pixel. This analog signal is converted into 8 bits for each pixel by an 8-bit A/D converter 201.
The signal is sequentially converted into a bit digital signal, and this digital signal is further corrected by a shading correction circuit 202.

The shading correction circuit 202 takes the optical system outside the document placement area, irradiates the white plate attached there, and stores data for one main scan in the memory when reading and scanning is performed by the COD 103. Based on this memory data,
Add corrections to actual image data. The shading-corrected data is sent to the image recognition section 204 and the editing circuit section 203. In addition, a buffer 205, a main scanning address generation circuit, a COD drive 206, a buffer control circuit 207, a CPU circuit section 208, and an operation section 209 are provided.
10 etc. is supplied to an external device.

FIG. 3 is a diagram showing a state in which a document is placed on the document table 101 of the document reading device.

From the standard coordinates SP of the document table 101 to the main scanning direction (CCD1
03 (the arrangement direction of the light-receiving elements) is set to
．． When the moving direction of the second optical unit) is Y, by moving the optical unit and pre-scanning before reading the original image, the points Pi (Xi, Yl) and P2 (
X2. Y2), point P3 (X3.Y3), point P4 (
X4. Y4) is detected by the image recognition unit 204. The document cover 110 is mirror-finished so that image data in areas other than the area where the document is placed is always black data. Main scanning and sub-scanning are performed so that the entire glass surface is pre-scanned.

FIG. 4 is a circuit diagram showing details of the image recognition section 204.

The main scanning counter 351 is a down counter and indicates the scanning position during the main scanning line.

This counter 351 is controlled in the main scanning direction (X direction) by a horizontal synchronizing signal H8YNC generated prior to each main scanning.
is set to the maximum value, and each time the image data clock CLK is input, it counts down and represents the pixel position in the main scanning direction.

The sub-scanning counter 352 is an up counter, and is reset to rOJ at the rise of VSYNC (image leading edge signal) whose logic level becomes high during the sub-scanning operation.
It is counted up by the 3YNC signal and represents the scanning position in the sub-scanning direction.

During scanning, after shading correction by the shading correction circuit 202, the image data VIDEO is binarized by a comparator (not shown) and is sent to an 8-bit shift register 301. Note that during each scan, C
PO 208 provides a predetermined fixed slice level to the comparator.

When the 8-bit input is completed, the gate circuit 302
It is checked whether all of the 8-bit data in the shift register 301 is a white image (0 level) representing the background of the original. If all of the data is white, the gate 302 is set to "1".
Output.

After the start of pre-scanning of the original, the flip-flop 304 is set when all consecutive 8-bit image data become white (0 level) for the first time.

The flip-flop 304 is reset in advance by VSYNC (image leading edge signal output at the start of forward movement). Thereafter, the set state is maintained until the next VSYNC comes. The main scanning counter 351 counts down by a clock CLK synchronized with the pixel output of image data from the comparator, and when the flip-flop 304 is set, the value of the main scanning counter 351 at that time is loaded into the latch 305. be done. This value is
This is the coordinate value of l.

Further, the sub-scanning counter 352 counts up a signal synchronized with the scanning of each line, and the value (number of lines) of the sub-scanning counter 352 when the flip-flop 304 is set is loaded into the latch 306. This value is the coordinate value of Yl. Therefore, point Pi (Xi,
Yl) is obtained.

Further, each time the gate 302 outputs "1", the value from the main scanning counter 351 is loaded into the latch 307.

The value from the main scanning counter 351 when all consecutive 8-bit image data are white for the first time is the value from the latch 3.
07, this value is compared by comparator 309 with the data in latch 310 (which is set to the maximum value in the X direction at VSYNC).

If the data in latch 307 is small, the output of comparator 309 becomes active, which causes the data in latch 307 to be loaded into latch 310. Also, at this time, the value of the sub-scanning counter 352 is
11. This operation ends until the next 8 bits enter shift register 301.

In this way, when the data comparison between the latch 307 and the latch 310 is performed for the entire image area, the minimum value in the X direction of the document area remains in the latch 310, and the coordinate in the Y direction at this time remains in the latch 311. That is, the main scanning counter 351
Since is a down counter, the coordinate corresponding to the minimum value in the X direction represents the coordinate farthest from SP in the main scanning direction. These coordinates are point P3 (X3.Y3).

The flip-flop 312 is a flip-flop that is set when image data representing a continuous 8-bit white image appears for the first time in each main scanning line, and is reset by the horizontal synchronization signal H8YNC. It is set when all the image data becomes white, and is held until the next l (SYNC).This flip-flop 3
12, the value of the main scanning counter 351 corresponding to the position of the first white signal appearing in one line is loaded into the latch 313. Then, a comparator 316 compares the value of the latch 313 and the value of the latch 315. The latch 315 is preset to the minimum value in the X direction, ie, "0" when VSYNC occurs.

If the data in latch 315 is less than or equal to the data in latch 313, comparator 316
becomes active and the data in latch 313 is loaded into latch 315. This operation is H8YN
This is done between C and HSYNC.

If the above comparison operation is performed for the entire image area, latch 3
15 remains the maximum value of the document coordinates in the X direction, that is, the X coordinate of the white signal at the point closest to the scanning start point in the main scanning direction. This is x2. Further, when the output of the comparator 316 becomes active, the value from the sub-scanning counter 352 is loaded into the latch 318. This becomes Y2, and point P2 (X2.Y2) is obtained.

The latches 319 and 320 are loaded with the values of the main scanning counter 351 and the sub-scanning counter 352 each time 8-bit continuous white image data appears in the entire image area. Therefore, the count values of the counters 351 and 352 when the last continuous 8-bit color image data appears when the pre-scanning of the original is completed remain in the latches 319 and 320, and the point P4 (X4.Y4 )
It is.

Above 8 latches 308.311.320.318.3
The data line of 05.310.315.319 is CP
The CPO 208 reads this data at the end of the forward movement in the previous scan. As a result, the position and size of the original on the original table 101 are determined.

5 and 6 are the editing circuit section 2 shown in the second diagram.
03 is a detailed circuit diagram.

Editing memories 401 and 402 store image editing data (
In other words, it is a RAM that stores information for performing image processing. When MSEL (memory select signal) is set to the rHJ level, the Q output of the flip-flop 407 becomes high level, the selectors 403 and 405 are selected to the A side, and the editing memory 401 receives the COD address ( main scanning address). At this time, the selectors 404 and 406 select the B side, and the editing memory 402 is controlled by the microcomputer address. In this state, the editing memo IJ 402 is
It is connected to the address bus and data bus of the microcomputer in the circuit section 208, and the microcomputer can read and write freely.

By the way, when the editing memories 401 and 402 are connected to the COD address, the addresses of the editing memories 401 and 402 correspond to the pixel address of the CCD 103. In other words, memory address 1 corresponds to the 1st pixel of the COD, address n corresponds to the nth pixel, and the 5000-pixel C
As an editing memory using a CD, a memory of at least 5000 addresses is used, for example, 8 bytes (8 bits x 8). Therefore, processing data for processing the m-th pixel is written to address m in the image memory.

In addition, the editing memories 401 and 402 have 8 addresses per address.
In the above embodiment, bit 0 indicates "Image output prohibited," bit 1 indicates "Image output prohibited area is black," bit 2 indicates "Negative," and bit 3 indicates "Evaporation power." ”, bit 4゜5 is “γ correction level”, bit 6 is
Bit 7 stores image editing data indicating a "photo area," and bit 7 indicates an rAE area.

Editing memory 401 or 402 using FIG. 8 and FIG.
is set by the CPU circuit unit 208. An example of image editing data will be explained.

FIG. 8 shows the processing content on the original ORG, in which the operator specifies three arbitrary areas (I), (n), and (III) using the operation unit 209, and furthermore, the image of area (I) is For the image, white/black inversion processing and second γ correction processing are performed for the image, third γ correction processing and photographic processing are performed for the image in region (m), and image processing for region (m) is performed. Assume that an instruction is given to perform white mask processing on an image.

Note that 5o-ss indicates the pixel position in the main scanning direction.

In accordance with the above instructions, the CPU circuit unit 208 forms image editing data for the image signal of each scanning line and sets it in the editing memories 401 and 402. In addition, the designated area (I)
, (n), and (m) for images in document areas other than the first one.
γ correction processing is executed.

FIGS. 9(1), (2), and (3) show image editing data set in the editing memory corresponding to scanning lines (A), (B), and (C) shown in FIG. 8, respectively. In other words, the specified area (
I), (1, Image editing data for areas other than (II) is (00000100), (00101000) for area (I), and (0 for area (II)).
0001110), and (10000
000) is written at the address corresponding to pixel position 5o-88 in the main scanning direction. Incidentally, in FIG. 9, to prevent the drawing from becoming complicated, consecutive pieces of the same data are indicated by "~" marks.

Furthermore, the existence of two memory systems such as editing memories 401 and 402 means that each line or multiple lines have M
This is to set the SL (memory select signal) to rHJ and rLJ to switch between the editing memory accessed by the microcomputer and the editing memory accessed by the COD address. In other words, when microcomputer access is enabled and editing information related to the next editing content is being written to one editing memory, read information from the other editing memory that has already been written is transferred to the bus 409 for COD image editing. It is read out and used.

To switch image editing data to new data, use MSE
By switching the level of L, the edit memory accessed by the COD address can be switched to the edit memory in which new edit data has been written by the microcomputer. In other words, if the MSEL level is changed line by line,
Edit data can be changed for each line at most. If the image editing data is not changed, that is, if the MSEL is not changed, the same image editing data written in the same editing memory is always used repeatedly.

CPU circuit unit 20 related to the formation of the above pixel editing data
8 will be explained below.

FIG. 10 is an external view of the operation section 209, and shows the document presser 10.
It consists of a digitizer part 162 provided at 2 for inputting editing conditions and editing coordinates.

By pressing and holding the coordinate input section 150 of the digitizer section 162 with the pointing pen 151, the X coordinate and the X coordinate from the reference point 166 are transmitted to the CPU circuit section 208. Further, 1, 152 to 161 are keys for inputting various editing conditions, and these keys are used with the pointing pen 1.
51, data indicating the corresponding editing condition is transmitted to the CPU circuit section 208. In addition, document presser 1
A numeric keypad for numerical input and a clear key 170. Display 1 for numerical display
732 Start key 17 for instructing the start of image reading operation
1 and a stop key 17 for instructing to stop the image reading operation.
2 is provided. Information on these keys 170 to 172 is also transmitted to the CPU circuit section 208.

Figures 11 (A), (B) and Figure 12 (A).

(B) is a flowchart showing the control procedure of the microcomputer of the CPU circuit section 208 related to the formation of image editing data, and this procedure is written in advance in the memory ROM built into the microcomputer.

FIGS. 11(A) and 11(B) are flowcharts showing control procedures regarding input determination from the digitizer part 162.

When keys 152 to 160 of the digitizer section 162 are pressed, it is determined in step 701 that any editing key has been turned on, and data indicating the editing conditions corresponding to the pressed key is stored in the built-in memory RAM of the CPU circuit section 208. is stored in Next, when two points (indicating two corners of a desired rectangular area) on the diagonal line of the coordinate input section 150 are pressed with the pointing pen 151, the coordinates indicating the two points (XI, Yl, X2, Y2 ) is stored in memory RAM.

Next, the editing conditions of the pressed editing keys 152 to 160 are determined, and depending on the conditions, Flag information on the memory RAM is
- Turn on F1ag9 (steps 706-723).

That is, if the key 152 or 153 that instructs trimming of the specified area is pressed, the process advances from step 706 to step 707, and if the key 152 is pressed that instructs the outside of the trimming area to be trimmed, then in step 708, the flag is
Turn on l. In addition, if the key 153 makes the outside of the trimming area white, then in step 709 F1a, g2
Turn on.

Further, if the key 154 or 154 for specifying masking of a specified area is pressed, steps 706 and 710
The process then proceeds to step 711, and if the key 154 is to be masked in black, F1ag3 is turned on in step 712. If the key 155 is to be masked with white, F1ag4 is turned on in step 713.

If the key 156 instructs to process the specified area in photo mode, steps 706, 710, 7
14, the process proceeds to step 715, and FIag5 is turned on.

If the key 156 instructs to process the specified area in photo mode, steps 706, 710, 7
14, the process proceeds to step 715, and F1ag5 is turned on.

Further, if the key 1-57 instructs to process outside the specified area in photo mode, steps 706 and 710,
Proceed to step 719 from 714 and 716, and F1ag6
Turn on.

If the key 158 instructs to output the specified area as a negative image, steps 706 and 7
Step 10,714,716,718 proceeds to step 719, and F1ag7 is turned on.

If the key 159 instructs to output the area outside the specified area as a negative image, steps 706 and 7
Step 7 from 10,714,716°718.720
Proceed to step 21 and turn on Flag8.

If the key 160 supports outputting the specified area at a desired density, step 706°710.714
, 718, 720, 722 to step 23, and F
Turn on 1ag9.

As described above, the coordinate data representing the desired area of the document input by the operator and the data corresponding to the editing conditions for images within or outside the desired area are stored in the memory R.
Set to AM. Note that multiple areas may be specified on the manuscript (and different types of editing conditions can be set for the specified areas).

FIGS. 12(A) and (B) show that the CP is
The start key 171 is activated based on the coordinate data and editing condition data stored in the memory RAM of the U circuit section 208.
CPU circuit unit 20 when reading the original after being pressed
FIG. 8 is a flowchart showing the control procedure of step 8;

When the start key 171 is pressed, the CPU circuit section 208
performs the following processing depending on what mode is set in the editing area (memory RAM).

First, data is set in the editing memories 401 and 402 to set initial values, such as character mode, trimming, no masking, and intermediate density level (step 749).

And in Steve Love 750, 751, 752,
It is determined whether the current scanning position of the original (the line read by the CCD 103) corresponds to the designated area (editing area) as described above.

Further, in steps 753 to 788, it is determined which flag is set in the memory RAM, and a pit set indicating the editing condition corresponding to the flag of the trick is set in the editing memory.

Note that steps 753 to 769 are processes performed before the scanning position reaches the designated area and after passing through the designated area, and steps 771 to 788 are processes performed while the designated area is being scanned.

Assume that the key 152 is now pressed and Flagl is turned on. When starting reading the original, the process advances from step 750 to step 757. Therefore, when it is determined in step 753 that Flagl is on, the process in step 754 is performed until the scanning position reaches the editing area, and bit O of the entire area of the editing memory is set to bit 0 to output black without outputting an image. 1,
Set bit 1 to 1. Next, if it is determined in step 770 that the editing area has been reached, step 7
71 to step 772. Then, the editing memory is set so that only the editing area is output as an image (bit O is 0, bit 1 is 1), and the area outside the editing area is black (bit 0 is 1, bit 1 is O).

After that, in step 752, when it is determined that the editing area has been passed, the process goes from step 753 to step 754 again, and bit 0 and bit 1 of the entire editing memory are set to 1 and 0, respectively, so as to become an image point.

Also, when the trimming white key 153 is pressed and F1ag2 is turned on, bit 0 of the editing memory is set to 1 and bit 1 is set to 0 so that white is output until the editing area is reached at steps 755 and 756. When the editing area is reached, the image is output only in the editing area (bit O is 0, bit 1 is 0) in steps 773 and 774, and other than that, images are prohibited and white is output (bit O is 0). 1
, bit 1 is set to O), the editing memory. Next, when the editing area ends, bit O and bit 1 of the entire editing memory are set to 1 and 0 so that the image is prohibited again in step 756 and all white is output.

Also, when the masking black key 154 is pressed and F1ag3 is turned on, steps 757 and 758 set bit 0 to 0 and bit 1 to 1 in the editing memory so that all images are output until reaching the editing area. is set, and when the editing area is reached, the image becomes black only in the editing area by steps '775 and 776 (bit O is set to 1, bit 1 is set to 1).
), otherwise the editing memory is set so that the image is output (bit 0 is 0, bit 1 is 1).

Next, when the editing area ends 1, bit 0 of the entire editing memory is O and bit 1 is 1 so that the entire image is output again.
(steps 757 and 758).

Also, if the masking white key 155 is pressed and F1ag4 is turned on, steps 759 and 760
Until the editing area is reached, bit 0 of the entire editing memory is set to 0 and bit 1 is set to 1 so that the entire image is output. When the editing area is reached, the image is whitened only in the editing area in steps 777 and 778. (bit 0 is 1, bit 1 is 0), and other than that, the editing memory is set so that the image is output (bit 0 is 0, bit 1 is 1). Next, when the editing area ends, bit 0 of the entire editing memory is set to 0 and bit 1 is set to O so that the entire image is output (steps 759, 760).

Furthermore, when the in-area photo key 156 is pressed and F1ag5 is turned on, bit 6 of the entire editing memory is set to 0 so that the image is output in character mode until it reaches the editing area in steps 761 and 762. set. When the editing area is reached, the editing memory is set in steps 779 and 780 so that only the editing area is subjected to photo processing (bit 6 is 1), and the rest is text processing (bit 6 is 0). Next, when the editing area ends, bit 6 of the editing memory is set to 0 so that the entire image is subjected to character mode processing (steps 761 and 762).

In addition, when the out-of-area photo key 157 is pressed and F1ag6 is turned on, bit 6 of the entire editing memory is set such that all images are output in photo mode until the editing area is reached in steps 763 and 764. Set to 1. When the editing area is reached, steps 781 and 782 are executed to set the editing area to character mode (bit 6 is set to 0).
), and otherwise set the editing memory so that it is photo processing (bit 6 is 1). Next, when the editing area ends, bit 6 of the entire editing memory is set to 1 so that the entire image is processed in photo mode (step 763,
764).

Also, if the area negative key 158 is pressed and F1ag7 is turned on, bit 2 of the entire editing memory is set to O so that the entire area is output as a positive image until the editing area is reached in steps 765 and 766. do. If the editing area is reached, steps 783, 7
84, only the editing area can be set to negative mode (bit 2
The editing memory is set so that the mode becomes 1) otherwise the mode is positive (bit 2 is 0). Next, when the editing area ends, bit 2 of the entire editing memory is set to 0 so that the entire image becomes a positive image (step 7).
65°766).

In addition, if the out-of-area negative key 159 is pressed and F1ag8 is turned on, bit 2 of the entire editing memory is set to 1 in steps 767 and 768 so that the entire area is output as a negative image until the editing area is reached. set. If the editing area is reached, step 785,
786, the editing memory is set so that only the editing area is in the positive mode (bit 2 is set to O) and the rest is in the negative mode (bit 2 is set to 1). Next, when the editing area ends, bit 2 of the entire editing memory is set to 1 so that the entire image becomes a negative image (steps 767 and 768).

In addition, if the area density key 160 is pressed and F1ag9 is turned on, editing is performed so that the density is set to "F5" in the normal first γ correction process until the editing area is reached in step 769. Bits 4 and 5 of entire memory
Set O to . And if you reach the edit area,
In steps 787 and 788, bits corresponding to the γ correction processing in which only the editing area is specified are set to bits 4 and 5, and in other cases, bits 4 and 5 are set to 0. Next, when the editing area ends, the first γ processing should be performed on the entire image (bits 4 and 5 of the entire editing memory are set to 0 (step 769)).

As described above, the CPU circuit unit 208 sets appropriate conditions in the editing memory in relation to the scanning position in accordance with the editing key and area designation.

Next, image processing according to image editing data will be explained.

The shading corrected image data is sent to a trimming block 410 shown in FIG.

In the image data of this example, rFFJ represents black, "00" represents white, and the larger the number, the closer it is to black (
Become.

Further, bits 0 to 6 shown in FIG. 6 are signals sent from the selector 405 or 406 shown in FIG. 5, and are image editing data.

The trimming block 410 includes an AND circuit 450.4.
51, an OR circuit 452, and an inverter 453, eight sets are provided for each bit of digital image data of 8 bits per pixel, and the other seven sets are omitted from the illustration. When bit 0 of the image editing memory sent from the editing memory 401 or 402 is "1", the output of the image signal is prohibited by the gate 450, and the information of bit 1 of the editing memory is output as image data. For this reason, by specifying bit 1 for an area where image data is prohibited by bit 0, it can be selected as black or white output.

The circuit block 411 has eight OR gates 454 (seven of which are omitted), and bit 3:
The image signal can be forced to black.

The circuit block 412 has eight EX-OR gates 455 (seven of which are omitted in the illustration), and bit 2 is set to r.
When set to HJ, the image signal is inverted and becomes a negative image.

The γ conversion ROM 413 (for example, MB71) receives image data at addresses O to 7, and outputs a γ conversion signal using the image data as an address. In this case, bits 4 and 5 indicate the 4 bits stored in the ROM 413 in advance.
One can be selected from the types of conversion tables for γ conversion.

Bit 6 is sent to buffer 205 as one piece of image data.

Bit 7 (not shown) is used as a signal indicating the area of the document to be subjected to AE, and only when bit 7 is rHJ, it is used as a gate signal for AE sample information.

FIG. 7 is a diagram showing details of the buffer 205 and buffer control circuit 207 in FIG. 2.

The buffer 20'5 enlarges, reduces, and moves the image, and converts image data synchronized with the COD reading clock (each CCDCLK) into image data synchronized with the printer synchronization clock (PCLK).

The image memories 506 and 507 have a double buffer memory configuration, and can each store one line of image data. In other words, a memory having a configuration of 8 bits x 9 bits is used.

Next, a case in which image data is written to the image memory 506 will be described as an example.

First, when the address selector 504 selects A, the address of the write address counter 502 is transferred to the image memory 50.
6 is input and image data 220 is written to memory.

At the same time, the address selector 505 of the memory 507 selects the read address counter 503, and the output of the memory 507 is selected by the selector 509 and taken out as image data. Then, for the next line, switching between read and write is performed by the horizontal synchronization signal (H3YNC), and the above operation is reversed.

Furthermore, during a write operation, when the write address counter 502 is operated by thinning CCDCLK by a BRM (binary rate multiplier, for example, SN7497), the image memory 506 or 5
07, the image data of the thinned out location is skipped and stored. Therefore, the image data is reduced.

Similarly, by thinning out the clocks input to the read address counter 503 by the BRM 510, the image data 221 is output redundantly only at the thinned out clocks. Therefore, the image data is expanded according to the degree of thinning.

In this case, the start addresses of the write address counter 502 and read address counter 503 can be freely set using the microcomputer, but if the same value is set for both counters, the image will not move, but if different addresses are set, the image will not shift in the main scanning direction. You can move.

Further, the image data 220 is added with a 1-bit photographic area signal and sent from the editing circuit section 203 to the buffer 205 as data of 9 bits in total, including 8 bits of image and 1 bit of control signal. The images are also enlarged and reduced in size. therefore,
Even after scaling, there is a one-to-one correspondence between the control signal and the image. The scaled and edited image data and control signal are sent to the recording unit 210.

Although not shown, in the recording unit 210, according to the control signal of the photo character added to the image data of each pixel,
It changes the recording characteristics to form images that match each text/photo.

In the above embodiment, only one bit of the control signal is enlarged or reduced together with the image signal, but a large number of control signals may be enlarged or reduced together with the image signal. This allows various signals corresponding to the image signal to be sent.

In addition, in the above embodiment, the editing memory is provided corresponding to the CoDI pixel, but the editing memory is provided for a plurality of consecutive pixels (for example,
8 pixels) may be considered as one block, and an editing memory may be provided corresponding to this block. According to this, the capacity of editing memory can be reduced. However, in this case, the accuracy of image editing deteriorates, but the calculation speed of the microcomputer becomes faster.

Further, in this embodiment, a digitizer is used as an input means for inputting the trimming area, etc., but a numeric keypad and keys representing X and Y may also be used. For example, X (
150~200mm), Y (50~100mm), press the "X" key "150*200*",'
The same thing can be achieved by sequentially inputting with the numeric keypad, such as "Y"Y"key*100*".

It is also possible to use voice input as another input means for trimming areas, etc., and the operations pressed on the numeric keypad can be directly inputted by voice, which can be used in place of the numeric keypad.

Further, it can also be realized by inputting an area determined by another microcomputer as an input means through serial communication.

Moreover, as another input means, the same thing can be realized by having the CPU read data stored in an IC card, a memory card, or the like.

In addition, although the editing RAM is used in such a way that all editing information is written in each pixel, it can also be realized by writing only changes in processing to the memory. Using this method saves the time required to write data to memory, but complicates the calculations.

Also, the capacity of the editing RAM was set to be the same as the number of main scanning pixels (
In this example, since a 5,000-pixel CCD is used, memory corresponding to 1 bit can also be used for 2 pixels, 3 pixels, etc. I can do it. In that case, editing accuracy will deteriorate (
For example, in the case of 1 bit for 2 pixels, the unit is 0.125 mm,
In the case of 1 bit for 3 pixels, the processing speed is 0.1875 mm), but the memory capacity is halved, 1/3, etc., and the memory capacity is reduced and the processing speed is improved. However, the same effects as the present invention can be obtained. In addition, in this embodiment, the image editing data is 8 bits for each pixel, making it possible to execute several types of editing processing for each pixel, but by increasing this number of bits, even more types of editing processing can be performed. In addition, the number of bits can be reduced if so many types of editing processing are not required.

〔effect〕

According to the configuration of the present invention described above, for example, in an image processing apparatus that edits and converts a read image in accordance with a document image, it is possible to prevent an increase in hardware circuitry, and also to This has the effect that processing can be performed at a position corresponding to the original image.

[Brief explanation of the drawing]

Figure 1 is an external view of the image processing device, Figure 2 is a block diagram of the image processing device, Figure 3 is a diagram showing a document placed on the document table, and Figure 4 shows details of the image recognition unit. The block diagram shown in FIG.
FIG. 6 is a block diagram showing details of the editing circuit section, FIG. 7 is a block diagram showing details of the buffer and buffer control circuit, FIG. 8 is a diagram showing an example of document processing by area, and FIG. 9 is a block diagram showing details of the editing circuit. 8 is a diagram showing an example of image editing data in the illustrated example; FIG. 10 is an external view of the operation unit; FIGS. 11(A), (B), and FIG. 12(A). CB) is a flowchart showing the control procedure of the CPU circuit section, 103 is a CCD, 203 is an editing circuit section, 20
8 is a CPU circuit section, 209 is an operation section, and 401 and 402 are editing memories.

Claims (1)

[Scope of Claims] Means for inputting image data representing each of a plurality of pixels; Means for setting desired image processing conditions for an image represented by the image data input from the input means; means for forming processing data representing a plurality of image processing conditions corresponding to each pixel or a plurality of consecutive pixels of image data input from the input means based on image processing conditions input from the input means; An image processing device comprising processing means for processing each pixel based on the processing data formed by the forming means.