JPH0193921A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress ringing by preparatorily changing an output by a first output circuit for a time determined by a delay circuit after the input of an input signal and changing the output to a prescribed voltage level with an essential driving force by the cooperation between the first and a second output circuits. CONSTITUTION:During the period from a time t0 to a time t1, the output is preparatorily changed only by the first output circuit 3 having a weak driving force. After the time t1, the output is changed to a desired voltage level with essential driving force by the cooperation between first and second output circuits 3 and 10. That is, the output change is preparatorily started by the first output circuit 3. Thus, the output is gently changed to reach the prescribed voltage level, and ringing is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to improvement of ringing in an output waveform in a semiconductor device.

[Conventional technology]

FIG. 3 is a diagram showing a conventional semiconductor device. In the figure, 13 and 14 are N-type transistors, and these N-type transistors 13 and 14 are connected in series and interposed between the power supply potential ■Co and the ground potential GND. Further, the gates of the N-type transistors 13 and 14 are configured to receive a first input signal S1 and a second input signal S2, respectively. Then, an output signal S is output from the node N3 between the N-type transistors 3° and 14. It is configured such that Ul is taken out.

Next, the operation of the semiconductor device configured as described above will be explained. First, the first and second input signals S, S2
The case where both are ``'' will be explained. In this case, since L'' is applied to the gates of N-type transistors 13 and 14, both N-type transistors 13 and 14 are cut off, and the output signal S becomes high impedance.

UT Next, the first and second input signals SS, S2 are respectively
The case of IT and 'l-1' will be explained. In this case, the L voltage is applied to the gate of the N-type transistor 3, so this N-type transistor 3 is cut off, while the N-type transistor “H” on gate 4
is applied, this N-type transistor 4 becomes conductive. Therefore, the output signal S. U□ becomes "L".

Next, the first. The case where f3 and the second input signals S 1 and S 2 are "'H" and 11 L 11 will be explained. In this case, 't-+' is applied to the gate of the N-type transistor 13, so the N-type transistor 13 becomes conductive, while the N-type transistor 1
Since L'° is applied to the gate of transistor 4, this N-type transistor 14 is cut off. Therefore, the output signal S
becomes H''.

UT Note that both the first and second input signals S and S are “
H'' is prohibited from being input to this semiconductor device, and the explanation will be omitted here.

The relationship between the first and second input signals S and S and the output signal S is summarized as shown in Table 1.

Table 1 [Problems to be Solved by the Invention] FIG. 4 shows an output signal S output from the semiconductor device shown in FIG. 3. These are the expected output waveforms when Uo is "l-1" and "L". In the figure, the horizontal axis shows time and the vertical axis shows the output voltage. 15 indicates the first and second output voltages. 16 is the output waveform when "HIT" and "L" are respectively given as the input signals S1 and S2 of 2, and "L" is given as the first and second input signals S1 and S2, respectively.
and 11 are the output waveforms when HIT is given. Note that Vll is the 'H' output judgment level, and ■
, is the "L" output determination level.

A characteristic feature that can be seen from the figure is that ringing occurs in the output waveforms 15° and 16. This ringing refers to the occurrence of an oscillating transient phenomenon in the output signal @SoU□ in response to sudden changes in the input signals S, S2. This occurs due to the capacitance of the circuit and the inductance of the circuit. Therefore, the output signal S is caused by ringing as shown in the figure. Ul momentarily reaches the output judgment level v11. There was a problem in that V was broken and malfunction occurred.

This invention was made to solve the above-mentioned problems, and aims to reduce ringing and obtain a highly reliable semiconductor device.

[Means for solving problems]

A semiconductor device according to the present invention includes: a first output circuit including a first transistor whose one electrode is connected to a reference potential and whose conduction is controlled by an input signal; a delay circuit which delays the input signal; a second output circuit including a second transistor having the same polarity as the first transistor, one electrode of which is connected to a reference potential, and conduction of which is controlled by the output signal of the delay circuit; The output is taken out from a connection point between the other electrode of the transistor and the other electrode of the second transistor.

[Effect]

According to the semiconductor device in this invention, the first J5
and a human input signal having a voltage level that causes the second transistor to conduct, the first transistor first conducts to preliminarily initiate an output change, and then after a time determined by the delay circuit. After the second transistor becomes conductive, the output is changed to a predetermined voltage level with the original driving force by the cooperation of both transistors. In this way, since the output change is first preliminarily initiated by the first transistor, the output change becomes gradual until the predetermined voltage level is reached, and ringing is reduced.

〔Example〕

FIG. 1 is a diagram showing an embodiment according to the present invention. In the figure, numerals 1 and 2 are N-type transistors with a small driving force, and the power supply voltage vvo. A first output circuit 3 having a small driving force is configured by being inserted in series between the output voltage and the ground potential GND. First and second input signals S2 and S2 are applied to the gates of N-type transistors 1 and 2, respectively,
The configuration is such that an output is taken out from a node N1 between both transistors 91.2. Further, D and D are first and second delay circuits, respectively, the first delay circuit D1 is constructed by connecting two inverters 4.5 in series, and the second delay circuit D2 is constructed by connecting two inverters 4.5 in series. It is constructed by connecting inverters 6 and 7 in series. These delay circuits D1 and D2 are configured to respectively delay the control signals S and S2 by a predetermined time and output them. 8.9 is an Nff1 transistor, which is an N-type transistor whose driving force is set to be larger than that of 2, and is inserted in series between the power supply potential Voo and the ground potential GND.
A second output circuit 10 having a larger driving force than the first output circuit 3 is configured. These N are 1 to 8 transistors,
The output signal of the first and second delay circuits D2 is input to the gate of transistor 9, and the output is taken out from node N2 of both transistors 8 and 9. Then, the node N1 and the node N2 are connected, and the configuration is such that the sum of the output of the first output circuit 3 and the output of the second output circuit 10 is extracted as the output signal S.
It is υd. However, the first and second output circuits 3.1
It is assumed that the sum of the driving forces of 0 is set to the same driving force as that of the conventional one shown in FIG.

Next, the operation of the semiconductor device configured as described above will be explained with reference to the output waveform diagram shown in FIG. 2. When "L II" is applied as both input signals S and S2, each transistor 1.2, 8.9 is all cut off, and the output is kept in a high impedance state.From this state, the time At t, when "H" is applied as the input signal S1 and "HI" is applied as the input signal S2, the N-pear transistor switches to the conductive state,
The N-type transistor 2 remains in a cut-off state, and the voltage of the signal output from the node N1 of the first output circuit 3 begins to rise. At this time, the input signal S1°S is simultaneously input to the input side of the delay circuit D2, and these signals are input to the input side of the delay circuit D1. Since the signal is delayed by a predetermined time by D2 and applied to the gates of the N-type transistors 8 and 9 at time t1, the N-type transistors 8 and 9 remain in a cut-off state during that time. Therefore, time t.

At time t1, an output waveform is obtained only from the output from the first output circuit 3. In this case, since the driving force of the first output circuit 3 is set small, the output waveform 11 (see FIG. ) has a much more gradual rise than the conventional output waveform 15 (FIG. 4).

Next, at time t1, H'' is input from the first delay circuit D1 to the gate of the N-type transistor 8, and the N-type transistor 8 is switched to a conductive state. Since L is subsequently input to the gate of N"1 transistor 9, the N-type transistor remains in the cut-off state.

As a result, the output signal S. 0 will rise when the output of the first output circuit 3 and the output of the second output circuit 10 are summed, and here the sum of the driving forces of both output circuits 3 and 10 is as shown in FIG. Since the driving force is set equal to the driving force of the conventional output circuit, the rise of the output waveform 11 after time t1 is equal to the rise of the conventional output waveform 15 shown in FIG.

In this way, the output signal @S 0LIT exceeds the output determination level VH at time t2, and then settles down to a constant level while attenuating, and the desired output level is obtained.

The output waveform 12 is obtained in the same manner as above when the first J3 and the second input signals S and S2 are respectively L II and H''.

As mentioned above, from time t to time t1, the output is preliminary changed only by the first output circuit 3, which has a small driving force, and after time t1, the output is changed preliminarily by the first output circuit 3, which has a small driving force. By the cooperative work of .10, the output is changed to the desired voltage level with the original driving force. In other words, since the first output circuit 3 first starts a preliminary output change, the output changes gradually until it reaches a predetermined voltage level, and ringing is suppressed.

In the above embodiment, the N-type transistor is 2°8.9
Although the output circuits 3 and 10 configured by the above have been described, the output circuits 3 and 10 may be configured by P-type transistors or 0MO8 type transistors.

Further, in the above embodiment, the driving force of the first output circuit 3 is the same as that of the second output circuit 3.
Although the case has been described in which the driving force is smaller than the driving force of the output circuit 1o, the magnitude relationship of the driving forces of the first and second output circuits 3 and 10 may be reversed, or they may be equal.

〔Effect of the invention〕

As described above, according to the present invention, the output is preliminarily changed only by the first output circuit from the time when the input signal is applied until the time determined by the delay circuit, and after that,
Since the output is configured to change to a predetermined voltage level with the original driving force through cooperation between the first and second output circuits, the output changes gradually until the predetermined voltage level is reached. As a result, ringing is suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention, FIG. 2 is an output waveform diagram of the circuit shown in FIG. 1, FIG. 3 is a circuit diagram of a conventional semiconductor device, and FIG. 4 is a circuit diagram of a conventional semiconductor device. 4 is an output waveform diagram of the circuit shown in FIG. 3. FIG. In the same figure, 1, 2, 8.9 are N-type transistors, 3
is the first output circuit, 4 to 7 are inverters, 10 is the second output circuit, Dl is the first delay circuit, D is the second delay circuit, N and N are nodes, and Sl is the first input signal , S2 is the second input signal, and 5o11□ is the output signal. J3, and the numbers -N in each figure indicate the same or equivalent parts.

Claims (5)

[Claims] (1) A first output circuit including a first transistor whose one electrode is connected to a reference potential and whose conduction is controlled by an input signal; a delay circuit that delays the input signal; and the first transistor. a second output circuit including a second transistor having the same polarity and one electrode connected to a reference potential and whose conduction is controlled by the output signal of the delay circuit, the other electrode of the first transistor and A semiconductor device characterized in that an output is taken out from a connection point with the other electrode of the second transistor. (2) The semiconductor device according to claim 1, wherein the first and second transistors have N-type polarity. (3) The semiconductor device according to claim 1, wherein the first and second transistors have a P-type polarity. (4) The semiconductor according to any one of claims 1 to 3, wherein the driving ability of the second transistor is set larger than the driving ability of the first transistor. Device. (5) Claim 1, wherein the delay circuit is configured by connecting two inverters in series.
5. The semiconductor device according to any one of items 1 to 4.