JPH0191533A - A/d converter - Google Patents

A/d converter

Info

Publication number
JPH0191533A
JPH0191533A JP24944887A JP24944887A JPH0191533A JP H0191533 A JPH0191533 A JP H0191533A JP 24944887 A JP24944887 A JP 24944887A JP 24944887 A JP24944887 A JP 24944887A JP H0191533 A JPH0191533 A JP H0191533A
Authority
JP
Japan
Prior art keywords
signal
output
white noise
converter
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24944887A
Other languages
Japanese (ja)
Other versions
JPH082021B2 (en
Inventor
Akira Yugawa
湯川 彰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62249448A priority Critical patent/JPH082021B2/en
Priority to EP88115804A priority patent/EP0308982B1/en
Priority to DE3854414T priority patent/DE3854414T2/en
Priority to US07/249,158 priority patent/US5010347A/en
Publication of JPH0191533A publication Critical patent/JPH0191533A/en
Publication of JPH082021B2 publication Critical patent/JPH082021B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To prevent deterioration of S/N by providing a means generating a 1-bit white noise and a means superimposing an input with a difference at two sampling point of times with consecutive one-bit white noise. CONSTITUTION:A delta modulation circuit A is added with a 1-bit white noise generating means 8, a D flip-flop 10 retarding the output 9 by one sampling time, an inverter 11, and an adder 12. Then the output of the white noise generating means 8 and the output of the inverter 11 are added to form a difference between two consecutive sampling points of time at the output of the white noise generating means 8 is formed as a signal 13 and it is superimposed on the signal from the input terminal 1. Thus, excellent S/N characteristic and output amplitude characteristic even at a small signal are obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、信号帯域に比べてかなり速いサンプリングレ
ートで低ビット数のデジタル信号を符号化するA/D変
換器に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D converter that encodes a digital signal with a low number of bits at a sampling rate that is considerably faster than the signal band.

〔従来の技術〕[Conventional technology]

従来、低周波のアナログ信号をデジタル信号に変換する
とき、被変換アナログ信号の最大周波数の2倍から3倍
程度のサンプリング周波数で、分解能の高いA/D変換
を行うのが通常であった。
Conventionally, when converting a low-frequency analog signal into a digital signal, it has been usual to perform high-resolution A/D conversion at a sampling frequency that is approximately two to three times the maximum frequency of the analog signal to be converted.

このときサンプリング周波数の1/2以上の周波数を有
する信号成分は雑音としてデジタル信号に混入するため
、変換に際してあらかじめ高精度の帯域制限フィルタを
通してサンプリング周波数の1/2以上の信号を十分減
衰させてからA/D変換が行われてきた。しかしこの帯
域制限フィルタを集積回路上に精度良く作ることは非常
に困難である。そこで近年簡単なA/D変換器で信号周
波数より十分高いサンプリング周波数でA/D変換した
のちデジタルフィルタにより信号帯域内の信号だけを抽
出する方法が試みられている。デジタルフィルタは、ク
ロック周波数が安定であれば精度も良く、再現性も非常
によい。このためのA/D変換方式としてデルタ変調方
式が知られている。
At this time, signal components with a frequency of 1/2 or more of the sampling frequency are mixed into the digital signal as noise, so before conversion, the signal with a frequency of 1/2 or more of the sampling frequency is sufficiently attenuated through a high-precision band-limiting filter. A/D conversion has been performed. However, it is extremely difficult to fabricate this band-limiting filter on an integrated circuit with high precision. Therefore, in recent years, attempts have been made to use a simple A/D converter to perform A/D conversion at a sampling frequency sufficiently higher than the signal frequency, and then use a digital filter to extract only the signal within the signal band. Digital filters have good accuracy and very good reproducibility if the clock frequency is stable. A delta modulation method is known as an A/D conversion method for this purpose.

デルタ変調器は、第1図に示すブロック図において破線
で囲まれたAの部分で示されるように。
The delta modulator is indicated by the dashed line A in the block diagram shown in FIG.

予測器4、端子1からの入力信号と前記予測器からの出
力信号の差をとる手段5、前記差をとる手段5の出力の
正負を判定する比較器6とを連結して構成される。予測
器には通常、積分器が用いられる。この積分器をデジタ
ル回路で構成してもよく、この場合にはデジタル積分器
と前記差をとる手段の間にはD/A変換器が必要である
。かかるA/D変換器でサンプリング周波数が高いため
、従来の方式に比べて分解能が粗くても最終的に得る信
号帯域で評価した時高いS 、/ N比を実現すること
が出来る。しかし、入力信号が小さいときには分解能が
粗いことに起因するS/Nおよび入出力振幅特性が劣化
する欠点を有することが知られている。そこで、従来は
入力に一定の直流バイアスを加えるか、もしくはサンプ
リングレー1〜に対して1/2P(Pは整数)になり且
つ信号帯域より高い周波数の正弦波もしくは方形波を印
加することによりこの劣化を防止できることが知られて
いた。
It is constructed by connecting a predictor 4, means 5 for taking the difference between the input signal from the terminal 1 and the output signal from the predictor, and a comparator 6 for determining whether the output of the difference taking means 5 is positive or negative. An integrator is usually used as a predictor. This integrator may be constituted by a digital circuit, in which case a D/A converter is required between the digital integrator and the means for taking the difference. Since such an A/D converter has a high sampling frequency, it is possible to achieve a high S/N ratio when evaluated in the finally obtained signal band even if the resolution is coarser than in conventional systems. However, it is known that when the input signal is small, the S/N and input/output amplitude characteristics deteriorate due to coarse resolution. Conventionally, this has been achieved by applying a constant DC bias to the input, or by applying a sine wave or square wave with a frequency of 1/2P (P is an integer) and higher than the signal band relative to the sampling rate 1. It is known that deterioration can be prevented.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の技術によるA/D変換器の問題点は、上
述のような信号を加える方法によれば、この加えた信号
の振幅及び周波数により決まるある入力信号振幅で信号
対雑音比に著しい劣化を生じてしまいA/D変換器とし
て要求される性能を満足しなくなってしまうという点に
有る。
The problem with the conventional A/D converter described above is that, according to the method of adding a signal as described above, the signal-to-noise ratio deteriorates significantly at a certain input signal amplitude determined by the amplitude and frequency of the added signal. The problem is that the performance required for an A/D converter cannot be satisfied.

従って、本発明の目的は、従来知られていたかかる劣化
をなくし、小信号でも良好なS/N特性および入出力振
幅特性を有するデルタ変調器を再現性良く集積回路上に
実現する手段を提供することにある。
Therefore, an object of the present invention is to provide a means for eliminating such conventionally known deterioration and realizing a delta modulator having good S/N characteristics and input/output amplitude characteristics even for small signals on an integrated circuit with high reproducibility. It's about doing.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、アナログ信号を入力する端子と、変換された
デジタル出力から前記入力信号を予測する手段と、前記
入力信号と前記予測する手段の出力を比較してデジタル
出力とする手段とを有するデルタ変調型のA/D変換器
であって、1ビットの白色雑音を発生する手段と、前記
1ビットの白色雑音の連続する2つのサンプリング時点
での値の差を入力に重畳する手段とを有して構成される
The present invention provides a delta signal having a terminal for inputting an analog signal, means for predicting the input signal from a converted digital output, and means for comparing the input signal and the output of the predicting means to obtain a digital output. A modulation type A/D converter, comprising means for generating 1-bit white noise and means for superimposing the difference between the values of the 1-bit white noise at two consecutive sampling points on the input. It is composed of

〔実施例〕〔Example〕

本発明の一実施例の構成と作動に対する説明を第1図を
用いて説明する。端子1から入力された信号は予測器4
の出力3の信号分だけ加減算器5において減算され、そ
の結果は比較器6により正負が判定される、即ち入力信
号と予測信号の大小が判定される。もし入力信号の方が
大きいときには出力信号を得る端子2にデジタルコード
“1″を出力して予測器の予測電圧を大きくする。ここ
でD型フリップフロップ7はサンプリング周期の1周期
出力を保持する回路である。以上説明した部分は、通常
よく知られたデルタ変調回路Aである。
The structure and operation of an embodiment of the present invention will be explained with reference to FIG. The signal input from terminal 1 is sent to predictor 4.
The adder/subtracter 5 subtracts the signal of the output 3 of the input signal 3, and the comparator 6 determines whether the result is positive or negative, that is, the magnitude of the input signal and the predicted signal is determined. If the input signal is larger, a digital code "1" is output to the terminal 2 from which the output signal is obtained to increase the predicted voltage of the predictor. Here, the D-type flip-flop 7 is a circuit that holds an output of one sampling period. The portion described above is the generally well-known delta modulation circuit A.

この回路に1ビットの白色雑音発生手段8と、この出力
9を1サンプリングタイム遅らせるD型フリップフロッ
プ10と、インバータ11と、加算器12とを付加し、
白色雑音発生手段8の出力とインバータ11の出力との
和を取ることにより白色雑音発生手段8の出力の連続す
る2つのサンプリング時点での差を信号13に作り、こ
れを入力の端子1からの信号に重畳する。信号13での
データは0,1.2の3種の値を取り得るが、これを入
力信号に重畳する場合にはOは−1に、1は0に、2は
1に対応する。出力13を重畳する時、出力コード1に
対して予測器4の最小分解能の1/2から178の大き
さで信号に加えるのがもっとも望ましい。
A 1-bit white noise generating means 8, a D-type flip-flop 10 that delays the output 9 by 1 sampling time, an inverter 11, and an adder 12 are added to this circuit,
By taking the sum of the output of the white noise generation means 8 and the output of the inverter 11, the difference between the outputs of the white noise generation means 8 at two consecutive sampling points is created as a signal 13, and this is added to the signal 13 from the input terminal 1. Superimpose it on the signal. The data in the signal 13 can take three values, 0 and 1.2, but when superimposed on the input signal, O corresponds to -1, 1 corresponds to 0, and 2 corresponds to 1. When superimposing the output 13, it is most desirable to add it to the signal with a magnitude of 1/2 to 178 of the minimum resolution of the predictor 4 for the output code 1.

白色雑音を発生する回路は種々あるが、その−例として
第2図にモデムに良く用いられるいわゆるスクランブラ
と呼ばれる回路を示す。この回路は、7段のシフトレジ
スタ100の6段目の出力と7段目の出力との排他的論
理和にさらに比較器6の出力(すなわち端子2の出力)
との排他的論理和をとってシフトレジスタ100の入力
側に戻すと共にこれを白色雑音源(すなわち信号9)と
することで実現できる。
There are various types of circuits that generate white noise. As an example, FIG. 2 shows a circuit called a scrambler, which is often used in modems. This circuit adds the exclusive OR of the output of the 6th stage and the output of the 7th stage of the 7-stage shift register 100, and the output of the comparator 6 (i.e., the output of terminal 2).
This can be realized by taking the exclusive OR with the signal and returning it to the input side of the shift register 100, and using this as a white noise source (ie, signal 9).

〔発明の効果〕〔Effect of the invention〕

本方式による雑音を印加することは、この雑音の電力ス
ペクトラムを評価することにより予測できる。いま印加
する雑音の振幅の実効電力をD2、サンプリング周期を
T、信号の角周波数をωとすると信号13の電力スペク
トラムはD2s i n2(ωT/2)で表され低い周
波数成分が非常に小さくて信号帯域外のスペクトラムが
大きい性質を持っている。発明者は、このA/D変換器
の出力をデジタルフィルタを通して信号帯域成分だけを
得ることにしているから、この雑音成分を加えても信号
帯域外の雑音が1子化雑音に対して3dB程度増加する
だけで、信号帯域内に対するA/D変換器の性能は劣化
しない。一方この雑音成分を加えることにより入力信号
の小さいときも、良好なS/N特性を実現することが出
来る。
Application of noise according to this method can be predicted by evaluating the power spectrum of this noise. If the effective power of the amplitude of the noise to be applied now is D2, the sampling period is T, and the angular frequency of the signal is ω, then the power spectrum of signal 13 is expressed as D2s in2 (ωT/2), and the low frequency component is very small. It has a characteristic that the spectrum outside the signal band is large. The inventor decided to pass the output of this A/D converter through a digital filter to obtain only the signal band component, so even if this noise component is added, the noise outside the signal band will be about 3 dB compared to the single child noise. The performance of the A/D converter within the signal band does not deteriorate. On the other hand, by adding this noise component, good S/N characteristics can be achieved even when the input signal is small.

さらに、従来の方法で問題であったS/N特性のへこみ
も生じない利点を持っている。従って、本発明は様々な
規格を満たすA/D変換器が実現できるという効果があ
る。
Furthermore, it has the advantage that no depression occurs in the S/N characteristic, which is a problem with conventional methods. Therefore, the present invention has the advantage that it is possible to realize an A/D converter that satisfies various standards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の構成を示すブロック図、第
2図は本発明の白色雑音を発生する手段の一例の構成を
示すブロック図。 4・・・予測器、6・・・比較器、8・・・白色雑音発
生手段、100・・・シフトレジスタ、A・・・デルタ
変調回路。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of an example of means for generating white noise of the present invention. 4...Predictor, 6...Comparator, 8...White noise generation means, 100...Shift register, A...Delta modulation circuit.

Claims (1)

【特許請求の範囲】[Claims] アナログ信号を入力する端子と、変換されたデジタル出
力から前記入力信号を予測する手段と、前記入力信号と
前記予測する手段の出力を比較してデジタル出力とする
手段とを有するデルタ変調型のA/D変換器であって、
1ビットの白色雑音を発生する手段と、前記1ビットの
白色雑音の連続する2つのサンプリング時点での値の差
を入力に重畳する手段とを有することを特徴とするA/
D変換器。
A delta modulation type A having a terminal for inputting an analog signal, means for predicting the input signal from a converted digital output, and means for comparing the input signal and the output of the predicting means to obtain a digital output. /D converter,
A/
D converter.
JP62249448A 1987-09-25 1987-10-01 A / D converter Expired - Lifetime JPH082021B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62249448A JPH082021B2 (en) 1987-10-01 1987-10-01 A / D converter
EP88115804A EP0308982B1 (en) 1987-09-25 1988-09-26 Analog-to-digital converter having an excellent signal-to-noise ratio for small signals
DE3854414T DE3854414T2 (en) 1987-09-25 1988-09-26 AD converter with excellent signal-to-noise ratio for small signals.
US07/249,158 US5010347A (en) 1987-09-25 1988-09-26 Analog-to-digital converter having an excellent signal-to-noise ratio for small signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62249448A JPH082021B2 (en) 1987-10-01 1987-10-01 A / D converter

Publications (2)

Publication Number Publication Date
JPH0191533A true JPH0191533A (en) 1989-04-11
JPH082021B2 JPH082021B2 (en) 1996-01-10

Family

ID=17193118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62249448A Expired - Lifetime JPH082021B2 (en) 1987-09-25 1987-10-01 A / D converter

Country Status (1)

Country Link
JP (1) JPH082021B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132825A (en) * 1992-10-16 1994-05-13 Nippon Precision Circuits Kk Signal generating circuit
US8549311B2 (en) 2008-03-05 2013-10-01 Panasonic Corporation Electronic device, password deletion method, and program

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023512A (en) * 1973-06-29 1975-03-13

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5023512A (en) * 1973-06-29 1975-03-13

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06132825A (en) * 1992-10-16 1994-05-13 Nippon Precision Circuits Kk Signal generating circuit
US8549311B2 (en) 2008-03-05 2013-10-01 Panasonic Corporation Electronic device, password deletion method, and program

Also Published As

Publication number Publication date
JPH082021B2 (en) 1996-01-10

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