JPH0184193U - - Google Patents

Info

Publication number
JPH0184193U
JPH0184193U JP1987178312U JP17831287U JPH0184193U JP H0184193 U JPH0184193 U JP H0184193U JP 1987178312 U JP1987178312 U JP 1987178312U JP 17831287 U JP17831287 U JP 17831287U JP H0184193 U JPH0184193 U JP H0184193U
Authority
JP
Japan
Prior art keywords
positive
terminal
output
circuit
negative
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987178312U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987178312U priority Critical patent/JPH0184193U/ja
Publication of JPH0184193U publication Critical patent/JPH0184193U/ja
Pending legal-status Critical Current

Links

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  • Emergency Alarm Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツクダイヤグ
ラム、第2図は本考案の別実施例を示すブロツク
ダイアグラムである。 1……アラーム入力回路A、2……アラーム入
力回路B、3……インバーター、4……アラーム
回路、5……アラーム入力回路C、6……正負切
替スイツチ。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing another embodiment of the present invention. 1...Alarm input circuit A, 2...Alarm input circuit B, 3...Inverter, 4...Alarm circuit, 5...Alarm input circuit C, 6...Positive/negative changeover switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 主に監視を目的に製作されるVTRやビデオモ
ニターに設けられており、センサー出力を接続す
る端子と、その出力を処理する回路とから成るア
ラーム回路において、正負どちらの論理で出力さ
れても受け付けられるように、正論理用端子と負
論理用端子を同時に設けるかスイツチにより正負
切換えを行なうようにしたことを特徴とするアラ
ーム入力回路。
The alarm circuit, which is installed in VTRs and video monitors manufactured mainly for monitoring purposes and consists of a terminal for connecting the sensor output and a circuit for processing the output, accepts output with either positive or negative logic. 1. An alarm input circuit characterized in that a positive logic terminal and a negative logic terminal are provided at the same time, or the positive and negative terminals are switched by a switch.
JP1987178312U 1987-11-25 1987-11-25 Pending JPH0184193U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987178312U JPH0184193U (en) 1987-11-25 1987-11-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987178312U JPH0184193U (en) 1987-11-25 1987-11-25

Publications (1)

Publication Number Publication Date
JPH0184193U true JPH0184193U (en) 1989-06-05

Family

ID=31469935

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987178312U Pending JPH0184193U (en) 1987-11-25 1987-11-25

Country Status (1)

Country Link
JP (1) JPH0184193U (en)

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