JPH01811A - pseudorandom binary sequence generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pseudorandom binary sequence generator.

Pseudo-random binary sequence generators are known,
Its structure and operation are described in the book by Baker and Piper “
Cryptographic System” London, 1982.

Published by Northwood Book Company.

In particular, this type of generator takes the form of a linear feedback shift register, particularly a linear feedback shift register of the "Galois'" type or a "Dual" type.
There is a type.

Such a pseudorandom binary sequence generator primarily comprises nli recirculating shift registers and one or more associated logic gates in a loop coupling the outputs of at least two shift register stages. By a suitable choice of logic gates, it is possible to obtain a repeating sequence of length 2"-1 bits. If n is a number of suitably large size, this sequence can be very long in practice, and The above bits can be considered random and therefore "pseudorandom".

It is necessary to reduce the possibility that the outputs of pseudo-random binary sequence generators are imitated, and even if the output signals of these generators and the contents of several shift register stages are known, the contents of these shift register stages must be There are many applications where it is necessary to increase the unpredictability of both.

The gist of the invention will be apparent from the claims below.

The invention will be explained in detail with reference to the drawings.

The pseudorandom binary sequence generator of the invention shown in FIG. 1 comprises two linear feedback shift registers S and T. The shift register S has 29 shift register stages S. ---S2a is provided, and the shift register T has 31 shift register stages T, ---T, .
will be established. Each shift register provides the output of the last shift register stage as an input to the first shift register role of the recirculation loop during normal operation. This loop is also provided with a plurality of logic gates G in the form of an exclusive-OR circuit, which combine the output of the last shift register stage with the output of the associated shift register stage to feed the next shift register stage. .

The location of the logic gate G is chosen accordingly so that the length of the sequence generated by the register is the maximum possible length. The position of a conventional logic gate can be expressed in polynomial form as expressed by the following equation.

f(X)=1+C,X+C2X2+---C,X'+-
-C, , X"-'+X" By using the above equation, the pseudo-random binary sequence generator S can be expressed as the following equation.

1+X2+X3+X4+XS+X7+X11 +30
I Sol 5LIT 5131314 and will be located on the input side to S20. There are therefore nine logic gates, and each gate introduces an additional term into the polynomial.

Similarly, the logic gate G of the pseudo-random binary sequence generator T also has shift register stages T,, T2゜T3+.
TS+ T6+ L+ T9+ TIO+ TIl+
T+5+ TI9+ People to T23 and T27 will be located on the blade side.

There are 13 logic gates in this case.

Further, the circuit shown in FIG. 1 is provided with a multiplexer Z, that is, a selection circuit. This selection circuit is provided with 5 address input terminals A and 32 data input terminals B+.
This selection circuit selects one of the data input terminals to be supplied to the output according to the address word supplied to the address input terminal. - Generally, when there are p data input terminals, there are q address input terminals, where q is the lowest value satisfying 2q≧p.

The data input terminal is supplied with the output of the shift register stage of the shift register T, so that T1 is connected to B1 (
i=0.1. ---30) And T30 is also connected to B31.

The address input terminals are supplied with the outputs of the first five shift register stages of shift register S, so 81 is A
r (i=0.L 2.3.4), so that q outputs are available from the register S.

In operation, the two shift registers S and T are clocked simultaneously. The 31 bits of the pseudo-random binary sequence held in the shift register T are applied to the data input terminal of the selection circuit M. One of these bits is selected as an output at any instant. This selected bit is determined by the contents of the first five shift register stages of the system register S. Therefore, even if the contents of the shift register T are known, it is difficult to predict the number of outputs.

The total number of shift register stages included in the shift register is q
- more than the number of shift register stages required to obtain only the bit address and p data bits, 60
shall be. When the total number of shift register stages is r, the following equation holds true.

r>p+q Words that require a large number of "unused" shift register stages to be provided if the outputs of these shift register stages are not supplied to the selection circuit M, and that this number must be large compared to the number of address bits. it is obvious. Therefore, the following equation holds.

r≧p +q2 Providing these unused shift register stages increases the unpredictability of the address word and therefore makes the output of the pseudo-random binary sequence generator unpredictable even if the contents of the shift register T are known. be able to.

It is also obvious that the number of logic gates G used in the system register is large, 22 in this example.

As mentioned above, these logic gates are selected in such a way that a sequence of maximum length is obtained in each case. but,
It is not necessarily necessary to use a large number of gates for this purpose only.

However, the greater the number of logic gates, the more difficult it becomes to predict the contents of the shift register. The reason is that the predetermined sequence is not easily phased from the beginning to the end of the shift register and can change at many points.

If the minimum number of logic gates this accumulates is S, then
The following equation is obtained, which allows for a higher degree of unpredictability for the total number of shift register stages.

25 ≧ r2 When the total number of shift register stages is 60, the minimum is 1
Two logic gates need to be provided, the minimum number for each shift register being preferably approximately proportional to the number of shift register stages.

The value of S is usually smaller than r/2.

As is clear from the drawing, the switch St! 11.5lli
2. St! 13 and SW4 are provided so that, in normal operation (run), two circular loops can be formed around the shift registers S and T. However, these four switches can be switched from the position shown to the load position, in which the output of shift register S is supplied as the input of shift register T, and all of the logic The output side supplies a zero value to the input side which is normally sustained. A 60-bit initialization word can then be applied to the load input terminal of clocked switch SWI through all 60 shift register stages.

This reinitialization operation is properly performed during normal operation of the binary sequence generator upon receipt of a defined cue, and is performed as described below with respect to FIG. This also makes it impossible to predict the output even if the contents of the shift register are known at any given moment.

After receiving the initialization word, the binary sequence generator must be clocked for several cycles before its output can be utilized.

FIG. 2 shows a modification of the pseudo-random binary sequence generator of FIG. Since most of the apparatus of this example is the same as the apparatus shown in FIG. 1, only the differences will be described.

In this example as well, the shift register S is provided with 29 shift register stages, and the shift register T is provided with 31 shift register stages. A logic gate is also coupled to the input side of the shift register stage shown below.

Shift register S - shift register 11S2. S3.
Sl.

Sa + S l l r Sl 6 and S20 shift register T - shift register stage T+, T2. T3
゜T'71 Ti4+ TI9 and T2゜Therefore, in this example, a total of 60 shift register stages, 32 data input terminals and 5 address input terminals of the selection circuit M, and 14 logic gates are provided. .

However, in this case several of the shift register stages of each shift register are respectively connected to several of each of the data and address input terminals. That is, this connection is shown below.

A, -3° At Sl A2-T.

A3-T.

4-T2 Bo-By-32~Ss (each compatible) B8~T31-
By mixing the output of the shift register and the input of the selection circuit M in this manner (corresponding to each other), it is possible to predict the operation of the binary sequence generator even though most of its states are known. is extremely difficult.

FIG. 3 shows yet another example of the pseudorandom binary sequence generator of the present invention. In this example, 61 shift register stages S are used instead of the two shift registers in FIGS.
. A single shift register S with -5aO is provided.

Furthermore, 25 logic games) G are connected to the input terminals of the shift register stage shown below as shown.

Shift register stage "21 S31 Sl, Sa, s,
, 5lotS1□+ S+s+S+s+ s,. ,
S2□+ S24+ S2S+ S2Sl s3°.

S33・S34・S37・S40・S43・S44・S
4S・S54・SSS and S60 Because of this, 5
The 32 address bits A0--A are taken from the outputs of the shift register stages S4+Sls and S24, and the 32 data bits are taken from the outputs of the shift register stages S2. ~ Take out from the output side of Sho. A single recirculating loop thus provides outputs to both the data and address inputs of multiplexer M.

In this case, only two switches SWI and SW2 are required for reinitialization with a 61-bit initialization word.

The pseudo-random binary sequence generator shown in FIG. 3 also allows a single recirculating loop to be used to supply address and data input bits to multiplexer M.

According to the prior art, such generators have been described and explained in terms of separate circuits. However, the description and claims are not intended to be useful for carrying out the invention in the form of a computer program that reproduces the polynomials of the generator mathematically or by logical steps to generate a composite sequence similar to the generator described above. It is clear that it can be applied in many ways.

The output of the pseudorandom binary sequence generator can be used to scramble the signal components of a conditional access (or subscription) television signal, such as a direct satellite broadcast signal. The reinitialization operation described above preferably transmits a new code every 10 seconds to scramble the video signal, but this code repeats many times during the 10 second period. The reason is that the maximum time to lock the decoder needs to be significantly less than 1 second. However, this means that the image information is scrambled by repeating the same sequence. This is relatively dangerous. The reason is that correlations between different parts of the scrambled image can be performed.

To count television frames, an 8-bit frame count word (FCNT) is transmitted directly with the television signal, such as a satellite broadcast signal.

This counting is advanced every 4 Qns (every frame) and is repeated after a predetermined number of frames, for example every 256 frames (approximately 10 seconds).

This frame count word (FCNT) may then be provided as input to a pseudo-random binary sequence generator at the transmitter and to an associated generator at the receiver's decoder. To this end, both a frame count signal and a secret control signal are provided to the transmitter's pseudo-random binary sequence generator at the beginning of each television frame. The effect of the use of the frame count signal on the binary sequence generator is to produce different outputs during each loading of the same control word value.

This means always scrambling the image signal with a different key stream, which is -layer secure.

Furthermore, each sequence is a television frame (40nS)
The decoder can quickly access the video information because the video information is generated every time. Frame count words can be combined with control words as appropriate. In this case a simple modulo-2 addition can be performed.

The operation described above will be explained below with reference to FIG.

A frame counter 10 produces an output in the form of so-called 8-bit words that increases from frame to frame. Each time the frame counter performs a step operation, it supplies its output 10a to a frequency dividing circuit 11, which divides the frequency by a number equal to the required length of the repetition period, in this example 256, and divides the frequency into 10 seconds. Try to get the repetition period. The output of the divider circuit clocks the control word generator 12 to generate control words of different lengths, such as 60-bit control words.

The 8-bit output of the frame counter is applied to a divide-by-2/2 inverter circuit 14 where each 8-bit frame count word is alternately complemented.

The output of inverter circuit 12 is then applied to a modulo-2 adder, represented by exclusive OR gate 15, which adds each frame count word modulo-2 to a byte consisting of a 60-bit control word. Therefore, the first 8-bit byte of the control word is added modulo-2 to the first frame count word, the second byte is added to the complement of the second frame count word, and the third byte is added to the third frame count word. and repeat this until the last byte. This last byte is only 4 bits for a 60-bit control word and is added to the least significant four bits of the complement of the eighth frame count word. The output of the exclusive OR gate 15 is provided as an initialization input to a pseudo-random binary sequence generator 16 and is loaded into the generator every frame count, ie every time the frame counter 10 advances.

The generator 16 may be any of the generators described above, but is preferably the generator shown in FIG.

Therefore, at the input side of the pseudo-random binary sequence generator there are two types of signals, namely one signal (frame count) -
is known and the other signal (control load) is unknown. In such a state, the unknown input cannot be detected by both the known input and the output of the generator. This allows the same control word to be loaded repeatedly into the pseudo-random binary sequence generator, but prevents its output from being repeated in the same sequence, thereby increasing security.

The processing described above can be performed word by word or concatenated.

Frame counting is a suitable periodic sequence for this purpose, but not an absolute sequence. For example, suitable counts can be derived b) from an associated data signal, such as a date/time signal, or from other counts, such as line counts, or from a combination of these counts.

[Brief explanation of drawings]

1, 2, and 3 are block circuit diagrams showing the configuration of each pseudo-random binary sequence generator that is an embodiment of the present invention, and FIG. 4 is a pseudo-random binary sequence generator shown in FIG. 1.2 or 3. FIG. 2 is a block diagram illustrating a circuit for changing inputs to the . M...Selection means B. -831...Data input terminal Ao=Aa...Address input terminal G...Logic gates S, T...Recirculating shift register means 10...Frame counter 10a...Output 11... Frequency divider circuit
12... Control word generator 14... A frequency division and inversion circuit 15... Exclusive OR gate 16... Pseudo-random binary sequence generator Flo, 4

Claims (1)

[Claims] 1. The device has p data input terminals and q address input terminals (2q≧p) and selects one of the data input bits at any instant according to an address input word to output the output of the device. and recirculating shift register means comprising a recirculating loop having a plurality of logic gates and logically combining the outputs of selected shift register stages of the loop to generate a pseudo-random sequence. a pseudo-random binary sequence generator comprising: connecting several output terminals of the shift register stage of said loop to a data input terminal of said selection means; and connecting other output terminals of the shift register stage of the same loop to a data input terminal of said selection means; A pseudo-random binary sequence generator comprising means for connecting to an address input terminal. 2. The recirculating shift register means comprises two recirculating loops, each loop being connected to each of the data input terminals of said selection means and to each of the address input terminals of said selection means. A pseudo-random binary sequence generator according to claim 1, characterized in: 3. Means for properly loading the reinitialization word into the shift register means.
The pseudo-random binary sequence generator according to item 1 or 2. 4. The loading means comprises means for generating a periodic count word, means for generating a control word, and means for combining the count and control words to properly load the reinitialization word into the shift register means. 4. The pseudo-random binary sequence generator according to claim 3, wherein the reinitialization word is changed each time the initialization is performed. 5. A pseudorandom binary sequence generator as claimed in claim 4, characterized in that the combining means comprises circuitry for complementing the alternating count words. 6. Pseudo-random binary sequence generator according to claim 4 or 5, characterized in that the combining means comprises modulo-2 addition means for adding each count word to selected bits of the control word. . 7. Pseudo-random binary sequence generation according to claim 4, 5 or 6, characterized in that means are provided which are connected to the output side of the generator and process at least one component of the television signal. vessel. 8. A pseudo-random binary sequence generator according to claim 7, characterized in that the periodic count word is a frame count word formed by counting successive video frames in sequence. 9. further comprising means operative after loading of the reinitialization word to clock the shift register means for a plurality of clock periods before utilization of the output of the generator. Pseudo-random binary sequence generator as described in any of the paragraphs. 10. Recirculating shift register means 2 in normal operating condition
Claims 3 to 9 characterized in that the shift register means of the two loops are arranged in two recirculating loops and that the loading means in operation connects the shift register means of the two loops to a single shift register. Pseudo-random binary sequence generator as described in that section.