JPH0170346U - - Google Patents
Info
- Publication number
- JPH0170346U JPH0170346U JP1987165533U JP16553387U JPH0170346U JP H0170346 U JPH0170346 U JP H0170346U JP 1987165533 U JP1987165533 U JP 1987165533U JP 16553387 U JP16553387 U JP 16553387U JP H0170346 U JPH0170346 U JP H0170346U
- Authority
- JP
- Japan
- Prior art keywords
- package
- integrated circuit
- connection terminals
- back surface
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165533U JPH0170346U (enFirst) | 1987-10-28 | 1987-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987165533U JPH0170346U (enFirst) | 1987-10-28 | 1987-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0170346U true JPH0170346U (enFirst) | 1989-05-10 |
Family
ID=31452104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987165533U Pending JPH0170346U (enFirst) | 1987-10-28 | 1987-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0170346U (enFirst) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230346B2 (enFirst) * | 1979-10-19 | 1987-07-01 | Aisin Seiki |
-
1987
- 1987-10-28 JP JP1987165533U patent/JPH0170346U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6230346B2 (enFirst) * | 1979-10-19 | 1987-07-01 | Aisin Seiki |