JPH0159832B2 - - Google Patents

Info

Publication number
JPH0159832B2
JPH0159832B2 JP57183325A JP18332582A JPH0159832B2 JP H0159832 B2 JPH0159832 B2 JP H0159832B2 JP 57183325 A JP57183325 A JP 57183325A JP 18332582 A JP18332582 A JP 18332582A JP H0159832 B2 JPH0159832 B2 JP H0159832B2
Authority
JP
Japan
Prior art keywords
voltage
secondary winding
capacitor
diode
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57183325A
Other languages
Japanese (ja)
Other versions
JPS5972982A (en
Inventor
Motoji Tawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP18332582A priority Critical patent/JPS5972982A/en
Publication of JPS5972982A publication Critical patent/JPS5972982A/en
Publication of JPH0159832B2 publication Critical patent/JPH0159832B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/06Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes without control electrode or semiconductor devices without control electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)

Description

【発明の詳細な説明】 本発明はテレビジヨン受像機に於いて使用する
高圧発生回路に関し、特にフライバツクトランス
の2次巻線の両端間に発生するパルス電圧の交流
的な最大振幅を減少させることを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high voltage generating circuit used in a television receiver, and in particular to a high voltage generating circuit for reducing the AC maximum amplitude of a pulse voltage generated across a secondary winding of a flyback transformer. The purpose is to

テレビジヨン受像機に於いて、受像管アノード
用の高電圧を作成する所謂高圧発生回路は一般に
多倍圧整流回路を使用したものが賞用されてお
り、これは例えば第1図の如く構成されている。
即ち、同図のものは2倍圧整流回路を使用した場
合であり、1は水平出力トランジスタ、2はダン
パダイオード、3は共振コンデンサ、4はフライ
バツクトランス、5,6,7はコンデンサ8,9
と共に2倍圧整流回路を構成するダイオード、1
0は受像管のアノード容量で代用される出力コン
デンサ、11は受像管フオーカス電圧取り出し用
の可変抵抗器である。
In television receivers, the so-called high-voltage generation circuit that generates the high voltage for the picture tube anode generally uses a multi-voltage rectifier circuit, which is configured as shown in Figure 1, for example. ing.
That is, the figure shows the case where a double voltage rectifier circuit is used, 1 is a horizontal output transistor, 2 is a damper diode, 3 is a resonant capacitor, 4 is a flyback transformer, 5, 6, 7 are capacitors 8, 9
A diode, 1, which together constitutes a double voltage rectifier circuit.
0 is an output capacitor substituted by the anode capacitance of the picture tube, and 11 is a variable resistor for taking out the picture tube focus voltage.

斯る従来の高圧発生回路は既に周知であるか
ら、その動作の詳細な説明は省略するが、基本的
には次のように動作するようになつている。即
ち、上記フライバツクトランス4の2次巻線4d
の両端間に第2図のパルス電圧(ただし、低電位
側の巻き初め端Sを基準とする)が発生するもの
とすると、コンデンサ8は帰線期間Trに第2図
中のV1の大きさの電圧まで図示の極性に充電さ
れ、またコンデンサ9には走査期間TsにV1+V2
の大きさの電圧まで充電されるから、結局、出力
コンデンサ10に充電(帰線期間)された電圧の
大きさV0はV0=2V1+V2となり、この直流電圧
V0が受像管のアノードに供給される訳である。
Since such a conventional high voltage generating circuit is already well known, a detailed explanation of its operation will be omitted, but basically it operates as follows. That is, the secondary winding 4d of the flyback transformer 4
Assuming that the pulse voltage shown in Fig. 2 is generated between both ends of Tr (with reference to the winding start end S on the low potential side), the capacitor 8 is The capacitor 9 is charged with the polarity shown in the figure to a voltage of V 1 +V 2 during the scanning period Ts.
Since the output capacitor 10 is charged to a voltage with a magnitude of
This means that V 0 is supplied to the anode of the picture tube.

なお、12及び13はフライバツクトランス4
の3次巻線4cから取り出す負極性パルスの正側
(走査期間)部分を整流平滑するためのダイオー
ドとコンデンサであり、その整流平滑して得る+
18V程度の直流電圧は受像機内の各回路の電源と
して使用されるものである。
In addition, 12 and 13 are flyback transformers 4
A diode and a capacitor are used to rectify and smooth the positive side (scanning period) portion of the negative pulse taken out from the tertiary winding 4c, and the +
A DC voltage of approximately 18V is used as a power source for each circuit within the receiver.

ところで、この第1図の回路では、2次巻線4
bの高電位側の巻き端Fに発生する電圧(第2
図)は図中細線のレベルを交流零レベルとするも
のであり、その正側のピーク値はV1(20インチの
受像機では通常9KV程度)となる。そして、こ
のように2次巻線4bに発生するパルス電圧が交
流的に大きなピーク値を持つものであることは、
次のような欠点を意味する。即ち先ず第1に、2
次巻線4bに発生するピーク値の大きな交流電圧
に対して、この2次巻線4bと1次巻線4a及び
2次巻線4bと3次巻線4c間の絶縁耐圧が問題
になり、コロナ放電が発生しやすいことである。
次に第2に、フライバツクトランス内には一般に
エポキシ等の絶縁樹脂を充填しているが、この樹
脂に交流電流が流れ誘電体損が増加し、フライバ
ツクトランスの発熱量が増大し温度が上昇する。
更に第3は先の第1の点に関連して1次、2次間
の絶縁を良好にすると、その1次、2次間の結合
が浅くなつて洩れインダクタンスが増大するた
め、高圧安定のための高次高調波同調が困難にな
ることである。
By the way, in the circuit shown in Fig. 1, the secondary winding 4
The voltage generated at the winding end F on the high potential side of b (second
In Figure), the level of the thin line in the figure is the AC zero level, and the peak value on the positive side is V 1 (normally about 9KV for a 20-inch receiver). The fact that the pulse voltage generated in the secondary winding 4b has a large AC peak value means that
It means the following disadvantages: That is, first of all, 2
With respect to the AC voltage with a large peak value generated in the secondary winding 4b, the insulation voltage between the secondary winding 4b and the primary winding 4a and between the secondary winding 4b and the tertiary winding 4c becomes a problem. Corona discharge is likely to occur.
Secondly, flyback transformers are generally filled with insulating resin such as epoxy, but alternating current flows through this resin, increasing dielectric loss, increasing the amount of heat generated by the flyback transformer, and lowering the temperature. Rise.
Furthermore, the third point is related to the first point above, if the insulation between the primary and secondary is improved, the coupling between the primary and secondary becomes shallow and the leakage inductance increases, making it difficult to maintain high voltage stability. This makes high-order harmonic tuning difficult.

そこで、本発明に斯る諸欠点を解消すべくなさ
れたものであり、以下、その詳細を図面に示す実
施例に則して説明する。
Therefore, the present invention has been made to eliminate the various drawbacks of the present invention, and details thereof will be explained below with reference to embodiments shown in the drawings.

第3図は本発明による高圧発生回路の一実施例
を示しており、第1図の従来回路と対応する部分
には同一図番を付して説明を省略するが、この実
施例では次の点を特徴としている。即ち、先ず第
1に、フライバツクトランス4の2次巻線4bの
中点位置に中間タツプMを設け、このタツプにコ
ンデンサ14の一端を接続し、且つ、このコンデ
ンサの他端を図示の方向のダイオード15を介し
て上記2次巻線4bの巻き初め端Sに接続した点
である。次に第2に上記2次巻線4bの巻き終り
端Fと前記中間タツプMとの間に図示の方向のダ
イオード16とコンデンサ17及び可変抵抗器1
8を図示のように接続し、その可変抵抗器18の
摺動子からフオーカス電圧を得るようにした点で
ある。
FIG. 3 shows an embodiment of a high voltage generation circuit according to the present invention. Parts corresponding to those of the conventional circuit in FIG. 1 are given the same figure numbers and explanations are omitted. It is characterized by points. That is, first, an intermediate tap M is provided at the midpoint of the secondary winding 4b of the flyback transformer 4, one end of the capacitor 14 is connected to this tap, and the other end of the capacitor is connected in the direction shown in the figure. This point is connected to the winding start end S of the secondary winding 4b via the diode 15. Next, a diode 16, a capacitor 17, and a variable resistor 1 are connected between the winding end F of the secondary winding 4b and the intermediate tap M in the direction shown in the figure.
8 is connected as shown in the figure, and the focus voltage is obtained from the slider of the variable resistor 18.

さて、斯る第3図の回路に於いて、中間タツプ
Mが前述の如く中点位置に設けられているから、
2次巻線4bのSM間及びMF間に夫々発生する
電圧値は第2図の場合の1/2なる。従つて、
今、帰線期間Trに2次巻線4bの両端間に波高
値V1のパルス電圧が発生すると、SM間の1/
2V1のパルス電圧によつてコンデンサ14が図示
の系路で充電され、このコンデンサの両端間電圧
は1/2V1になる。そして、この両端間電圧は走
査期間Tsに亘つて保持されるから、結局M点は
接地点から見て1/2V1の直流電位にクランプさ
れることになる。
Now, in the circuit shown in FIG. 3, since the intermediate tap M is provided at the midpoint position as described above,
The voltage values generated between SM and MF of the secondary winding 4b are 1/2 of those in the case of FIG. 2. Therefore,
Now, when a pulse voltage with a peak value V 1 is generated between both ends of the secondary winding 4b during the retrace period Tr, 1/
A pulse voltage of 2V 1 charges capacitor 14 in the circuit shown, and the voltage across the capacitor becomes 1/2V 1 . Since this voltage between both ends is maintained over the scanning period Ts, the point M is eventually clamped to a DC potential of 1/2V 1 when viewed from the ground point.

一方、2倍圧整流用のコンデンサ8は上記帰線
期間TrではSF間のパルス電圧によつて充電さ
れ、その両端間電圧はV1となつている。従つて、
走査期間Tsでは2倍圧整流用の他方のコンデン
サ9がV1+V2まで充電され、且つ出力コンデン
サ10は帰線期間Trに2V1+V2まで充電される
ことになり、斯る点は第1図の従来回路と全く同
様である。
On the other hand, the capacitor 8 for double voltage rectification is charged by the pulse voltage across SF during the retrace period Tr, and the voltage across it is V1 . Therefore,
During the scanning period Ts, the other capacitor 9 for double voltage rectification is charged to V 1 +V 2 , and the output capacitor 10 is charged to 2V 1 +V 2 during the retrace period Tr. This circuit is exactly the same as the conventional circuit shown in FIG.

ここで、2次巻線4bに発生する電圧について
交流的に考えて見ると、第4図に示すようにF点
の電圧波形は、接地点に対して1/2V1であるM
点の電位を交流零レベルとし、ピーク値(正側)
を1/2V1とする実線のようになり、S点の電圧
波形は上記交流零レベルに対して、F点の波形と
対称な破線のようになる。従つて、2次巻線4b
に発生する交流電圧は、最大ピーク値(最大振
幅)が1/2V1となり、先の従来回路の場合の
1/2になることが判る。
Here, if we consider the voltage generated in the secondary winding 4b from an AC perspective, the voltage waveform at point F is 1/2V 1 with respect to the ground point, as shown in Figure 4.
The potential at the point is taken as the AC zero level, and the peak value (positive side)
The voltage waveform at point S becomes like a solid line with 1/2V 1 , and the voltage waveform at point S becomes like a broken line which is symmetrical to the waveform at point F with respect to the above-mentioned AC zero level. Therefore, the secondary winding 4b
It can be seen that the maximum peak value (maximum amplitude) of the AC voltage generated is 1/2V 1 , which is 1/2 that of the conventional circuit described above.

また、フオーカス電圧取り出し用の可変抵抗器
18の両端間には先のFM間のパルス電圧(第4
図の実線)をダイオード16とコンデンサ17で
整流平滑して得た電圧が印加されており、その分
圧後の電圧がコンデンサ14の両端間の直流電圧
に重畳されて取り出されるから、この場合は第1
図と同じ大きさのフオーカス電圧を取り出すのに
耐圧が1/2の可変抵抗器で済むことになり、上
記可変抵抗器18の小型化が可能となる。
In addition, the pulse voltage between the previous FM (fourth
The voltage obtained by rectifying and smoothing the solid line (solid line in the figure) with the diode 16 and capacitor 17 is applied, and the divided voltage is superimposed on the DC voltage across the capacitor 14 and taken out. 1st
In order to extract a focus voltage of the same magnitude as shown in the figure, a variable resistor with a withstand voltage of 1/2 is required, and the variable resistor 18 can be made smaller.

次に第5図は他の実施例を示しており、この実
施例では2次巻線4bのF点側を巻き上げて得た
E端に2倍圧整流用のコンデンサ9の一端を接続
し、これによつてダイオード5,6,7の耐圧関
係を変更するようにしたものであるが、その基本
的動作は第3図の回路と何等変わらない。また、
フオーカス電圧取り出し用のダイオード16のア
ノードを上記ダイオード5のカソード側に接続し
ているが、斯る点には特に特徴はない。更に、こ
の実施例とは逆にダイオード5のアノードをE端
に接続し、F点に上記コンデンサ9の一端側を接
続してもよい。従つて、このことからも判るよう
に、中間タツプMはSF間或いはSE間の必ずしも
中点位置に設ける必要はない。
Next, FIG. 5 shows another embodiment, in which one end of a capacitor 9 for double voltage rectification is connected to the E terminal obtained by winding the F point side of the secondary winding 4b. This changes the breakdown voltage relationship of the diodes 5, 6, and 7, but its basic operation is no different from the circuit shown in FIG. Also,
Although the anode of the diode 16 for extracting the focus voltage is connected to the cathode side of the diode 5, there is no particular feature in this point. Furthermore, contrary to this embodiment, the anode of the diode 5 may be connected to the E terminal, and one end of the capacitor 9 may be connected to the F point. Therefore, as can be seen from this, the intermediate tap M does not necessarily need to be provided at the midpoint between SF or SE.

以上の如く本発明の高圧発生回路に依れば、フ
ライバツクトランスに発生するパルス電圧の交流
的な最大振幅を減少させることができるので、フ
ライバツクトランス内でコロナ放電が起りにく
く、且つ、フライバツクトランス内の絶縁樹脂を
流れる交流分も減少するので、フライバツクトラ
ンスの温度上昇が抑えられる。また、上記の如く
コロナ放電が起りにくいから1次・2次間の結合
を密にして洩れインダクタンスを減少させること
ができ、しかも、2次巻線が実質的に二分割され
ているから2次巻線全体としての分布容量も小さ
くなり、従つて、2次巻線に発生するパルス電圧
に所望の高次高調波同調を行なわせることができ
ると云う利点もある。また、フオーカス電圧取り
出し用の可変抵抗器18の両端間にダイオード1
6とコンデンサ17で整流平滑して得た電圧が印
加されており、その分圧後の電圧がコンデンサ1
4の両端間の直流電圧に重畳されて取り出される
から、この場合は第1図と同じ大きさのフオーカ
ス電圧を取り出すのに耐圧が1/2の可変抵抗器
で済むことになり、上記可変抵抗器18の小型化
が可能となる。
As described above, according to the high voltage generation circuit of the present invention, the maximum AC amplitude of the pulse voltage generated in the flyback transformer can be reduced, so corona discharge is less likely to occur in the flyback transformer, and flyback is prevented. Since the amount of alternating current flowing through the insulating resin in the back transformer is also reduced, the temperature rise in the fly back transformer can be suppressed. In addition, since corona discharge is less likely to occur as mentioned above, it is possible to reduce leakage inductance by tightly coupling the primary and secondary windings, and since the secondary winding is essentially divided into two, it is possible to reduce leakage inductance. There is also the advantage that the distributed capacitance of the winding as a whole is reduced, and therefore the pulse voltage generated in the secondary winding can be tuned to desired high-order harmonics. In addition, a diode 1 is connected between both ends of the variable resistor 18 for taking out the focus voltage.
A voltage obtained by rectifying and smoothing is applied to capacitor 6 and capacitor 17, and the voltage after division is applied to capacitor 1.
Since it is superimposed on the DC voltage between both ends of the 4 and taken out, in this case, a variable resistor with a withstand voltage of 1/2 is sufficient to take out the same focus voltage as shown in Fig. 1. The size of the container 18 can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の高圧発生回路を示す回路図、第
2図はそのフライバツクトランスの2次巻線に発
生するパルス電圧波形を示す図、第3図は本発明
の一実施例を示す回路図、第4図はそのフライバ
ツクトランスの2次巻線に発生するパルス電圧波
形を示す図、第5図は本発明の他の実施例を示す
回路図である。 4:フライバツクトランス、5,6,7:2倍
圧整流のダイオード、8,9:2倍圧整流用のコ
ンデンサ、14:他のコンデンサ、15:他のダ
イオード。
FIG. 1 is a circuit diagram showing a conventional high voltage generation circuit, FIG. 2 is a diagram showing a pulse voltage waveform generated in the secondary winding of the flyback transformer, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. 4 is a diagram showing a pulse voltage waveform generated in the secondary winding of the flyback transformer, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. 4: flyback transformer, 5, 6, 7: diodes for double voltage rectification, 8, 9: capacitors for double voltage rectification, 14: other capacitors, 15: other diodes.

Claims (1)

【特許請求の範囲】 1 フライバツクトランスの2次巻線4bに多倍
圧整流回路5,6,7,9を接続すると共に、上
記2次巻線4bの低電位側の一端にダイオード1
5のカソード側を接続し、このダイオード15の
アノード側と上記2次巻線に設けた中間タツプM
との間にコンデンサ14を接続した高圧発生回路
に於て、 前記2次巻線4bの高電位側の出力を整流する
ための整流用ダイオード16と、 一端がこの整流用ダイオード16に接続され、
他端が前記中間タツプMに接続される整流用コン
デンサ17と、 この整流用コンデンサ17に並列接続され、フ
オーカス電圧を出力する可変抵抗器18と、 を備えることを特徴とする高圧発生回路。
[Scope of Claims] 1 Multiplier rectifier circuits 5, 6, 7, and 9 are connected to the secondary winding 4b of the flyback transformer, and a diode 1 is connected to one end of the low potential side of the secondary winding 4b.
An intermediate tap M provided between the anode side of this diode 15 and the secondary winding is connected to the cathode side of the diode 15.
In the high voltage generation circuit in which a capacitor 14 is connected between the rectifier diode 16 for rectifying the high potential side output of the secondary winding 4b, and one end connected to the rectifier diode 16,
A high voltage generation circuit comprising: a rectifying capacitor 17 whose other end is connected to the intermediate tap M; and a variable resistor 18 connected in parallel to the rectifying capacitor 17 and outputting a focus voltage.
JP18332582A 1982-10-19 1982-10-19 High voltage generator circuit Granted JPS5972982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18332582A JPS5972982A (en) 1982-10-19 1982-10-19 High voltage generator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18332582A JPS5972982A (en) 1982-10-19 1982-10-19 High voltage generator circuit

Publications (2)

Publication Number Publication Date
JPS5972982A JPS5972982A (en) 1984-04-25
JPH0159832B2 true JPH0159832B2 (en) 1989-12-19

Family

ID=16133728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18332582A Granted JPS5972982A (en) 1982-10-19 1982-10-19 High voltage generator circuit

Country Status (1)

Country Link
JP (1) JPS5972982A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4923525A (en) * 1972-06-22 1974-03-02

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4923525A (en) * 1972-06-22 1974-03-02

Also Published As

Publication number Publication date
JPS5972982A (en) 1984-04-25

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