JPH0159732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mask alignment method that can automatically align a wafer and a mask.

In photolithography, which is used in the manufacturing process of semiconductor devices, a mask pattern is printed onto the surface of a wafer, which is the workpiece, so it is necessary to align the wafer and mask in a predetermined positional relationship. A so-called mask aligner is used for alignment. FIG. 1 shows an alignment method using this type of aligner. Targets 3 and 4 are formed at corresponding positions on wafer 1 and mask 2, respectively, and when mask 2 is stacked on wafer 1, each The overlap between the targets 3 and 4 can be viewed from above, and alignment can be performed by relatively moving the two targets so that the overlapping state is in a preset state. To detect the overlapping state of the targets 3 and 4, a scanning method using a slit 5 is used as shown in the figure.

However, this method using a slit relies on the principle of detecting the difference in the amount of reflected light at the target, so it has the disadvantage that accurate target detection cannot be performed in situations where the slit scans something other than the target. There is. In other words, attempts have been made to form a target 3 on a scribe grid 6 as shown in FIG. 2A in order to increase the rate of obtaining chips from a wafer, but the width of the scribe grid is limited. As a result, one element pattern 7 tends to overlap the other target 4 as shown in FIG. 3, and alignment becomes impossible in such a case.

For this reason, conventionally, as shown in Figure 2B,
Two chips to be formed are crushed and a target is formed therein, so that the target and the other pattern do not overlap. However, it cannot be denied that if this method is used, the rate of obtaining chips from the wafer will decrease, and if for some reason there is a large positional deviation between the two, even though the target is formed within the chip, Overlapping of the target and pattern may occur, making automatic alignment using the slit impossible.

Therefore, the present invention recognizes the targets using a pattern recognition method and performs coarse alignment between the wafer and the mask, and recognizes each target using a position recognition method and performs fine alignment, so that each target can be accurately aligned on the scribe grid. It is an object of the present invention to provide a mask alignment method capable of automatically aligning the mask by forming a target on the mask.

Hereinafter, the present invention will be explained based on the drawings.

FIG. 4 is a diagram showing the overall configuration of an apparatus capable of realizing the mask alignment method of the present invention.
2 is fixed at a predetermined position, and the wafer 11 is aligned with respect to this mask 12. The mask 12 and the wafer 11 are provided with targets 15 and 16 at opposite positions of the scribe grids 13 and 14, respectively.The target 15 of the mask 12 is arranged in a two-line cross, and the target 16 of the wafer 11 is arranged in a thick line. A cross 16a and a thin line 16b extending outward from the cross 16a. wafer 1
1 is placed on the X, Y, θ table 17 and
It is slightly moved in the Y and θ directions by a pulse motor, etc.
Furthermore, TV cameras 18A and 18B are placed above the targets 15 and 15 of the mask 12, respectively, so that the targets 15 and 16 can be imaged and detected. Note that each of the TV cameras 18A and 18B is rotated by 45 degrees with respect to the X axis of the X, Y, θ table 17.

Each of the TV cameras 18A and 18B is connected to a video processing unit 19 that cuts the captured video signal at an appropriate threshold value and binarizes it into 120×160 picture elements, for example. The video processing unit 19 includes a partial pattern cutting unit 20 that cuts out the binarized signal into, for example, 12×12 bit partial patterns, and compares this cut signal with a dictionary pattern 21 shown in FIG. A coarse recognition processing circuit 26 is connected to the comparison section 22, a coincidence detection counter 23 that detects the degree of coincidence between the two, and a microcomputer 25 that calculates the amount of positional deviation based on the output of this counter and operates the pulse motor control section 24. . The video processing unit 19 also includes an HD component extraction unit 27 that extracts H and D (horizontal and vertical) components of the targets 15 and 16, a counter 28 that counts sampling pulses, and a counter 28 that detects relative positions and detects deviation amounts. A relative position detection section 29 for reading the information and a precision recognition processing circuit 30 consisting of the microcomputer 25 are connected. In the figure, 31 is a synchronization signal generator,
For example, 3MHZ and 18MHZ sampling pulses are sent to the circuits 26 and 30.

Next, the method of the present invention will be explained.

First, mask 12 is used with TV cameras 18A and 18B.
And each target 15, 16 of the wafer 11 is imaged. Then, this video is processed by the video processing section 19.
After binarizing into 120×160 picture elements, the partial pattern cutting unit 20 sequentially divides the picture elements into 12×
A partial pattern of 12 bits is cut out, and each time this partial pattern is compared with the dictionary pattern 21 of FIG. 5 in the comparing section 22. Through this comparison, the counter 23 is able to detect the part with the highest degree of coincidence, and the current wafer 1
It can be determined in which part of the picture element the bold cross 16a of No. 1 exists, and therefore the microcomputer 25
The amount of deviation of the wafer 11 can be calculated by
target 16 as shown in Figure 6 A to B.
Approximately the center of the TV camera image plane, in other words mask 1
It can be set at approximately the center position of the second target 15.
This operation is performed using the TV cameras 18A and 18B at two targets, thereby completing the rough alignment of the mask 12 and the wafer 11, and at least at the positions where the targets 15 and 16 and the element patterns 11a and 12a do not overlap. You can combine both.

Next, after rough alignment as shown in Figure 6,
The HD component extraction unit 27 performs horizontal and vertical masking M _H and M _D as shown in FIG.
Scan vertically to target 15, 16, 16
Extract the horizontal and vertical components of b. FIG. 8 shows an example in which horizontal components are extracted. Then, the interval a, b between the targets 15 and 16 detected by this component is calculated by using the sampling pulse SP at the counter 28.
The relative positions of targets 15 and 16 are determined by counting at . In this example, the thin wire 16b of the target 16 is placed between the two thin wires 15a and 15b of the target 15, and the correct position is the position where the spacing a and b between the thin wire 16b and the thin wires 15a and 15b are equal. Therefore,
The amount of deviation between the targets 15 and 16 can be detected from the relative positions, and based on this, the pulse motor control section 24 performs feedback control on the X, Y, and θ tables 17 to align the wafer 11 and mask 12 with high precision. can be done. It goes without saying that similar operations can also be performed in the vertical direction.

As described above, the mask and wafer alignment can be completed, so even if the target is formed on the scribe grid, the coarse recognition processing circuit can automatically perform the coarse alignment, improving the chip acquisition rate. On the other hand, fully automatic alignment can be performed in combination with a precision recognition processing circuit.

Although the targets 15 and 16 may have other shapes, the target on the movable side (usually the wafer side) needs to have a shape that allows pattern recognition and horizontal and vertical position recognition.

As described above, according to the mask alignment method of the present invention, one of the targets formed on the wafer and the mask is pattern-recognized to perform precise alignment of both, and both targets are position-recognized to achieve precise alignment of both. Therefore, even if the target is formed on the scribe grid, accurate positioning can be performed fully automatically, and the chip acquisition rate can be improved.

[Brief explanation of drawings]

Fig. 1 is a schematic perspective view of the conventional method, Fig. 2 A and B are enlarged views of the conventionally formed target part, Fig. 3 is an enlarged view of the target part to explain the problem, and Fig. 4 is the present invention. Fig. 5 is a dictionary pattern diagram, Fig. 6 is an enlarged view of the target area after rough alignment, and Fig. 7 is a state in which horizontal and vertical components are extracted. FIG. 8 is an enlarged view of the target section showing the state of the video signal. 11... Wafer, 12... Mask, 13, 14...
Scribe grid, 15 (15a, 15b),
16 (16a, 16b)...Target, 17...
X, Y, θ table, 18A, 18B...TV camera, 21...Dictionary pattern, 24...Pulse motor control unit, 25...Microcomputer, 26...Rough recognition processing circuit,
30... Fine recognition processing circuit, SP... Sampling pulse.

Claims (1)

[Scope of Claims] 1. A wafer (mask) having a target consisting of a thick line for coarse alignment and a first thin line for fine alignment, and a wafer (mask) having a target formed of a thick line for coarse alignment and a thin line for fine alignment; Coarse alignment and fine alignment with a mask (wafer) having a target made of the formed second fine alignment thin line are performed by fixing the mask (wafer) within the same field of view in a specific range,
When performing this by moving the wafer (mask), a) preparing a standard pattern having a pattern that almost matches the rough alignment thick line pattern of the wafer (mask), and b) determining the position of the standard pattern. c) sequentially recognize the patterns within the field of view using a pattern recognition method; d) among the sequentially recognized patterns, the pattern with the highest degree of matching with the standard pattern. By selecting a high pattern part, the position of the thick line for rough alignment of the wafer (mask) is assumed; e) the deviation between the assumed position and a specific position on the mask (wafer); f) roughly aligning the wafer and the mask by moving in the specific position direction based on the amount of deviation in e); g) adjusting the position of the wafer (mask); The distance between the first fine alignment thin line and the second fine alignment thin line of the mask (wafer) is detected in at least two locations in the horizontal direction (vertical direction), and the distance between the two fine alignment thin lines detecting the amount of deviation from the above-mentioned predetermined positional relationship; h) moving the wafer (mask) based on the amount of deviation in g), thereby performing precise alignment of the wafer and the mask; A mask alignment method characterized by: