JPH01592A - Vector generation circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vector generation circuit in a raster scan type graphic display device for displaying input/output information of an electronic computer or the like.

In conventional technology graphics displays, for example, in order to draw a pattern at any position, at any size, and at any angle, the pattern data is held as a vector, the necessary calculations are performed, and the vector for straight line drawing is created. Patterns are often drawn by feeding data to a generating circuit. Blesenham's method is known as an algorithm for finding a straight line connecting the coordinates of two given points as a sequence of points.

To draw a straight line using Plersenham's method, start point Cx
BtyB) and the coordinates of the end point (xy, yy), ΔX = x
y-! S, Δy = yy-y3 tD = MAX
(IΔ!1, 1Δy1).

Calculate D I = MIN (IΔ11, 1Δyl), determine whether to increment or decrement the coordinates to be drawn based on the numbers ΔI and Δy, and calculate 1Δx1,
It is necessary to determine the reference axis by determining the larger value of 1Δy1.

FIG. 4 is a circuit diagram of an initial setting section in a conventional pattern vector generation circuit that performs the above calculation, and FIG. 3 is a block diagram of a portion of a graphic display device used for pattern drawing.

An example of conventional vector pattern drawing will be shown using character drawing as an example using FIG. 4 and FIG. Reference numeral 37 denotes an address decoder circuit, which decodes an address issued by the CPU 31 and controls the external circuit when the central processing unit (hereinafter referred to as CPU) 31 accesses the external circuit. The CPU 31 that manages the graphic display (Is
, ys) When there is a request to draw a character at a point, the address where the data of that character is stored and the number of data are learned from the memory 32, and the character data (flag t''otyo) is read from the memory 32.

Next, the CPU 31 checks this flag, checks whether it is the start point or the end point of the straight line, and! o'=!
S+! Oy 70' ”” 7j3 + 70
is calculated and sent to the initial setting section 33 through the system bus 1.
The data on the system bus 1 passes through the buffer 2, and if it is the starting point, it is sent to the latch 53.
ty3) is read in, and if it is the end point, the latch 64 (x
Ft7y) is read.

Logic operation units (hereinafter abbreviated as ALU) 65 and 56 receive ΔX from xs and Xy, and Δy from 7B and 7F, respectively.
Calculate. ALU5 completed and 68 are each Δ! , the absolute value of Δy is calculated. Comparator 69 is 1Δx1 and l
Δ1 is compared and the result is sent to the multiplexer 80,
61, multiplexer 60 selects the larger one, and multiplexer 61 selects the smaller one.

Furthermore, after the data is stored in the latch 64 that stores the end point, the calculation time of the initial setting section is guaranteed, and the latch 63 is
(!5t7B) from multiplexer 80 to MA
X(lΔ!1.IΔyl), MIN(lΔ!1,1Δyl) from multiplexer 61, AI, U55.5
The numbers ΔX and Δy are fetched from the latch 13 from the comparator 69, and the reference axis is fetched from the comparator 69, respectively.

Using these parameters, a digital differential analysis circuit (hereinafter abbreviated as DDA) 34 calculates a drawing point and writes it into the frame memory 36. After the parameters are loaded into the latch 13, end point data is written into the latch 53 through the multiplexer 52.

By repeating the above operation for the number of character data, any character can be written at any position. Frame memory information is converted to DA and cathode ray tube (hereinafter referred to as CRT) 3s
displayed as image information.

Problems to be Solved by the Invention However, in the configuration of the first half, the graphic display cannot be used, for example, when drawing characters as a character terminal (console mode), when drawing kanji etc. as a word processor, or when registering pattern figures. When drawing a pattern without enlarging or rotating it, in order to draw the pattern at an arbitrary position, the reading cycle of the CPU 31 and the position of the data and pattern are required for all data of the pattern. Since the addition of 1 and a write cycle are necessary, the display speed has been slow.

Therefore, an object of the present invention is to provide a vector generation circuit that reduces the burden on the CPU 31 and executes high-speed drawing for pattern data that does not require enlargement or rotation.

Means for Solving the Problems The present invention includes a memory that stores pattern vector data expressed in relative coordinates, flag data indicating whether the next vector data is drawn or moved, and a memory that stores the drawing start position as absolute coordinates. a first register for storing the drawing or movement distance; an adder for adding the drawing start position and the drawing or movement distance; This vector generation circuit includes means for storing in one register and means for storing an output to a digital differential analyzer.

Effects According to the present invention, when drawing a pattern that does not require two rotations of enlargement, the drawing start position is added only once at the start among the position data of a plurality of patterns, and the second Subsequent data will no longer be necessary. Furthermore, since the second and subsequent data can use the data already in the memory as is, the central processing unit can transfer the data to the vector generation circuit by just performing one read cycle for each piece of data. moreover,
The decision whether to draw or move can be made at the same time as the calculation of the vector generation circuit using the previous data.

Embodiment FIG. 1 is a block diagram of the initial setting section of the vector generation circuit in one embodiment of the present invention, and FIG. 2 is a schematic diagram of the memory storing the pattern in the case of the character 1A. Using this and Figure 3,
The case of drawing "A" will be explained. CPU31
When there is a request to draw "A" at position (!B, 7B), the address (pointer) that stores the data of "A" and the number of data required to draw "A" are sent. Learn from memory 32. The CPU 31 uses the upper address to read the initial data, and uses the lower address to perform a read cycle for the pointer, x = 6,
Know that y = 20 and flag = ○.

For example, the drawing position of characters! S: 100°7S = 1
00, the CPU 31 performs addition and xO=105
．． Data is placed on the data bus 1 using ys=120 as the absolute coordinates of the drawing start point. The address decoder circuit 37 decodes the address in the case of absolute coordinates of the drawing start point.
controls the control signal 17 and the multiplexer -3.

As a result, the data on the data bus 1 is transmitted via the buffer 2 to the latch 4 that stores the drawing start position, and the address decoder circuit 37 causes the latch 4 to take in the data using the control signal 18 while ensuring the time.

Here, the CPU 31 checks the flag and learns that the next data is a drawing command. (In the case of a movement command, the flag is set to 1 here.) The next higher address indicates the end point of drawing, the lower address indicates the next data pointer, and the data is stored in the memory 32. A read cycle is performed on the data. The address decoder circuit 37 causes the memory 32 to load the data onto the data bus 1, guarantees the data confirmation time, and the relative coordinates of the drawing end point Δx=15
．． When Δy=o is loaded into the latch 6 and the same data (flag=o, Δ!=15°Δy=o) is also read into the CPU, the read cycle of the CPU 31 is ended.

In addition, ALUs 9 takes the absolute values of ΔI and Δy, and comparator 1o indicates IΔ! 1 and 1Δyl are compared, and based on the outputs, multiplexer 11 outputs the larger one, and multiplexer 12 outputs the smaller one.

The latch 13 is a latch that stores a value necessary for the DDA 34 to operate, and the obtained value is exactly the same as that described in the conventional method.

The control signal 21 guarantees the computation time after inputting the relative coordinates of the end point. The control signal 22 ensures that the DDA 34 completes the calculation. If both have been completed, the latch 13 takes in the data and the DDA starts calculation.

6.7 is an ALU that calculates the coordinates of the end point by adding relative coordinates ΔX and Δy to the I and y coordinates of the starting point, respectively,
After the data is loaded into the latch 13, the coordinates of the drawing end point are loaded into the latch 4.

During this time, the CPU 51 checks the flag and knows that the next command is also a drawing command, so it performs the same cycle as described above. During this period, DDA changes from (105, 120) to (12
Frame memory 3 as a straight line as a point sequence up to 0,120)
Write in 5. When the CPU performs a flag check, it is found that the next instruction is a move instruction.

Furthermore, in the next cycle, the CPU 31 indicates relative coordinate movement using an upper address, indicates the next pointer using a lower address, and performs a read cycle to the memory 32. Like the drawing command, the latch 6 and CPU 31
receives the data, but since the control signal 21 from the decoding circuit that decoded the upper address does not operate, the latch 13 does not operate, but the latch 13 receives the signal from the control signal 18 and is calculated using ALUe, 7. The coordinates of the end point are captured in the latch 4. During this time, DDA34 (12
Draw a straight line from 0°120) to (119,112).

The CPU 31 similarly checks the flag and learns that the next data is a drawing command. Since there is no new data in latch 13, DDA 34 does not operate.

Similarly, the next cycle is performed, and the CPU 31 knows from the first memorized data count that the drawing of 6A'' data has been completed, and executes the next command.

After the calculation of the initial setting section is completed, the DDA34
, 114) to (1os, 104), and the drawing of "A" is completed.

As described above, the graphic display is managed by allowing the drawing start position to be moved using relative coordinates in the initial setting section of the DDA 34, and by setting a flag indicating whether it is a movement command or a drawing command immediately before the data. The determination of whether it is drawing data of the CPU 31 or movement data is made by the calculation of the initial setting section and the DDA.
34 calculations can be performed simultaneously, and the CPU 31
This eliminates the need for writing cycles, making it possible to draw character patterns at extremely high speed.

As described in detail, according to the present invention, it is possible to draw vector data patterns at high speed without the need for expansion or rotation, and when the graphic display is used in console mode or as a word processor display. etc., a particularly high-speed reaction can be obtained, and its practical effects are great.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the initial setting section of a vector generation circuit according to an embodiment of the present invention, and Fig. 2 is a schematic representation of how data is held in the data memory in the same embodiment, using "A" as an example. The explanatory diagram, FIG. 3, is a block diagram of a portion necessary for drawing a character pattern on a graphic display, and FIG. 4 is a block diagram of an initial setting section of a conventional vector generation circuit. 1...System bus, 31...Central processing unit (CPU), 32...Memo IJ-1
33...Initial setting circuit, 34...Vector generation circuit (DDA), 36...Frame memory, 3θ...Cathode ray tube (CRT). Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 55.5 &, 57. ! 23- A L U39-
Comparator ω, 67- Marvalve plenchner Fig. 4

Claims (1)

[Claims] In a graphic display device using raster scan point display, a memory stores pattern vector data expressed in relative coordinates, flag data indicating whether to draw or move, and a first register stores a drawing start position as absolute coordinates. a second register for storing a drawing or movement distance; an adder for adding the drawing start position and the drawing or movement distance; and storing the output of the adder in the first register as a new drawing start position. and means for controlling writing to a third register that stores an output to a digital differential analyzer.