JPH0158871B2 - - Google Patents
Info
- Publication number
- JPH0158871B2 JPH0158871B2 JP57005679A JP567982A JPH0158871B2 JP H0158871 B2 JPH0158871 B2 JP H0158871B2 JP 57005679 A JP57005679 A JP 57005679A JP 567982 A JP567982 A JP 567982A JP H0158871 B2 JPH0158871 B2 JP H0158871B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- input protection
- gate
- input
- planar shape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 20
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 230000015556 catabolic process Effects 0.000 description 4
- 230000006378 damage Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
- Amplifiers (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
発明の技術分野
この発明はたとえばMOS形集積回路における
入力トランジスタのゲートの破壊を防止する入力
保護装置に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to an input protection device for preventing destruction of the gate of an input transistor in, for example, a MOS type integrated circuit.
発明の技術的背景
一般にMOS FETのゲートは、そのゲート耐
圧以上の電圧が印加されると破壊される。極めて
注意深く作られたMOS FETのゲート絶縁膜た
とえばシリコン酸化膜（SiO2）は、107V／cm程
度の電界が加えられても破壊されない。たとえば
1000Åのゲート膜厚を持つMOS FETは、ゲー
トに100V程度の電圧が印加されても破壊されな
い。ところがこれ以上の電圧、たとえば静電気等
のサージ電圧が印加された場合、上記ゲート膜厚
を持つMOS FETは破壊されてしまう。したが
つて、このようなサージ電圧による破壊を防止す
るため、MOS形集積回路には第１図に示すよう
な構成の入力保護装置が設けられている。図にお
いてデイプレツシヨンモードのMOS FET QDと
エンハンスメントモードのMOS FET QEとは
MOS形集積回路の入力段のインバータを構成し、
このうちMOS FET QEのゲートには入力端子Io
の信号が与えられるようになつている。上記入力
端子Ioには入力保護装置を構成する抵抗Ｒの一端
が接続され、この抵抗Ｒの他端は同じく入力保護
装置を構成するダイオードＤのカソードと上記
MOS FET QEのゲートに接続される。上記ダイ
オードＤのアノードは接地電位点（基準電位点）
に接続される。すなわち、第１図の回路では入力
端子Ioと入力段のMOS FET QEのゲートとの間
に、抵抗ＲとダイオードＤとからなる入力保護装
置が挿入されている。Technical Background of the Invention Generally, the gate of a MOS FET is destroyed when a voltage higher than its gate withstand voltage is applied. The gate insulating film of a MOS FET, such as a silicon oxide film (SiO 2 ), is created with great care and will not be destroyed even when an electric field of about 10 7 V/cm is applied. for example
A MOS FET with a gate film thickness of 1000 Å will not be destroyed even if a voltage of about 100 V is applied to the gate. However, if a voltage higher than this is applied, for example a surge voltage such as static electricity, the MOS FET having the above gate film thickness will be destroyed. Therefore, in order to prevent damage caused by such surge voltages, MOS integrated circuits are provided with an input protection device having a configuration as shown in FIG. In the figure, what is MOS FET Q D in depletion mode and MOS FET Q E in enhancement mode?
Configures the input stage inverter of a MOS integrated circuit,
Among these, the input terminal I o is connected to the gate of MOS FET Q E.
signals are now being given. One end of a resistor R that constitutes an input protection device is connected to the input terminal Io , and the other end of this resistor R is connected to the cathode of a diode D that also constitutes an input protection device.
Connected to the gate of MOS FET Q E. The anode of the diode D above is the ground potential point (reference potential point)
connected to. That is, in the circuit shown in FIG. 1, an input protection device consisting of a resistor R and a diode D is inserted between the input terminal I o and the gate of the input stage MOS FET Q E.
このような回路において、入力端子Ioにサージ
電圧が印加されると、ダイオードＤがブレークダ
ウンを起こしてMOS FET QEのゲートにはこの
ブレークダウン電圧以上の電圧は印加されない。
したがつて、MOS FET QEは破壊から保護され
る。また、上記抵抗Ｒは、ブレークダウン時、ダ
イオードＤに流れる電流を制限する機能を有し、
過電流によりダイオードＤが破壊されることを防
止するとともに、サージ電圧印加時にダイオード
Ｄのカソードに加えられる電圧の立ち上りをゆる
やかにする機能も有し、この機能によつてダイオ
ードＤのブレークダウンのスイツチングがMOS
FET QEのゲートに高電圧が印加される前に起こ
るようにしている。なお、上記抵抗Ｒは絶縁膜内
に設けられたポリシリコン層や半導体基体内に設
けられた拡散領域等によつて構成されている。 In such a circuit, when a surge voltage is applied to the input terminal Io , diode D causes breakdown and a voltage higher than this breakdown voltage is not applied to the gate of MOS FET QE .
Therefore, MOS FET Q E is protected from destruction. Further, the resistor R has a function of limiting the current flowing through the diode D at the time of breakdown,
In addition to preventing diode D from being destroyed due to overcurrent, it also has the function of slowing the rise of the voltage applied to the cathode of diode D when a surge voltage is applied, and this function allows switching of the breakdown of diode D. is MOS
This occurs before high voltage is applied to the gate of FET Q E. Note that the resistor R is constituted by a polysilicon layer provided within an insulating film, a diffusion region provided within a semiconductor substrate, and the like.
ところで、最近のように、集積回路の集積度が
向上し、素子が微細化されてくると、上記抵抗Ｒ
のパターン形状もそれに伴つて小さくする必要が
生じる。このことは、同一抵抗値を得るために抵
抗Ｒのパターン形状の幅を小さくすれば長さも必
然的に短かなものとなり、集積度から見れば好都
合である。また、上記抵抗Ｒを構成する場合、従
来では、パターンレイアウト上、第２図のパター
ン平面図に示すようにその平面形状に折れ曲がり
部分が生じるように構成される。 By the way, recently, as the degree of integration of integrated circuits has improved and elements have become smaller, the resistance R
The pattern shape also needs to be made smaller accordingly. This means that if the width of the pattern shape of the resistor R is made smaller in order to obtain the same resistance value, the length will inevitably be made shorter, which is advantageous from the viewpoint of the degree of integration. Furthermore, when configuring the resistor R, conventionally, the resistor R is constructed so that its planar shape has a bent portion due to the pattern layout, as shown in the pattern plan view of FIG.
背景技術の問題点
ところが、上記抵抗Ｒのパターン形状の幅を小
さくすれば電流密度が大きくなり、しかも抵抗Ｒ
の折れ曲がり部分の内側の谷部における電流密度
が極めて大きくなる。この結果、MOS FET QE
は保護されるが、抵抗Ｒの折れ曲がり部分での溶
断事故が多発するようになつた。これは抵抗Ｒの
折れ曲がり部分がジユール熱による発熱によつて
溶断するものである。また、一般に上記抵抗Ｒを
絶縁膜内に設けたポリシリコン層によつて構成す
る場合の方が、半導体基体内に設けた拡散領域に
よつて構成する場合よりも放熱がしにくく、した
がつて抵抗Ｒをポリシリコン層によつて構成した
場合に上記問題が多く発生する。Problems with the Background Art However, if the width of the pattern shape of the resistor R is made smaller, the current density increases;
The current density in the valley inside the bend becomes extremely large. As a result, MOS FET Q E
However, fusing accidents at the bent portion of the resistor R have become more frequent. This is because the bent portion of the resistor R is fused due to the heat generated by the Joule heat. Additionally, in general, when the resistor R is constructed from a polysilicon layer provided within an insulating film, heat is more difficult to dissipate than when constructed from a diffusion region provided within a semiconductor substrate. The above problems often occur when the resistor R is made of a polysilicon layer.
発明の目的
この発明は上記のような事情を考慮してなされ
たもので、その目的とするところは、集積回路の
微細化に適し、しかも入力保護用の抵抗が溶断さ
れにくい入力保護装置を提供することにある。Purpose of the Invention The present invention has been made in consideration of the above circumstances, and its purpose is to provide an input protection device that is suitable for miniaturization of integrated circuits and in which the input protection resistor is less likely to be blown out. It's about doing.
発明の概要
この発明による入力保護装置は、入力保護用の
抵抗を絶縁膜中に設けられた一様な幅のポリシリ
コン層によつて構成し、しかもパターンレイアウ
ト上この抵抗の平面形状に折れ曲がり部分が生じ
るように形成し、上記抵抗の平面形状の折れ曲が
り部分の内側の谷部をポリシリコン領域で埋め
て、折れ曲がり部分の内側の電流密度を低下させ
ることによつて、入力保護用の抵抗の溶断を防止
するようにしたものである。SUMMARY OF THE INVENTION The input protection device according to the present invention comprises an input protection resistor made of a polysilicon layer of uniform width provided in an insulating film, and furthermore, the pattern layout includes bent portions in the planar shape of the resistor. By filling the valley inside the bent part of the planar shape of the resistor with a polysilicon region and lowering the current density inside the bent part, the input protection resistor can be melted. It is designed to prevent this.
発明の実施例
以下、図面を参照してこの発明の各実施例を説
明する。第３図ａないしｄはそれぞれ、この発明
に係る入力保護装置に用いられる入力保護用の抵
抗Ｒの平面形状を示すパターン平面図であり、こ
の抵抗Ｒは絶縁膜内に設けたポリシリコン層によ
つて構成されている。Embodiments of the Invention Each embodiment of the invention will be described below with reference to the drawings. FIGS. 3a to 3d are pattern plan views showing the planar shape of the input protection resistor R used in the input protection device according to the present invention, and this resistor R is formed on a polysilicon layer provided within the insulating film. It is structured accordingly.
第３図ａに示すものは、一様な幅のポリシリコ
ン層を、その平面形状がコの字形となるように折
曲した状態で形成して抵抗Ｒを構成し、２ヶ所の
折れ曲がり部分の内側の谷部１１，１２を、平面
形状が正方形状の一対の各ポリシリコン領域１
３，１４で埋めるようにしたものである。 In the resistor R shown in FIG. 3a, a polysilicon layer with a uniform width is formed by bending the polysilicon layer so that its planar shape is U-shaped. The inner valleys 11 and 12 are formed by a pair of polysilicon regions 1 each having a square planar shape.
It is designed to be filled with numbers 3 and 14.
抵抗Ｒのパターン形状を上記のようにすること
により、折れ曲がり部分の内側における電流密度
が従来よりも小さくなり、この部分における発熱
も少なくなつて、抵抗Ｒは従来に比較して溶断し
にくくすることができる。 By making the pattern shape of the resistor R as described above, the current density inside the bent part becomes smaller than before, and the heat generation in this part also decreases, making the resistor R more difficult to blow out than before. Can be done.
第３図ｂに示すものは、２ヶ所の折れ曲がり部
分の内側の谷部１１，１２を、平面形状が三角形
状の一対の各ポリシリコン領域１５，１６で埋め
るようにしたものである。そしてこの場合にも第
３図ａのものと同じ理由により、抵抗Ｒは従来に
比較して溶断しにくくすることができる。 In the structure shown in FIG. 3B, the valleys 11 and 12 inside the two bent portions are filled with a pair of polysilicon regions 15 and 16 each having a triangular planar shape. Also in this case, for the same reason as in FIG. 3a, the resistor R can be made more difficult to melt than in the past.
第３図ｃに示すものは、第３図ａ中の一対のポ
リシリコン領域１３，１４を互いに延長形成して
１つのポリシリコン領域１７としたものである。 In the case shown in FIG. 3c, the pair of polysilicon regions 13 and 14 in FIG. 3a are formed to extend from each other to form one polysilicon region 17.
第３図ｄに示すものは、上記第３図ｃ中のポリ
シリコン領域１７を設けるとともに、この領域１
７を設けたことによつて新たに発生する２ヶ所の
谷部１８，１９を、平面形状が長方形の一対の各
ポリシリコン領域２０，２１で埋めるようにした
ものである。 In the case shown in FIG. 3d, the polysilicon region 17 shown in FIG. 3c is provided, and this region 1
Two new valleys 18 and 19 created by providing the polysilicon regions 7 are filled with a pair of polysilicon regions 20 and 21 each having a rectangular planar shape.
このように上記各実施例では抵抗Ｒの折れ曲が
り部分の内側の谷部をポリシリコン領域で埋める
構成としたので、幅を小さくしてもすなわち微細
化しても、抵抗Ｒを溶断しにくくすることができ
る。 In each of the above embodiments, the valley inside the bent portion of the resistor R is filled with the polysilicon region, so even if the width is reduced, that is, the resistor R is miniaturized, it is difficult to blow out the resistor R. can.
なお、この発明は上記各実施例に限定されるも
のではなく、たとえば前記折れ曲がり部分の内側
の谷部１１，１２あるいは１８，１９を埋めるポ
リシリコン領域１５，１６あるいは２０，２１の
平面形状が、正方形、三角形および長方形である
場合について説明したが、これはどのような形状
でもよい。さらに抵抗Ｒには２ヶ所の折れ曲がり
部分がある場合について説明したが、これは何ケ
所設けられていてもよく、折れ曲がりの角度も直
角以外でもよい。 Note that the present invention is not limited to the above embodiments; for example, the planar shape of the polysilicon regions 15, 16 or 20, 21 that fills the valleys 11, 12 or 18, 19 inside the bent portions is Although square, triangular, and rectangular shapes have been described, any shape may be used. Further, although the case where the resistor R has two bent portions has been described, the resistor R may be provided in any number of places, and the angle of the bent portion may also be other than a right angle.
発明の効果
以上説明したようにこの発明によれば、集積回
路の微細化に適し、しかも入力保護用の抵抗が溶
断されにくい入力保護装置を提供することができ
る。Effects of the Invention As described above, according to the present invention, it is possible to provide an input protection device which is suitable for miniaturization of integrated circuits and whose input protection resistor is less likely to be blown out.
第１図は入力保護装置の一般的な構成を示す回
路図、第２図は上記装置に用いられる抵抗の平面
形状を示すパターン平面図、第３図ａないしｄは
それぞれこの発明の各実施例による抵抗の平面形
状を示すパターン平面図である。
QD……デイプレツシヨンモードのMOS FET、
QE……エンハンスメントモードのMOS FET、Io
……入力端子、Ｒ……抵抗、Ｄ……ダイオード、
１１，１２，１８，１９……谷部、１３，１４，
１５，１６，１７，２０，２１……ポリシリコン
領域。
FIG. 1 is a circuit diagram showing a general configuration of an input protection device, FIG. 2 is a pattern plan view showing the planar shape of a resistor used in the above device, and FIGS. 3 a to 3 d are respective embodiments of the present invention. FIG. 2 is a pattern plan view showing a planar shape of a resistor according to FIG. Q D ... MOS FET in depression mode,
Q E ……Enhancement mode MOS FET, I o
...Input terminal, R...Resistor, D...Diode,
11, 12, 18, 19...Tanibe, 13, 14,
15, 16, 17, 20, 21... polysilicon region.
Claims (1)
の間に入力保護用の抵抗を挿入し、この抵抗を絶
縁膜中に設けられたポリシリコン層によつて構成
し、しかもその平面形状に折れ曲り部分が生じる
ように上記抵抗を形成し、この曲り部分の内側の
谷部を埋めるようなポリシリコン領域を設けるよ
うに構成したことを特徴とする入力保護装置。1. A resistor for input protection is inserted between the input terminal and the gate of the transistor in the input stage, and this resistor is made of a polysilicon layer provided in an insulating film, and the bent portion in the planar shape is 2. An input protection device characterized in that the resistor is formed so that the above-mentioned resistor is formed, and a polysilicon region is provided to fill a valley inside the curved portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57005679A JPS58123769A (en) | 1982-01-18 | 1982-01-18 | Protective device for input |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57005679A JPS58123769A (en) | 1982-01-18 | 1982-01-18 | Protective device for input |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58123769A JPS58123769A (en) | 1983-07-23 |
| JPH0158871B2 true JPH0158871B2 (en) | 1989-12-13 |
Family
ID=11617775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57005679A Granted JPS58123769A (en) | 1982-01-18 | 1982-01-18 | Protective device for input |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58123769A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021077797A (en) * | 2019-11-12 | 2021-05-20 | ソニーセミコンダクタソリューションズ株式会社 | Semiconductor device and electronic apparatus |
-
1982
- 1982-01-18 JP JP57005679A patent/JPS58123769A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58123769A (en) | 1983-07-23 |
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