JPH0158595B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a dynamic semiconductor memory device that can prevent soft errors caused by alpha lines.

[Technical background of the invention and its problems]

Conventionally, a dynamic type semiconductor memory device has a structure in which unit memory cells are arranged in a matrix as shown in FIG. In other words, the bit line
A switching MOS transistor Q and a MOS capacitor C are connected between BL and the reference potential supply source V.
are connected in series, and the gate electrode of the transistor Q is connected to the word line WL. Then, the switching MOS transistor of the memory cell selected by the word line and bit line is turned on, and the charge is accumulated in the capacitor to hold the memory, and the charge accumulated in the capacitor C is transferred to the switching MOS transistor. It is read out onto the bit line via a transistor. The read storage information is determined by comparing the charge read onto the bit line with the reference charge of the dummy cell by a sense amplifier.

By the way, the above-mentioned dynamic type storage device retains stored information using the electric charge stored in the capacitor, so if the stored electric charge is lost due to leakage etc., it is likely to lead to misjudgment of the stored information. . In particular, a malfunction mode that is difficult to deal with in terms of process and design is soft errors caused by alpha wires. This is because when α particles emitted by extremely small amounts of uranium (U) and thorium (Th) atoms contained in semiconductor memory device packages enter the semiconductor substrate, many electron-hole pairs are generated. However, the stored contents are destroyed by collecting the generated electrons.

In order to prevent malfunctions caused by the above-mentioned α particles, the surface of a semiconductor memory device has conventionally been coated with a resin such as polyimide. With this configuration, even if α particles are emitted from the package toward the semiconductor surface, they are blocked by the coated resin layer and do not reach the semiconductor surface, so device operation is not affected.

However, such resin coatings involve several problems. First of all, although alpha particles released from the package can certainly be blocked, alpha particles released from the coating resin itself may reach the semiconductor surface and cause defects. Of course, the coating resin has α
Choose one that does not contain elements that emit particles, but if it is contained in extremely small amounts, it is difficult to detect and remove it.
On the other hand, even a very small amount of α particles can cause defects, which poses a major problem in systems that use a large number of such storage devices. Further, if an excessively purified substance is used, defects can be prevented, but the cost will be high and an inexpensive and high-performance device cannot be obtained.

Second, since a resin film of several tens of micrometers will be introduced into a process that previously used only thin films of about 1 micrometer, the processing method and the effect of the new material on the device are still unknown. There are many problems to be solved.

The defects caused by the soft errors mentioned above are expected to increase significantly as devices become denser and more integrated, and will become a serious problem as we enter the era of ultra-LSIs. ing.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to provide a highly reliable dynamic semiconductor memory device that can prevent malfunctions (soft errors) caused by alpha particles. It is.

[Summary of the invention]

That is, in this invention, in addition to the circuit configuration shown in FIG. The time constant of is set to be longer than the duration of the current generated by α rays.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.
In addition to the configuration shown in FIG. 1, a resistance element R is provided between the bit line BL and the switching MOS transistor Q. Then, the time constant given by this resistance element R and the storage capacitor C is set to be longer than the duration of the current generated by the α particles.

The operation of the above configuration will be explained with reference to FIG. on the P-type semiconductor substrate 11
n ⁺ diffusion layers 12 and 12' are formed, and the diffusion layer 12
(drain) is connected to the reference potential supply source V via the storage capacitor C, and the diffusion layer 1
2' (source) is connected to the bit line BL via the resistive element R.
It is connected to the. Here, the parasitic capacitance C _B of the bit line BL is about 10 times as large as that of the storage capacitor C. Now, as shown in the figure, when an alpha particle α is incident, a large number of electron-hole pairs are generated along its trajectory. Of this electron-hole pair, the electron follows the trajectory of the alpha particle α on the surface.
It moves toward the n ⁺ diffusion layer 12', lowering the potential of the circuit node of the n ⁺ diffusion layer 12'. At this time, the potential of the bit line BL decreases, but the change becomes slow due to the insertion of the resistor R.

It is known that the movement of electrons by alpha rays is extremely short-term, and the time change of this current is as shown in FIG. That is, momentarily
A current of about 300 μA flows, but it lasts only about 3 × 10 ^-10 seconds and quickly decays. Therefore, if the time constant of the resistive element R and the storage capacitor C is set to be larger than the duration of the current, malfunction will not occur even if alpha rays are incident.

Figure 5 shows the amount of decrease in the bit line potential by varying the resistance value of the resistor R. For example, in a circuit that will fail if the bit line level drops by 250mV or more, the resistance of the resistor If the value is 5kΩ or more, malfunctions and other defects will not occur.

FIG. 6 shows an example of forming the resistance element R.
Impurity diffusion layer 1 formed on semiconductor substrate 11
2' and the metal wiring 1 disposed through the insulating layer 13.
Use contact resistance with 4. Here, the impurity diffusion layer 12' corresponds to the source region of the transistor Q in FIG. obtain. With such a configuration, soft errors can be prevented without increasing the memory cell size.

As described above, even if alpha rays are incident on the semiconductor substrate, the potential of the bit line of the dynamic semiconductor memory device hardly decreases, so that soft errors caused by the bit line potential can be prevented. Although soft errors can also occur due to defects in circuits other than bit lines, it is generally thought that most soft errors are caused by bit lines. Therefore, soft errors in dynamic storage devices can be significantly reduced, and device reliability can be significantly improved. Moreover, since the surface of the semiconductor memory device is not coated with resin, there are no defects caused by alpha particles emitted by the resin, and there is no need to consider processing problems of the resin or the effects of the resin on the device.

〔Effect of the invention〕

As described above, according to the present invention, a highly reliable dynamic semiconductor memory device that can effectively prevent malfunctions (soft errors) caused by alpha particles can be obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a unit memory cell in a conventional dynamic semiconductor memory device, FIG. 2 is a circuit diagram showing a unit memory cell in a dynamic semiconductor memory device according to an embodiment of the present invention, and FIG. is a diagram for explaining the operation of the circuit shown in FIG. 2 above, FIG. 4 is a characteristic diagram showing the relationship between the current generated when alpha particles are incident on a semiconductor substrate and time, and FIG. FIG. 6 is a characteristic diagram showing the relationship between the amount of potential drop in the bit line that decreases when alpha particles are incident on the semiconductor substrate and the resistance value of the resistance element. FIG. 6 is a configuration diagram showing an example of forming the resistance element. . BL...Bit line, WL...Word line, Q...
MOS transistor for switching, C... capacitor for storage, R... resistance element, 11... semiconductor substrate, 12, 12'... impurity diffusion region.

Claims (1)

[Claims] 1. A switching MOS transistor whose one end is connected to a bit line and whose conduction is controlled by the word line potential, and a storage MOS transistor connected between the other end of this transistor and a reference potential supply source. In a memory device in which a capacitor is used as a unit memory cell and the unit memory cells are arranged in a matrix, the bit line is formed by a wiring spaced apart from the semiconductor substrate, and an impurity between the bit line and one of the switching transistors is formed. A semiconductor memory characterized in that a resistance element having a resistance value such that a time constant with a storage capacitor is larger than the duration of a current generated by alpha rays is disposed between the diffusion region and the storage capacitor. Device. 2. The semiconductor memory device according to claim 1, wherein the resistance element is a contact resistance between the bit line and one impurity diffusion region of the switching transistor.