JPH0158175U - - Google Patents

Info

Publication number
JPH0158175U
JPH0158175U JP15315587U JP15315587U JPH0158175U JP H0158175 U JPH0158175 U JP H0158175U JP 15315587 U JP15315587 U JP 15315587U JP 15315587 U JP15315587 U JP 15315587U JP H0158175 U JPH0158175 U JP H0158175U
Authority
JP
Japan
Prior art keywords
circuit
frequency
voltage
shot multi
power source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15315587U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP15315587U priority Critical patent/JPH0158175U/ja
Publication of JPH0158175U publication Critical patent/JPH0158175U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1A図はこの考案の一実施例によるF―Vコ
ンバータの構成図、第1B図はそのF―V特性を
説明するための図、第2A図および第3A図はそ
れぞれ従来のF―Vコンバータの構成図、第2B
図および第3B図は第2A図および第3A図の各
F―V特性を説明するための図である。 1…ワンシヨツトマルチ回路、R1…固定抵抗
、C…コンデンサ、2…積分回路、4…インバー
タ、TR…スイツチングトランジスタ、E…直流
電源、E…電源電圧、V…出力電圧。なお、図
中、同一符号は同一または相当部分を示す。
Figure 1A is a block diagram of an F-V converter according to an embodiment of this invention, Figure 1B is a diagram for explaining its F-V characteristics, and Figures 2A and 3A are conventional F-V converters. Configuration diagram, 2nd B
The figure and FIG. 3B are diagrams for explaining each FV characteristic of FIG. 2A and FIG. 3A. 1...One-shot multi-circuit, R1...Fixed resistance, C...Capacitor, 2...Integrator circuit, 4...Inverter, TR...Switching transistor, E...DC power supply, E0 ...Power supply voltage, V...Output voltage. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 周波数の可変な入力パルスを加えることにより
トリガされるワンシヨツトマルチ回路と、このワ
ンシヨツトマルチ回路からの出力パルスを積分す
る積分回路とを備えた周波数―電圧変換回路にお
いて、上記ワンシヨツトマルチ回路と積分回路と
の間に、ワンシヨツトマルチ回路からの出力パル
ス信号によりオンオフされるスイツチング素子と
電圧可変の直流電源とからなるインバータを介挿
し、上記直流電源の電源電圧を可変制御すること
により、入力周波数の変化に対応させて積分回路
の出力電圧を可変制御するように構成したことを
特徴とする周波数―電圧変換回路。
A frequency-voltage conversion circuit comprising a one-shot multi-circuit that is triggered by applying an input pulse with a variable frequency and an integrating circuit that integrates the output pulse from the one-shot multi-circuit. An inverter consisting of a switching element that is turned on and off by the output pulse signal from the one-shot multi-circuit and a DC power source with variable voltage is inserted between the integrating circuit and the input voltage of the DC power source is variably controlled. A frequency-voltage conversion circuit characterized in that it is configured to variably control the output voltage of an integrating circuit in response to changes in frequency.
JP15315587U 1987-10-05 1987-10-05 Pending JPH0158175U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15315587U JPH0158175U (en) 1987-10-05 1987-10-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15315587U JPH0158175U (en) 1987-10-05 1987-10-05

Publications (1)

Publication Number Publication Date
JPH0158175U true JPH0158175U (en) 1989-04-11

Family

ID=31428738

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15315587U Pending JPH0158175U (en) 1987-10-05 1987-10-05

Country Status (1)

Country Link
JP (1) JPH0158175U (en)

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