JPH0154740B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a parallel reasoning computer, and increases the number of processor elements that can operate simultaneously by reducing the frequency of passing goals between each processor element. Regarding the distribution method of goals.

[Background of the Invention] Conventional inference computers generally perform inference processing sequentially. The typical processing method is
“Research report from the Department of Artificial Intelligence, University of Edinburgh (Dept.of
Artificial Intelligence Research Report) No. 39
No. 40 (1977). Such sequential inference calculations have the problem of low processing performance because each inference process is executed sequentially by a single processor. Generally, multiple new goals are derived from inference processing of one goal, and these new goals can be processed in parallel. Focusing on this point, for example, ``International Conference on Fifth Generation Computer Systems (1984), Proc. of Int.Conf, on Fifth Generation
Computer Systems1984, ICOT), pp. 479-No.
489 page" (publicly known example), multiple processors and
Parallel inference computers have been proposed to improve processing performance by connecting elements through a network and executing multiple inference processes in parallel.

There are two issues facing parallel reasoning computers:

(1) Distribute inference processing to as many processor elements as possible and increase the number of processor elements that operate in parallel.

(2) Efficiently distribute goals in a network with small throughput.

(1) and (2) are not unrelated, and the network throughput is practically limited to a certain value, so
In order to achieve (1), it is essential to overcome the issue (2).

Now, in conventional parallel reasoning computers, for example,
As shown in the known examples, each processor
An element pools new goals derived as a result of processing a single goal (called a goal pool)
was sent to. Each processor element accesses the goal pool to retrieve goals and perform inference processing. For this reason, the processor
Communication between each processor element via the goal pool is required for each inference process in an element, and if the network throughput is insufficient, processors that can perform parallel processing are required.
The number of elements is limited.

In addition, Information Processing Society of Japan 30th National Conference Proceedings 6C
-9 (p.201) (publicly known example), east, west,
It connects with the south and north processor elements to form a net-like network, and generates a new goal from the processor element that generated it (called its own processor element) → east processor element → south processor element → There is also a conventional example in which the required network throughput is kept low by sequentially distributing the self-processor element and so on. In the known example, the required network throughput is kept low by introducing a mesh network with four-neighbor connections, but a throughput of ~1 Gb/sec is required, and in a normal network, parallel operation is not possible. The number of processors to be used could not be increased sufficiently.

[Purpose of the invention]

An object of the present invention is to provide a goal distribution method that can reduce the frequency of communication between processor elements via a network, and to realize a high-performance parallel reasoning computer.

[Summary of the invention]

The number of new goals generated as a result of goal processing by the processor element is usually one or two, and often only one. Therefore, if the generated new goal is the goal for the next processing of the processor element that has processed it, there is no need to transfer the goal to another processor element via the network.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail. For example, a parallel reasoning computer can execute a program written in a language called Prolog based on first-order predicate logic.

The grammar, programming methods, and program examples of Prolog are described in textbooks such as Hideyuki Nakajima's ``Prolog'' (Sangyo Tosho). FIG. 2 shows an example of such a prolog program. The first line of Figure 2 is a question that reads, ``What does Hanako like?''
The second line describes the rule and reads, "X likes Y means that X is Z's child and Z likes Y." Lines 3 to 7 describe the facts.

The program in FIG. 2 is executed as follows.
Comparing the question in the first line with the facts in lines 3 to 7, I found no facts about Hanako, so I answered the question in the second line.
Apply row rules. As a result, the question in the first line is “Children (Hanako, Z), likes (Z, Y)”, that is,
"Hanako is someone's child, and what does this someone like?"
replaced by the question. The question in the first line is called the goal. Next, the new question (goal) resulting from the substitution is compared with the facts in lines 3 to 7 of Figure 2, and is compared to the facts in lines 3 to 7 of Figure 2. is Taro's child, and Taro likes baseball.'' and ``Children (Hanako, Kazuko), likes (Kazuko, Hon)'' are obtained. From the first result, “I like (Hanako, baseball)”, and from the second result, “I like (Hanako, books)”
is obtained.

An embodiment of the invention is shown in FIG. The goal corresponding to the first question, “Like (Hanako, A)” is passed to Processor Element #0 and processed, resulting in “Child (Hanako, Taro), Like (Taro, Y)” and “Child (Hanako, Y)”. , Kazuko) and ``Like (Kazuko, Y)'' are generated. Of these two new goals, only the first goal is passed to the goal pool, and the second goal is processed by processor element #0. The first goal passed to the goal pool is passed to #n, one of the waiting processor elements, and processed. Programs and data for processing all of the goals that can be processed by the system are stored in a memory location (not shown) common to the system, which each processor accesses as appropriate.

In this embodiment, the transfer of new goals from the processor element to the goal pool and the transfer of new goals from the goal pool to the processor element, which were performed twice in the case of the known example, can be reduced to one each. . As a result, the frequency of use of the network is reduced from five times in the known example to three times, so that more processor elements can be operated in parallel.

In the known example, each time a new goal occurs, the process is executed as follows: own processor element → east processor element → south processor element → own processor element.
Since the distribution destination is changed cyclically with the elements,
Only 1/3 of the new goals generated can be confined to the own processor. In other words, the frequency of network usage can be reduced by at most two-thirds. In the present invention, at least one new goal is distributed to the own processor for each inference process, so a higher goal confinement rate can be obtained. In particular, when only one or two new goals are generated from one inference process, the difference from the known example becomes large and it is effective.

〔Effect of the invention〕

In the example of FIG. 1, the result was obtained after two goal processes, but normally ten or more goal processes are required before a result is obtained. In the present invention, one of the new goals generated as a result of goal processing is
Confines the goal to the processor element that executed the goal processing without sending it to the goal pool via the network. Therefore, according to the present invention, the frequency of use of the network can be reduced to about one-tenth of that in the conventional case, which has the effect of increasing the performance of the parallel inference computer by ten times.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing the transfer of goals between processor elements, and FIG. 2 is an example of a prolog program. A, X, Y, and X in FIG. 2 and FIG. 1 represent variables.

Claims (1)

[Claims] 1 Consists of multiple processor elements, each processor element processes a separate goal at the same time, and passes a new goal generated as a result of the goal processing to other processor elements through communication between each processor element. , in a parallel inference computer in which the processor element next performs the goal processing, for each goal processing, one of the new goals generated as a result is distributed to the processor element that executed the goal processing, Transfer the remaining new goals to other processors.
A goal distribution method in a parallel reasoning computer characterized by distribution to elements.