JPH0152734B2 - - Google Patents

Info

Publication number
JPH0152734B2
JPH0152734B2 JP13586080A JP13586080A JPH0152734B2 JP H0152734 B2 JPH0152734 B2 JP H0152734B2 JP 13586080 A JP13586080 A JP 13586080A JP 13586080 A JP13586080 A JP 13586080A JP H0152734 B2 JPH0152734 B2 JP H0152734B2
Authority
JP
Japan
Prior art keywords
substrate
liquid crystal
rubbed
electrode
common terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13586080A
Other languages
Japanese (ja)
Other versions
JPS5762026A (en
Inventor
Shigeru Hatori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13586080A priority Critical patent/JPS5762026A/en
Publication of JPS5762026A publication Critical patent/JPS5762026A/en
Publication of JPH0152734B2 publication Critical patent/JPH0152734B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1337Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • G02F1/13378Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation
    • G02F1/133784Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by treatment of the surface, e.g. embossing, rubbing or light irradiation by rubbing

Description

【発明の詳細な説明】 本発明は液晶素子の製造方法、特に基板のラビ
ング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a liquid crystal device, and particularly to a method for rubbing a substrate.

液晶分子の配向処理手法としては、ラビング
法、SiOまたはAuの斜め蒸着法、イオンビーム
による斜めエツチング等の手法が用いられるが、
本発明はラビング法による場合を対象とする。
As methods for aligning liquid crystal molecules, methods such as rubbing, oblique evaporation of SiO or Au, and oblique etching using an ion beam are used.
The present invention is directed to a case using a rubbing method.

第1図は従来の手法によるラビング法の説明図
である。下板基板1には電極パターン2および上
板基板と電気的な接続をとるためのコモン端子3
が形成されている。下板基板1の上に斜線で示す
金属製マスク4を重ねラビングを行ない配向処理
を行なう。この状態でラビングを行なうと基板表
面に静電気が発生し、コモン端子3が形成されて
いない右端電極パターンと金属マスク4との隙間
5にゴミが付着する。または隙間5に静電気のス
パークが発生することがある。これらの結果、界
面の汚染または破壊により局部的に液晶分子の配
列が乱れ配向しない現象を起す結果となる。
FIG. 1 is an explanatory diagram of a conventional rubbing method. The lower substrate 1 has an electrode pattern 2 and a common terminal 3 for electrical connection with the upper substrate.
is formed. A metal mask 4 shown by diagonal lines is placed on the lower substrate 1, and rubbing is performed to perform alignment processing. If rubbing is performed in this state, static electricity will be generated on the substrate surface, and dust will adhere to the gap 5 between the right end electrode pattern where the common terminal 3 is not formed and the metal mask 4. Alternatively, static electricity sparks may occur in the gap 5. As a result, the alignment of liquid crystal molecules is locally disturbed due to contamination or destruction of the interface, resulting in a phenomenon in which the liquid crystal molecules are not oriented.

本発明は上記従来技術の欠点を解消した液晶表
示素子を提供することを目的とする。
An object of the present invention is to provide a liquid crystal display element that eliminates the drawbacks of the above-mentioned prior art.

以下、本発明を図示の実施例により説明する。
第2図はスタテイツク型の素子に適用した例を、
第3図は時分割型の素子に適用した例を示す。同
図に示すように、ソケツトと直接接触しない下板
電極面の内、コモン端子3と反対側の電極パター
ン2と電気的に接続されているダミーリード6を
設ける。ダミーリード6は下板基板1の端面まで
形成されており、ラビングを行なう場合、マスク
4と接触する。この場合ダミーリード6は1本で
も複数本設けても良い。
Hereinafter, the present invention will be explained with reference to illustrated embodiments.
Figure 2 shows an example applied to a static type element.
FIG. 3 shows an example applied to a time division type element. As shown in the figure, a dummy lead 6 is provided which is electrically connected to the electrode pattern 2 on the side opposite to the common terminal 3 on the lower plate electrode surface that does not come into direct contact with the socket. The dummy leads 6 are formed up to the end surface of the lower substrate 1, and come into contact with the mask 4 when rubbing is performed. In this case, one or more dummy leads 6 may be provided.

以上の説明から明らかな如く、ダミーリード6
を設け、このダミーリード6とコモン端子3の双
方に接触するとともにラビングすべき面に対応し
た開口部を備えた導電性のマスク4を重ねた基板
面をラビングすることにより、静電気が発生して
も、マスク4により電極パターン2の両サイドが
通されて電位差が少なくなつているので、スパー
クの発生を防止でき配向特性が改善される。
As is clear from the above explanation, dummy lead 6
Static electricity is generated by rubbing the surface of the board overlaid with a conductive mask 4 that contacts both the dummy leads 6 and the common terminal 3 and has an opening corresponding to the surface to be rubbed. Also, since both sides of the electrode pattern 2 are passed through the mask 4 and the potential difference is reduced, generation of sparks can be prevented and the alignment characteristics can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の素子の下板電極パターンとマス
クとの関係を表わす平面図、第2図、第3図はそ
れぞれ本発明の実施例を示す平面図である。 1……下板基板、2……電極パターン、3……
コモン端子、4……枠マスク、5……隙間、6…
…ダミーリード。
FIG. 1 is a plan view showing the relationship between the lower plate electrode pattern and the mask of a conventional element, and FIGS. 2 and 3 are plan views showing embodiments of the present invention, respectively. 1... Lower board, 2... Electrode pattern, 3...
Common terminal, 4...Frame mask, 5...Gap, 6...
...Dummy lead.

Claims (1)

【特許請求の範囲】[Claims] 1 対向する内面をラビング処理した一対の基板
間に液晶を挟持してなる液晶表示素子の製造方法
において、ソケツトと直接接触しない一方の基板
の電極の、該電極を他方の基板の電極へ導通をと
るために設けられているコモン端子と反対側の位
置に、前記一方の基板の電極に電気的に接続さ
れ、かつ前記一方の基板のほぼ外形位置まで延在
するダミーリードを設け、前記一方の基板上に、
前記コモン端子および前記ダミーリードの双方に
接触するとともにこの基板のラビングすべき面に
対応した開口部を備える導電性のマスクを重ね
て、前記一方の基板上をラビングすることを特徴
とする液晶表示素子の製造方法。
1. In a method of manufacturing a liquid crystal display element in which a liquid crystal is sandwiched between a pair of substrates whose inner surfaces facing each other are rubbed, conduction is established between an electrode of one substrate that does not come into direct contact with a socket and an electrode of the other substrate. A dummy lead electrically connected to the electrode of the one substrate and extending almost to the outer shape of the one substrate is provided at a position opposite to the common terminal provided for the connection. on the board,
A liquid crystal display characterized in that the one substrate is rubbed by overlapping a conductive mask that contacts both the common terminal and the dummy lead and has an opening corresponding to the surface of the substrate to be rubbed. Method of manufacturing elements.
JP13586080A 1980-10-01 1980-10-01 Liquid crystal display element Granted JPS5762026A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13586080A JPS5762026A (en) 1980-10-01 1980-10-01 Liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13586080A JPS5762026A (en) 1980-10-01 1980-10-01 Liquid crystal display element

Publications (2)

Publication Number Publication Date
JPS5762026A JPS5762026A (en) 1982-04-14
JPH0152734B2 true JPH0152734B2 (en) 1989-11-09

Family

ID=15161450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13586080A Granted JPS5762026A (en) 1980-10-01 1980-10-01 Liquid crystal display element

Country Status (1)

Country Link
JP (1) JPS5762026A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0727138B2 (en) * 1986-01-16 1995-03-29 日本電装株式会社 Liquid crystal display element manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54141155A (en) * 1978-04-25 1979-11-02 Sharp Corp Production of liquid crystal cell
JPS5570818A (en) * 1978-11-22 1980-05-28 Hitachi Ltd Liquid crystal display element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54141155A (en) * 1978-04-25 1979-11-02 Sharp Corp Production of liquid crystal cell
JPS5570818A (en) * 1978-11-22 1980-05-28 Hitachi Ltd Liquid crystal display element

Also Published As

Publication number Publication date
JPS5762026A (en) 1982-04-14

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