JPH01500477A - Reset and synchronization interface circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] This invention relates generally to interface circuits for use in telecommunications systems. In particular, the integrated services digital network (ISDN) S interface Reset for use in subscriber power controller integrated circuits that provide power across It concerns the circuit and synchronization interface circuit.

In the field of telecommunications, the operation of digital signals in transmitting information over long distances The use of technology covers a wide range of communications, including voice, computer data and video data. It is becoming more and more obvious due to faith. Typically, the International Telegraph and Telephone Advisory Committee S-interface as cited by the CCI TT The subscriber line interface connects the 15DN terminal equipment to a private branch exchange facility (PBX). ) used to interconnect one or more network termination devices, such as

For integrated circuits in 15DN terminal equipment such as telephones or data generating equipment. Stable, regulated 5 volts to 40 volts delivered via S interface to A subscriber power controller (SPC) is used to convert to a power source. like that The power controller is manufactured by California Sunni under the part number designated Am7936. - Veil's Advanced φ Micro Devices Incorporated ( Manufactured by Advanced Micro Devices, Inc. One is on sale. The subscriber power controller is an integrated device formed in a single chip package. circuit, and one of its capabilities is to detect low voltage and allow digital subscribers to Reset controllers, microprocessors, and other integrated circuits in their terminal equipment. and synchronize the internal free-running oscillator for use with other integrated circuits in the terminal. be synchronized with an external clock signal in order to

The reset and synchronization interface circuit of this invention is integrated into the same subscriber power controller collection. provided as part of the product circuit to perform such reset and synchronization functions. Applying a reset signal to other integrated circuits in the terminal equipment further causes intermodulation hum. Try to remove noise interference. This result is calculated by the first comparator, the second comparator and and a reset means for generating a reset signal formed from an inverting network and a third ratio. Synchronization for generating modified synchronization signals formed from comparators and logic gates This is achieved by providing means.

Summary of the invention In a preferred embodiment of the invention, a reset for use in a subscriber power controller is provided. reset and synchronous interface circuits to generate a reset signal. and synchronization means for generating a modified synchronization signal. The reset means It is formed from first comparator means, second comparator means, and circuitry means. synchronization The means are formed from third comparator means and an AND logic gate. first comparator The means are formed from a first comparator with hysteresis to convert the input signal into a reference signal. to produce a first output signal and a second output signal. The second comparator means is a second comparator that connects the first output signal from the first comparator to a reference voltage; A comparison is made and a third output signal is generated. The network means responds to the third signal to 3 and shifts the level of the output signal of No. 3 to produce a reset signal.

The third comparator means is formed from a third comparator for inverting the synchronization pulse; Generates complementary sync pulses. The AND logic gate outputs the second output from the first comparator. The invention creates a modified synchronization signal by logically combining the signal with complementary synchronization pulses. , read in conjunction with the accompanying drawings in which like reference numbers indicate corresponding parts throughout. will be better understood from the following detailed description.

FIG. 1 shows a digital diagram for communication across an S interface according to the invention. 1 is an overall block diagram of an integrated service network.

FIG. 2 shows a reset circuit of the present invention for use in the subscriber power controller block of FIG. FIG. 2 is a block diagram of a synchronous interface circuit.

FIG. 3 is a detailed schematic diagram of the various blocks of FIG.

Description of the preferred embodiment Referring now to the drawings in detail, the terminal equipment 2 may be configured as a private branch exchange facility (PBX). The S interface, that is, the subscriber interface, connected to the network termination device 3 The overall block of Integrated Services Digital Network (ISDN) for communications across A diagram is shown in FIG. The terminal equipment 2 is a digital subscriber controller 5, a micro It includes a processor 6 and a subscriber power controller 7. As explained earlier, subscribers The power controller connects the 40 volts delivered to the S interface to the l5DN terminal equipment. An integrated circuit that converts a stable, regulated 5 volt power supply for other chips in the be. As part of the same subscriber power controller integrated circuit or chip 7, When detecting the pressure, the digital subscriber controller 5, the microprocessor 6 and its end Reset the other integrated circuits of the terminal device 2 and synchronize the internal free-running oscillator to restart the terminal. Can be synchronized to an external clock signal for use with other integrated circuits in the device A reset and synchronization circuit 10 is provided which functions to perform the same function.

More detailed blocks of the reset and synchronization interface circuit 10 of the present invention The diagram is illustrated in FIG. Interface circuit 10 is reset circuit part 1 2 and a synchronous circuit part 14. The reset circuit section 12 is the first comparison 16, a second comparator 18, and an output network 20. Synchronous circuit part 14 includes a third comparator 22 and an AND logic gate 24.

The first comparator 16 has its inverting input connected to an input terminal 26, typically 2. A reference signal REF/I is received which is 5 volts DC. Non-inverting of the first comparator 16 The input is connected to input terminal 28 to connect the DAMP block (shown) at the subscriber power controller. receives an input signal R1/I obtained from Comparator 16 is line 3 A first output signal R★ on Connected to input. The second output signal of comparator 16 on line 32 is the second output signal of comparator 16 on line 32. 18 and one end of capacitor 34. Comparator 18 The 0 inverting input is also connected to the reference signal REF/I. typically 5.08 volts The low power supply V1/1, which is Given. Ground potential GND/l is connected to comparator 16 via lines 38 and 40. and 18. The second end of capacitor 34 is also connected to ground potential GND/I connected to. The output of comparator 18 on line 42 is the input of output network 20. sent to. The output of network 20 on line 44 is a reset consisting of positive pulses. digital subscriber controller 5, microprocessor 6 and its Other integrated circuits of the terminal device 2 are reset. Positive supply voltage VL/I and negative voltage The source voltage vON/I is connected to the network 20 by lines 46 and 48, respectively. Continued.

The third comparator 22 has its inverting input connected to the input terminal 50, typically 19 Receive a synchronous clock signal operating at a frequency of 2kHz. Non-inverting of comparator 22 Input via diode D2, resistor R1, diode D1 and line 52 connected to the positive power supply voltage VL/I, and diode D3, diode D4, and resistor VON/I via line 54 and VON/I. Masaoyo The negative and negative supply voltages are also connected to comparator 2'2 via respective lines 56 and 58. Connected. The output signal SYN★ from comparator 22 on line 60 is synchronization signal SY It is the complement of N/I and is sent to the second input of logic gate 24. mentioned earlier , the first input to logic gate 24 is signal R★. This signal R★ is the output It is the complement of the reset signal R at terminal 45. Each output from logic gate 24 Modified synchronous output signals SRA/I and SRB/I at power terminals 62 and 64 operates according to the truth table and pool formula shown below.

(Margin below) R* SYN* SRA/I or SRB/l5RA/l-R★, SYN★ comparators 16.18 and 22 of the reset and synchronization interface circuit 10; A detailed schematic diagram of the output network 20 and logic gate 24 is shown in FIG. 3 of the drawings. is shown. As can be seen, in the reset circuit portion 12, the first comparison The transistor Q9.1 pair of transistors Q4 and 16 provide the base current. and Q5, transistors Q1 and Q5 acting as active loads. and a resistor-biased current mirror formed from transistor Q 3, and a current mirror formed from transistors Q6 and Q7. input Reference signal REF/I at terminal 26 is applied to the base of transistor Q4, and Input signal RI/I on input terminal 28 is applied to the base of transistor Q5. . The first output of comparator 16 is a transistor connected to the collector of transistor Q8. It is located at the emitter of star Q7. The second output of comparator 16 is connected to the collector of transistor Q6. Located in Kuta.

Normally the input signal RI/I will be higher than the reference signal REF/I. to this As a result, transistors Q5, Q2 and Q3 are turned off. In this way, the transition The first output at the emitter of star Q7 will be high. Therefore, in bin 2 Connectable external capacitor 34 is enabled to be charged from current source IC8 . Capacitor 34 determines the width of the reset pulse. Furthermore, transistor Q6 The output at the collector of will also be high to enable logic gates 24.

On the other hand, when the input signal RI/I becomes lower than the reference voltage REF/1, the transistor Q 5, Q2 and Q3 are made conductive so that the output at the emitter of transistor Q7 power will be low. Therefore, capacitor 34 is allowed to discharge. be done. Furthermore, the output at the collector of transistor Q6 also becomes low, and the AND logic It will disable gate 24.

A second comparator 18 is of similar construction to that of comparator 16 and provides a bias current. transistor Q17.1 from a pair of transistors Q12 and Q13. from transistors Q14 and Q15 acting as active loads. A resistor biased current mirror formed and transistor Q16 including. The reference signal REF/I is applied to the base of transistor Q12, and the comparator The first output of 16 is applied to the base of transistor Q13. Output of comparator 18 Power is received at the collector of transistor Q16. Base of transistor Q1B The non-inverting input of comparator 18 corresponding to will be charged. Therefore, the output of comparator 18 will normally be at a high voltage level. It will be. Capacitor 34 connected to the non-inverting input of comparator 18 is discharged. When the output is turned on, the output will change to a low voltage level.

Output circuitry 20 functions to halve and shift the level of the output of comparator 18. do. Network 20 includes current source transistor Q23, transistor Q18 and and a current mirror formed from transistors Q22, Q21 and includes a class B push-pull output stage formed from Q20. Usually, comparator 18 When the output of Q19 is at a high voltage level, transistor Q19 is conductive and the transistor Q19 is conductive. This will cause current to sink through resistor Q20.

Thus, the reset signal at the connection of the emitters of transistors Q21 and Q20 No. R will be at a low voltage level.

When the output of comparator 18 changes to a low voltage level, transistor Q19 is turned off. , the current supply would be via transistor Q21. Therefore, the net The output of network 20 is connected to digital subscriber controller 5, microprocessor 6 and A positive pulse that is a reset signal R for resetting other integrated circuits of the terminal device 2 will be switched to a high voltage level correspondingly.

In the synchronous circuit section 14, the comparator 22 is a transistor for providing a bias current. Q28. A differential amplifier formed from a pair of transistors Q29 and Q30, or and diode-connected transistors Q24 to Q27. as string and resistors R1 and R2. No transistor Q24 Q27 corresponds to the respective diode connection D4 of FIG. Comparator 2 The non-inverting input of Q2 corresponds to the base of transistor Q29 and is connected to the bias string is connected to the connection point of diode-connected transistors Q25 and Q26. . The inverting input is connected to input terminal 50 to receive the synchronized clock signal SYN/I. This corresponds to the base of transistor Q30. The output of comparator 22 connects line 60 to The transistor Q30 is connected to the second input of the AND logic gate 24 through the It's in Rector.

AND logic gate 24 connects a pair of transistors Q40 and Q36, a current source transistor Differential amplifier with transistor Q35 and emitter follower transistor Q37 It includes an ECL gate circuit formed from. The complement of the reset signal R is the emitter photo. The complement of the synchronizing signal SYN/I is applied to the base of the lower transistor Q37. It is applied to the base of resistor Q40. The modified synchronization signal SRA/I A modified synchronization signal comes from the first emitter of follower transistor Q37. SRB/I comes from the second emitter of transistor Q37.

The input signal RI/I to the comparator 16 is lower than the normal operating condition reference voltage REF/I. When high, transistor Q6 of comparator 16 is turned off and therefore the complementary reset The cut signal R★ will be at a high voltage level. Therefore, the modified synchronous output signal The signals SRA/I and SRB/1 can be controlled by the complement of the synchronization signal SYN/I. Probably. However, the input signal R1/I to the comparator 16 is is lower than the reference voltage REF/I representing Causes the complementary synchronization signal R★ to go to a low voltage level, thereby causing the complementary synchronization The output of logic gate 24 is held low regardless of signal SYN★. Ru. In other words, the AND logic gate has synchronization signal SYN/I at output terminal 62 and and 64.

From the above detailed description, it can be seen that the present invention thus provides a reset signal for generating a reset signal. and synchronization means for generating a modified synchronization signal. provide a reset and synchronization interface circuit for use with I understand. The reset signal is a positive signal generated when the input signal is lower than the reference voltage. It's a pulse. At the same time, the modified synchronization signal will be in a disabled state .

In addition, it can also provide a reset signal to other integrated circuits in the terminal equipment and cause intermodulation hum. Required for use in subscriber power controller equipment to eliminate noise interference. A method is provided for generating a set signal and a synchronization signal.

What is presently believed to be the preferred embodiment of the invention is illustrated and described. While the invention has been described, various changes and modifications may be made thereto without departing from the true scope of the invention. Modifications may be made and equivalents may be used in place of elements thereof. will be understood by those skilled in the art. Further, the teachings of this invention include its central scope. Many modifications may be made to suit particular situations or materials without departing from the obtain. Therefore, this invention is the best mode contemplated for carrying out this invention. Although not limited to the particular embodiments disclosed as is intended to include all embodiments falling within the scope of .

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Claims (17)

[Claims] 1. Reset and circuit synchronization interface for use in subscriber power controllers a first comparator means, a second comparator means, and a reset circuit at a first node; circuitry means for generating a set signal; The first comparator means is formed from a first comparator with hysteresis, comparing the force signal to a reference voltage to produce a first output signal and a second output signal; comparator means are formed from the second comparator to output the first output signal from the first comparator. comparing the signal to a reference voltage to produce a third output signal; said network means responsive to a third signal to invert the level of a third output signal; and shifted to produce a reset signal; a synchronous signal modified at the second node including third comparator means and an AND logic gate; including synchronization means for generating a signal; Said third comparator means receives a signal from the third comparator for inverting the synchronized clock signal. is used to generate complementary synchronous clock signals, and The logic gate converts the second output signal from the first comparator into a complementary synchronous clock signal. Reset and circuit synchronization that is logically combined with the signal to produce a modified synchronization signal interface circuit. 2. 1, wherein the first comparator has its base connected to the input signal and the reference voltage; Claim 1 comprising a first differential amplifier formed from a pair of transistors. Reset and synchronization interface circuit as described. 3. The second comparator has its base connected to the output of the first comparator and a reference voltage. The claim includes a second differential amplifier formed from a pair of transistors connected together. 2. The reset and synchronization interface circuit according to paragraph 2. 4. The network means comprises a current mirror arrangement and a push-pull output stage. The reset and synchronization interface circuit according to claim 3. 5. The third comparator has its base connected to a synchronized clock signal and a bias voltage. Claims include a third differential amplifier formed from a pair of transistors. Reset and synchronization interface circuit according to clause 4. 6. The AND logic gate connects the input transistor, the reference transistor, and the current A reset according to claim 5, including an ECL circuit formed from a source; Synchronous interface circuit. 7. The reset signal is typically at a low voltage level and is lower than a reference voltage. The voltage level of claim 1 changes to a higher voltage level corresponding to a positive pulse in response to an input signal. Reset and synchronization interface circuit according to paragraph 1. 8. The second output signal from the first comparator is configured such that the synchronized clock signal is a second output signal. AND logic when there is a low voltage detected that prevents it from reaching the output node. claim is the complement of the reset signal used to disable the control gate. Reset and synchronization interface circuit according to clause 7. 9. S-interface as used by integrated circuits in ISDN terminal equipment. To subscriber power controller equipment for converting high voltage to stable, regulated low voltage wherein the controller device includes a digital subscriber controller, a microprocessor and a digital subscriber controller; For resetting other integrated circuits of the terminal equipment and synchronizing the internal free-running oscillator reset and synchronization with external clock signals in other integrated circuits. and synchronization means, said reset and synchronization means comprising a first comparator means and a second comparator means. and network means for generating a reset signal at the first node. including a reset means including; The first comparator means is formed from a first comparator with hysteresis, comparing the force signal to a reference voltage to produce a first output signal and a second output signal; A second comparator means is formed from a second comparator and a first output from the first comparator. comparing the force signal to a reference voltage to produce a third output signal; said network means responsive to a third signal to invert the level of a third output signal; and shifted to produce a reset signal; a third comparator means and an AND logic gate, the synchronization being modified at the second node; including synchronization means for generating a signal; Said third comparator means receives a signal from a third comparator for inverting the synchronous clock signal. is used to generate complementary synchronous clock signals, and The logic gate converts the second output signal from the first comparator into a complementary synchronous clock signal. and the synchronization signal to produce a modified synchronization signal. 10. The reset and synchronization interface circuit according to claim 9 and the first comparator has its base connected to an input signal and a reference voltage. A first differential amplifier formed from a pair of transistors is included. 11. The reset and synchronization interface circuit according to claim 10 , the second comparator has its base connected to the output of the first comparator and a reference. A second differential amplifier formed from a pair of transistors connected to a voltage. 12. The reset and synchronization interface circuit according to claim 11. wherein the network means comprises a current mirror arrangement and a push-pull output stage. include. 13. The reset and synchronization interface circuit according to claim 12. The third comparator has its base connected to the synchronous clock signal and the bias voltage. A third differential amplifier formed from a pair of connected transistors is included. 14. The reset and synchronization interface circuit according to claim 13 wherein the AND logic gate has an input transistor, a reference transistor, and It includes an ECL circuit formed from a current source. 15. The reset and synchronization interface circuit according to claim 9 and the reset signal is typically at a low voltage level and lower than the reference voltage. It changes to a high voltage level corresponding to a positive pulse in response to an input signal. 16. The reset and synchronization interface circuit according to claim 15 The second output signal from the first comparator is a synchronized clock signal. AND when there is a low voltage detected to prevent reaching the output node of 2. It is the complement of the reset signal used to disable the logic gate. 17. Generates reset and synchronization signals for use in subscriber power controller equipment. a method for producing comparing the input voltage to a reference voltage to produce a first signal and a second signal; comparing the first signal to a reference voltage to produce a third signal; inverting and shifting the level of the third signal to produce a reset signal; inverting the synchronous clock signal to produce a complementary synchronous clock signal; The second signal and the complementary synchronous clock signal are logically combined to generate a reset signal complement. produces a modified synchronization signal only when the second signal corresponding to the signal is at a high voltage level. and a step of editing.