JPH01500227A - data conversion - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] data conversion 1; This invention relates to data conversion t, especially when a first unit converts n data and a second unit converts data into n data. A unit consists of two complementary units that perform the inverse of the transformation performed by one unit. It relates to the data conversion method performed in the equipment used.

The invention is defined in the claims appended hereto.

This should be referenced here.

Data conversion and apparatus embodying the invention may be used at the receiving end of a data transmission link. shall be used in the field of broadcasting, where converters are likely to be duplicated many times. is expected. therefore.

It is desirable that the second unit that performs the "inverse" conversion be made as simply and inexpensively as possible. Yes. Any consequential complications of transmission or forward conversion that result. I can accept it.

A simple and inexpensive "inverse" conversion device can be constructed using the data conversion method of the present invention. I can do it.

A data conversion method and apparatus according to the present invention will be described below by way of example with reference to a drawing. The first section of the drawing is a configuration diagram of the data conversion unit according to the present invention. the law of nature.

or FIG. 2 shows the configuration of a complementary data conversion unit that can be used with the unit of FIG. It is a diagram.

As mentioned above, the first and second data & exchange units are at the input end of the data transmission link. and should be used at the output end. As shown schematically in Figure 1 Unit 2 is designed to be used at the output end of the data link and is therefore Execute the data conversion process.

Unit 2 has an input data buffer 10, which is a three-way It is coupled by multiplexer 12 to the input of conversion input register 13 . system Control word register 11 is used to control the conversion performed by unit 2. It is meant to hold the control word for the next version (verge four) that will be released.

This register is also connected to the conversion input register 13 by multiplexer 12. can be done.

The conversion input register 13 supplies the bit permutation matrix 14, whose output is connected to eight identical permutation lookup tables 20 to 27. Ru. The output of lookup table 20 to 27 is connected to conversion output register 30, and this register The register is connected to the output data buffer 32 and changed through the multiplexer 12. It is connected to the conversion input register 13.

The input data buffer 10 receives data from a data link (not shown) 6 Holds a 4-bit input data block. The conversion input register 13 stores the arrived change. According to the stages of the conversion process, the input data buffer 10, the Jm word register 11 ．． Or one of the three sources of data that has been converted and output from the error 30. A block of 64-bit data is provided via a three-way multiplexer 12. . From the data link held in the input data buffer 10 at the time of opening the conversion process The received 64-bit incoming data block is applied to the conversion input register 13; and its output validates the 1-order of the data bits from the conversion input register 13. The bit permutation matrix 14 is added to the bit permutation matrix 14, which rearranges the bits.

The bit permutation matrix 14 includes, for each output bit, the bit permutation of the corresponding input bit. can be defined by a table that defines the number of cuts. Therefore 6 For a 4-bit block, this table contains 6406 bit numbers. conversion If the process is not to be a one-way function, the table will contain all possible 6-bit numbers (O to 63), and each value must appear only once in the 64 memory locations. No.

The output bits from bit permutation matrix 14 are then divided into groups of 8 bits, which and each group is an address input to one of eight identical permutation lookup tables 20 to 27. used. One lookup table for each 8 bits in the input data block There is.

Eight identical permutation lookup tables 20 to 27 each store 256 8-bit words. However, the selected output word is the 8 bits obtained from the bit permutation matrix 14. Depends on bit input address. If the required operating speed of the conversion process is low enough replaces the eight tables 20-27 with a single table and appropriate multiplexers be able to.

Search tables 20 to 27 are stored in the constant velocity discharge storage device, so the values of the items in table 1 are , can be converted as a function of the control word stored in the control word register 11. can. The initial values of the table items are obtained from the fixed storage device 31. Search table 2 during the conversion process Items in 0 to 27 are control variables as explained in more detail below. It has a value that depends on the code.

The eight output bits from each of lookup tables 20 to 27 are output to output conversion register 3. collected to 0. At the end of the conversion process the contents of register 30 are stored in the output data buffer 7. Transferred to 32. However, the conversion process requires bit permutation matrix 14 and This includes cycling the data block several times through the replacement lookup tables 20 to 27. It is designed to. Therefore, the 64-bit data held in the conversion output register 3° The data block is converted via a three-way multiplexer 12 at an intermediate stage in the conversion process. It is returned to the input register 13. The data block is from the input data buffer 10. The number of times the initial input is recirculated should be specified as a system parameter. and a single bit change in the input data block changes the output data block. to at least 8 to ensure that it cannot be correlated with bit changes in should. Preferably, a single bit change in the input data will on average 32 bits of output data should be changed.

The permutation search tables 20 to 27 contain all possible outputs so that the conversion function can have an inverse. force bit combinations appear and each such combination appears only once. Must. Tables 20 to 27 are therefore for addressable memory locations. Each of them includes 255 spits stochastically arranged. fixed mentioned above As such, the contents of lookup tables 20 to 27 during the conversion process are stored in control word register 11. , but nevertheless meet this requirement. Must do. This allows you to change the table contents through a series of storage location conversion operations. This is achieved by

Therefore, before unit 2 is used for the data transformation process, the permutation search table The contents of 20 to 27 are initially set as follows.

The control word from control word register 11 is converted into input by multiplexer 12. is supplied to the force register 13. At the same time, the basic Values are loaded from fixed storage 31 into the table. held in the control input register 13 The bits that make up one control block can be saved in the data conversion process itself. The changes are made by being passed through the bit permutation matrix 14 and the lookup tables 20 to 27. receive an exchange. The output from the conversion output register 3° is once via the multiplexer 12. The above data may be recirculated to the conversion input register 13. (Bit permutation matrix, 21 4 and the number of passes through search tables 20 to 27 are specified as system parameters. There is. ) After the specified number of passes, the contents of the 8 bytes in the conversion output register 3o are stored in the search table 2. Used to address four pairs of memory locations from 0 to 27.

The values in these paired memory locations are exchanged. of the values in the same pair of storage locations. Exchanges are carried out in all eight tables 20-27.

This process, i.e., bit permutation matrix 14 and lookup tables 20 to 270 The following four pairs of values are exchanged in memory locations for a specified number of times. This process is repeated until the exchange is completed. What you say is 256 exchanges, i.e. By specifying 64 sets of four exchanges, each set of exchanges requires 1, for example, 2 matrix 14 entries. The data in the search tables 20 to 27 may be passed through first. This is bi The cut permutation matrix 14 and permutation search tables 20 to 27 were used a total of 128 times. On average, 87% of table locations have their contents changed at least once. That means that.

Once the required number of storage location pairs have been exchanged, the initial settings of the search tables 20 to 27 are is completed and the data conversion itself can proceed. to input data buffer 10 The retained 64-bit input data block is converted by multiplexer 12. input register, 13, and bit permutation a specified number of times 1, e.g. 8 The matrix 14 and permutation search tables 20 to 27 are circulated to perform the required transformation. achieved.

In this way, the initial settings in the lookup tables 20 to 27, and therefore the output buffer 32 The ultimate content of is determined by the control word held in the control word register 11. be done.

As mentioned above, the conversion process performed by the data conversion unit 2 is a data link It is designed to be carried out at the receiving end.

The non-inverting or IE direction transformation at the transmitting end C (is deduced from the inverse transformation already described). Ru.

Complementary forward transform unit that can be used with transform unit 2 of Figure 1 4 is shown in FIG. The one-way conversion unit 4 has an input data backup 7a 4o. , which connects multiplexer 41 to conversion input register 42 by 7L. ing.

The output of the conversion input register 42 is added to eight −j substitution search tables 50 to 57. i, and their outputs are added to the bit permutation matrix 60. bit replacement Matrix 60 is coupled to a conversion output register 61, and this register outputs The conversion input register is connected to the data buffer 62 and is connected to the conversion input register by the multiplexer 41. 42.

The equipment provided at the transmitting end of the data link may also be similar to that shown in Figure 1. equipment but lacks any input from a data link or other external data source. can be included. This device is used as a pseudo-decoder during the initialization of the lookup table. be done.

Unit 2 in FIG. 1 uses the accumulated control word pit from the control word register 11. and operates as described above to initialize the values in lookup tables 20 to 27. be given At the same time, the pseudo-decoder device associated with the forward transform unit 4 in Fig. 2 is , to initialize the values in the same set of lookup tables using the same control word bits. It can be operated in order to The contents of the lookup table in the pseudo-decoder are then transformed into a forward transform unit. Used to generate the inverse value to be used in lookup tables 50 to 57 of cut 4. used.

Converting table values to be given as inverse values is easy. In the search table of the pseudo-decoder, the value y is If it appears in memory location then the value X is placed in memory location y. In Table 1, for all memory locations and do this, all the storage locations in table 2 will become (irregular with increasing values) fulfilled] in a certain order.

- Once initialized, the forward translation unit operates as follows.

Of the incoming data buffers 40 holding 64-bit blocks of input data. The value can be loaded into conversion input register 42 by multiplexer 41. conversion The output of input register 42 is divided into 8 groups of 8 bits, each of which has 8 groups of 8 bits. One of the same replacement search tables 50 to 57 is addressed. Search tables 50 to 57 are This is the reverse of the conversion lookup tables 20 to 27 in FIG. formed by the search table output Eight sets of 8 bits are supplied to the bits of FIG. Output of reverse bit placement matrix 60 The power is supplied to a % conversion output register 42 from which it is output to a multiplexer 41. through to the transform input register 42 and finally to the lookup tables 50 to 5. 7 and completes the number of passes through the bit conversion matrix 60. required number of times Once the pass is complete, the 64-bit block of output data is stored in the output data buffer. 62.

The control word is sent at predetermined intervals, e.g. at the end of each transmission or at the end of a specified number of data blocks. is converted after the transmission of the block. The control word is selected probabilistically, and the selected word The code may be sent by any suitably secure means such as by post, by the courier or separately. be transmitted between the input and output conversion units by a protected data link. Can be done.

It is anticipated that the method described will be realized by software algorithms. However, in that case, each drawing can be treated as an information flow diagram rather than a circuit configuration diagram. Ru.

Although the conversion process has been described in relation to 64-bit blocks, each block It will be appreciated that the number of bits in may be other than 64. however , the number of input and output data bits should be You must roll in exact multiples of the number added to the search table. Similarly, add to each search table. The number of bits added is approximately the number of bits added to the input and output data blocks. Any number other than 8 may be used as long as it is a number.

Input bits for partial use of input or output bits of a table or by two or more tables If the number of input bits added to one table is equal to the number of output bits from the table, If they are not the same, a one-way function will result.

This involves appropriate selection of the initial values of the lookup tables 20 to 27 and the bit arrangement matrix 14. This can be achieved by appropriate selection of the table that defines the . with one-way function Since the device does not have a reverse.

The units of FIG. 2 would be unrelated and impossible to construct.

As mentioned above, the control word has the same number of bits as the input and output data blocks. , but less than or equal to the length of the input and output blocks. Any length is fine. If a shorter control word is used, its length is With value 1, logical value O or any constant bit pattern! can be accomplished. ? l The 1tlJ control bit can appear at any position relative to the field of the input data block. can be done.

Finally, the number of iterations in the conversion process is determined by the initial settings of permutation search tables 20 to 27. The number of iterations and memory location pair exchanges can be refined as well. for example, The number of iterations between collocated memory location pair exchanges could be increased.

Input child-7 blow/7 Out n + - ri f +0,7 λ category''-7 ゛α-/7 已77 Riichifu Pro, 7 Procedural amendment □ October 2, 1988 Yoshi, Commissioner of the Patent Office 1) Takeshi Moon PCT/GB87100266 2. Name of the invention data conversion 3. Person who makes corrections Relationship to the incident: Applicant address Name British Broadcasting Corporation 4. Agent Address: Shin-Otemachi Building, 206-ku, 2-2-1 Otemachi, Chiyoda-ku, Tokyo 5. Date of amendment order: Dark day, September 27, 1986) As shown in the attached sheet (in addition, the above ( Submission of a translation of the written amendment that does not change the content of the document in 3) (Article 184-7 of the Patent Law December 229, 1988

Claims (18)

[Claims] 1. A permutation lookup table in which several groups of m data output bits are stored in multiple memory locations. Multiple groups of m cheater input bits are used as address inputs for the search The output bits held in each memory location in the lookup table are added to the control word added to the lookup table. A method of converting n data input bits into n data output bits, depending on the method. 2. The lookup table initially contains a predetermined group of m data bits and the control word is contained in the first block of n data input bits added to the lookup table and The content of the table is changed depending on the data bits output by it. The method described in Scope No. 1. 3. Multiple groups of data output bits held in the lookup table are output by the lookup table. as claimed in claim 2, wherein the data bits are rearranged in a manner determined by the data bits. Method. 4. Search where the reordering is determined by the data bit output output by the lookup table Swap groups of m data output bits held in one or more pairs of memory locations in a table 4. A method according to claim 3, which is achieved by: 5. The cheater output bits obtained from the lookup table are set at least once before each change in the lookup table contents. Any preceding one that is added to the input of the lookup table and recirculates this lookup table. A method according to claim 1. 6. A group of n data input bits are reordered before being added to the lookup table. A method as claimed in any one of the claims. 7. According to claim 6, the reordering is achieved by a bit permutation matrix. How to put it on. 8. 3. A method according to claim 2, wherein the control word comprises n bits. 9. The step of changing the contents of the lookup table and searching the data bits output by the lookup table Claim 5, wherein the step of recirculating through the lookup table is repeated a predetermined number of times. Method described. 10. received for transmission over a data transmission link and after transmission over this link Converts n data bits into n data output bits corresponding to n data input bits. In order to convert n data input pits into n data bits, The conversion process carried out at the receiving end of the link is in accordance with claim 1 and is The contents of the lookup table are determined and the input data bits are transformed into data bits for transmission. In the above method, an inverse search table is prepared that can be used when converting. 11. A plurality of groups of m data input bits each containing a group of m output bits. permutation lookup table with multiple memory locations addressable by changing the contents of the lookup table depending on the storage device and the stored control word; converting n data input bits into n data output bits, comprising: a device for converting n data input bits into n data output bits; equipment for. 12. Groups of m data bits initially supplied to multiple memory locations in the lookup table. a device for storing a control word, a device for adding a control word to an input of a lookup table, and A device for changing the contents of a lookup table depending on the data bits output by the lookup table. 12. The apparatus according to claim 11, comprising: a. 13. A device for changing the contents of the lookup table changes the number of groups of m data held in the lookup table. To rearrange the tabbits in a way that depends on the data pits output by the lookup table. 13. Apparatus according to claim 12, comprising a device for. 14. A device for reordering is maintained in one or more pairs of locations in the lookup table. Claim 1 comprising a device for exchanging a plurality of groups of m data bits. The device according to item 3. 15. The data bits output by the lookup table are added to the input of the lookup table and the bits are searched. The lookup table can be recirculated one or more times before each change made to the contents of the lookup table Any one of claims 11 to 14, comprising a device for The device described in one of the following. 16. for reordering a group of n data input bits before adding them to the lookup table. The apparatus according to any one of claims 11 to 15, comprising a device. Place. 17. Claim 16, wherein the device for reordering is a bit permutation matrix. Equipment described in Section. 18. Each lookup table consists of a set of m data bits selected from n data input bits. A claim that has multiple identical lookup tables with addressable storage locations. The apparatus according to any one of the ranges 12 to 18.