JPH0149950B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sound guessing training device which is suitable for music training for beginners and the like while enjoying a game by guessing randomly generated target sounds by pressing keys.

Generally, in music education for beginners, etc., it is preferable to add game-like elements so that they can naturally develop their pitch sense while having fun.

However, conventional electronic musical instruments lack game elements and are not suitable for music education for beginners.

An object of the present invention is to provide a new sound guessing training device that incorporates game-like elements in order to enhance the effectiveness of music education.

That is, the training device according to the present invention includes means for randomly generating a target sound, compares and determines the target sound data and key press data obtained by key press operations, and determines whether the key press is correct or incorrect. can be displayed using judgment sound effects.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows its configuration, which includes a keyboard circuit 11, in which the keyboard circuit 11 responds to key depressions on a keyboard section (not shown in the figure) and responds to pitches corresponding to the pitches of the operated keys. data (key data =
KD) is generated and this key data is OR circuit 1
4. Take out through the gate circuit 15 and further supply to the musical tone generation circuit 17 through the OR circuit 16,
A musical tone signal having a pitch corresponding to the key data is formed, and the speaker 18 is driven to express it as a performance sound.

Further, the key data is supplied to the key press detection circuit 12. The key press detection circuit 12 generates pitch data corresponding to the highest pitch of the pressed key in response to a key press detection command from the main control circuit 13, which will be described later. Corresponding to the end of the operation, a key press end (END) signal is supplied to the main control circuit 13.

Further, this device is provided with a target data generation circuit 19 consisting of a random number generation mechanism. The target data generation circuit 19 includes a pseudo-random code generation circuit 20 and generates target data as pitch data. It is supplied as judgment data B1 together with key data A1, and both input data A1 and B1 are compared and judged. Then, determination outputs such as "A1>B1", "A1<B1", "mismatch", "match", etc. are generated. This judgment operation in the judgment circuit 21 is executed based on a judgment command from the main control circuit 13.

The random code generation circuit 20 in the target data generation circuit 19 is composed of, for example, a shift register and an exclusive OR circuit, which is driven by a clock φ supplied through an AND circuit 23 whose gate is opened when the flip-flop circuit 22 is set. The flip-flop circuit 22 is composed of a T-type flip-flop to which the clock φ is supplied as a trigger signal, and supplies the target setting command from the main control circuit 13 to the J terminal.
Generates a set output in response to this type of setting command,
The random code generation circuit 20 is driven by counting.

Further, the output data corresponding to the target data from the random code generation circuit 20 is outputted to the comparison circuit 2.
4 as comparison data B. The comparison circuit 24 is supplied with lower limit data A and upper limit data C specifying the target data setting range from the grade designation switch circuit 25, and "A<
An output signal is generated from the comparator circuit 24 in the state of "B<C". The output signal from this comparison circuit 24 is
It is supplied to the K terminal of the flip-flop circuit 22 and reset to fix the output data from the random code generation circuit 20 to the output state at that time, and also supplied to the main control circuit 13 as a target setting end (END) signal. do. In this case, a command is given to the grade designation switch circuit 25 in response to a correct signal, which will be described later, and new grade ranges A and C are arbitrarily and variably set.

That is, the target data generation circuit 19 outputs target data that is randomly set within the grade range set by the grade designation switch circuit 25, and is supplied to the determination circuit 21. This target data is further supplied to the OR circuit 14 via the gate circuit 26 together with the key data from the key press detection circuit 12. In this case, the gate circuit 26 is opened by a signal from the one-shot circuit 27 to which a setting sound end (END) signal, which will be described later, is supplied, and the gate is opened for a time specified in the target setting end state, and the target data is A target sound having a pitch corresponding to the target sound is generated from the speaker 18.

The above-mentioned “A1>B1” from the determination circuit 21
The judgment output signals of “A1<B1” and “mismatch” are supplied to the incorrect answer processing circuit 28, and the judgment output signals of “match” are supplied to the correct answer processing circuit 29. This incorrect answer and correct answer processing circuit 28, 29
is further supplied with score data from the score processing circuit 30. This score data is obtained from an accumulator 31 of the score processing circuit 30, and this accumulator 31 is connected to the main control circuit 13. The score is preset to ``100 points'' by a score setting command from , and the subtraction data R ₀ (R ₀ =-30 in this case) set in the memory 32 is input.
Then, from the incorrect answer processing circuit 28,
When a signal corresponding to the determination is obtained, the accumulator 31 inputs the subtraction data from the memory 32, and sets the drive state (enable =
The score data of the accumulator 31 is further stored in a register 33 and displayed digitally on a score display 34 as appropriate. In this case, the register 33 is cleared by the score setting command, the load command LD is obtained by the score display command from the main control circuit 13, the data in the accumulator 31 is read and stored, and the score is displayed on the score display 34. Make it visible.

The incorrect answer and correct answer processing circuits 28 and 29 are configured as shown in FIG. 2, respectively, and are provided with memories 35 and 36, respectively.The memory 35 stores the disqualifying score data R1, and the memory 36 stores the passing score data R2. I remember each one. In this case, for example, "R1=20" and "R2=79". This memory 3
The data R1 and R2 from the accumulator 31 are supplied to comparison circuits 37 and 38 as comparison data A2 and A3, respectively. Data is provided as B2 and B3, respectively. The comparison circuit 37 generates comparison outputs of "A2<B2" and "A2>B2", and the comparison circuit 38 generates comparison outputs of "A3>B3" and "A3>B3", respectively. The comparison output of “A2<B2” is the AND circuit 3
9 and 40, the comparison output of "A2>B2" is supplied to an AND circuit 41, and the comparison outputs of "A3<B3" and "A3>B3" are supplied to AND circuits 42 and 43, respectively.

“A1>B1” and “A1<B1” from the determination circuit 21 are supplied to the incorrect answer processing circuit 28
The judgment output signals of are sent to AND circuits 39 and 4, respectively.
0 as a gate signal and also "mismatch"
The determination output signal is supplied to the OR circuit 44. The output signal from this OR circuit 44 is differentiated by a differentiating circuit 45, and the differentiated pulse is supplied to a counter 46 as a count signal. generate a signal. The count output of "1" from the decoder 47 is supplied to the score processing circuit 30 described above as a drive command EN to the accumulator 31 as a mismatch signal, and is also supplied to the OR circuit 44 via the OR circuit 48. The counter 46 is incremented. Further, the output signal of the count value "2" of the decoder 47 is supplied as a gate signal to the AND circuits 39 to 41, respectively, and the output signal of the count value "3" is
The signal is supplied to the OR circuit 48, and is also output as an incorrect answer signal and supplied to the main control circuit 13. and,
The output signal of the count value "4" is sent to the OR circuit 50 along with a disqualification signal from the effect data generation circuit 49, which will be described later.
The output signal of the OR circuit 50 resets the counter 46 and sets its count value to "0". Here, from the AND circuits 39 and 40,
It generates upper and lower signals indicating the mismatch direction of the upper side (treble side) and lower side (lower side) with respect to the target sound, respectively, and outputs a disqualification signal from the AND circuit 41, and these signals are sent to the effect data generation circuit 4.
Supply to 9.

In the correct answer processing circuit 29, the "coincidence" determination signal from the determination circuit 21 is supplied to an OR circuit 51, and the output signal of this OR circuit 51 is differentiated by a differentiation circuit 52 and counted by a counter 53. The count value data of the counter 53 is taken out as an output signal of "0" to "3" by a decoder 54, and the output signal of "1" of the decoder 54 is supplied to the effect data generation circuit 49 as a correct command. Further, the output signal of "2" from the decoder 54 is supplied to the AND circuits 42 and 43 as a gate signal, and the output signal of "3" is similarly outputted as a correct signal while resetting the counter 53 to "0". A grade change command is given to the grade designation switch circuit 25 and is also supplied to the main control circuit 13. The output signal from the AND circuit 42 is supplied to the effect data generation circuit 49 as a correct answer score content signal, and the output signal from the AND circuit 43 is supplied to the OR circuit 55 together with the correct answer/pass signal from the effect data generation circuit 49. The signal is supplied to the OR circuit 51 through the circuit 51, and the counter 53 is incremented by the count.

The effect data generation circuit 49 includes an encoder 56, and the encoder 56 has an incorrect answer processing circuit 2.
The upper and lower signals from 8 are supplied through delay circuits 57 and 58, respectively, and the disqualification signal is supplied directly, so that commands for generating the upper tone, lower tone, and disqualified person, respectively, are obtained. Further, the correct answer score content signal from the correct answer processing circuit 29 is directly sent to the encoder 56, and the accurate signal is sent to the delay circuit 59.
Juan Juale sound, respectively powered through
It is designed to obtain a command to generate a hit sound, and a set sound generation command is also supplied from the main control circuit 13. The sound effect type corresponding to the input command signal to the encoder 56 is supplied to a sound effect data memory 60, and this memory 60 is read out and controlled by an address counter 62 driven by a tempo clock from a tempo generator 61. , generates a sound effect signal corresponding to the specified sound effect from the encoder 56, and supplies it to the musical sound generation circuit 17 via the OR circuit 16, so that the sound effect is generated from the speaker 18. Further, the end of the output of the sound effect data from the sound effect data memory 60 is detected by a FINISH detection circuit 63,
This end detection signal is supplied as a gate signal to the gate circuit 15 and the AND circuit 64, and is also supplied to a differentiating circuit 65, and a pulse signal corresponding to the end of the sound effect from the differentiating circuit 65 is sent to the gate group 66 as a gate signal. Supply as. The AND circuit 64 is supplied with a signal from a NOR circuit 67 which is supplied with an input signal to the encoder 56,
In response to the end of the sound effect, an output signal is generated from the AND circuit 64, and the address counter 62 is reset and initialized.

The gate group 66 is composed of a plurality of AND circuits each supplied with each input signal to the encoder 56, and each gate of the AND circuits is opened by the output pulse signal of the differentiating circuit 65, and the gates are opened for upper and lower tones. The output signal from the AND circuit to which the signal corresponding to the sound is supplied is supplied to the OR circuit 68, and the output signal from this OR circuit 68 is as follows.
The signal is supplied to the incorrect answer processing circuit 28 as the upper and lower incorrect answer signals, and is supplied to the OR circuit 48 so that the counter 46 increments the count. Further, the output signal from the gate group 66 corresponding to the disqualified sound is supplied to the incorrect answer processing circuit 28 and the main control circuit 13 as a disqualification command signal, and the output signal from the gate group 66 corresponding to the fan fare and hit sounds is supplied to the incorrect answer processing circuit 28 and the main control circuit 13. The signal is supplied to the correct answer processing circuit 29 via the OR circuit 69 as a correct/pass command signal. Further, the output signal from the gate group 66 corresponding to the set sound is supplied to the main control circuit 13 as a set sound end (END) signal, and the above-mentioned one shot circuit 27
and generates a one-shot pulse to open the gate of the gate circuit 26.

The main control circuit 13 includes a flip-flop circuit 71 which is set by operating a start switch 70, and an output signal of the flip-flop circuit 71 when set is supplied to an OR circuit 72. In addition, the setting END signal from the target data generation circuit 19 supplied to the main control circuit 13, the key press END signal from the key insertion detection circuit 12, and the setting sound END signal from the effect data generation circuit 49, correct answer, disqualification. Each signal is detected by OR circuits 73 and 74,
The signal is supplied to the OR circuit 72. The output signal from this OR circuit 72 is differentiated by a differentiation circuit 75, and this differentiated pulse is supplied via an OR circuit 76 to a counter 77 as a counting step signal.

Further, the incorrect answer signal supplied from the incorrect answer processing circuit 28 sets a flip-flop circuit 78, and the output signal of this flip-flop circuit 78 at the time of setting is differentiated by a differentiating circuit 79, and further delayed by a delay circuit 80. The output signal from delay circuit 80 is applied to OR circuit 76, and the output signal from delay circuit 80 resets flip-flop circuit 78. The output signal of the flip-flop circuit 78 upon reset is supplied to the counter 77 as an up/down command, so that an up count is set in the reset state and a down count is set in the set state.

The counting data of the counter 77 is detected by a decoder 81 and generates an output signal of "0" to "7", and the output signal of "1" is used to send a target sound setting command to the J terminal of the T-type flip-flop circuit 22. , the output signal "2" is output from the effect data generation circuit 49.
The output signal "3" is supplied to the score processing circuit 30 together with the OR circuit 74 as a score setting command. In addition, the output signal of "4" is sent to the key press detection circuit 12 as a key press detection command.
The output signal "6" is supplied to the determination circuit 21 as a determination command, and the output signal "6" is supplied together with the OR circuit 74 to the score processing circuit 30 as a score display command. Then, the output signal of "7" is supplied to the OR circuit 82 together with the initial clear IC command, and this OR circuit 8
2, the output signal from flip-flop circuit 71
and resets the counter 77.

FIG. 3 shows a flowchart for explaining the operation of the apparatus configured as described above, and the operation of the above apparatus will be explained below in accordance with this flowchart. First, in a first step 201, a start operation is performed by operating the start switch 70. When this switch 70 is operated, the flip-flop circuit 71 is set, and the differential pulse of the differential circuit 75 is sent to the counter 77 via the OR circuit 76.
is supplied as a counting step signal. In this case, the counter 77 and flip-flop circuit 7 are cleared by the initial clear target IC for initial setting.
1 is set to reset, and the flip-flop circuit 78 is reset in its initial state.
The counter 77 is set to count up.

Therefore, in response to the start operation, the count value of the counter 77 is incremented to "1", a target sound setting command is generated from the decoder 81 in response to the count "1", and the target data setting circuit 19 A signal is applied to the J terminal of the T-type flip-flop 22.
Then, the pseudo random code generating circuit 20 is driven in response to the clock φ, and randomly generated data corresponding to the target sound corresponding to the output signal from the random code generating circuit 20 is set by the grade specifying switch circuit 25. When the grade is within the specified grade range, the T-type flip-flop circuit 22 is reset, the generated signal from the random code generation circuit 20, that is, the target sound data is fixed, and the process ends from the target sound setting operation shown in step 202.

In this case, the comparison circuit 24 determines whether the data from the random code generation circuit 20 falls within the set grade range. ”
The output signal from the comparison circuit 24 is supplied to the OR circuit 74 of the main control circuit 13 as a setting END signal, and
By incrementing the counter 77, the output signal "2" of the decoder 81, that is, the set sound generation command can be obtained. This command signal is sent to the effect data generation circuit 4.
The set sound data is supplied to the encoder 56 of 9, and is supplied to the sound effect data memory 60 as a setting sound data selection command, based on an address command from an address counter 62 driven by a tempo clock from a tempo generation circuit 61. is read out from the memory 60 and output. This set sound data is then supplied to the musical sound generation circuit 17 via the OR circuit 16, and the speaker 18 generates a set sound generation operation corresponding to step 203, that is, a sound effect that notifies that the target sound has been set. .

When such setting sound generation operation is completed, this is detected by the completion detection circuit 63, a gate signal is given from the differentiating circuit 65 to the gate group 66, and an output signal is obtained from the AND circuit corresponding to the setting sound generation command. , main control circuit 1 as the setting sound END signal
3, the counter 77 is incremented, and the output signal "3" of the decoder 81 is generated. That is, a score setting command is generated, the accumulator 31 of the score processing circuit 30 is preset to "100 points", and the score presetting operation of step 204 is performed.

In this case, the setting sound END signal from the effect data generation circuit 49 is simultaneously sent to the one shot circuit 2.
7, the gate circuit 26 is opened for a specified time, the target data set in the target data setting circuit 19 is taken out via the OR circuit 14,
The signal is supplied to the gate circuit 15. At this time, since the gate circuit 15 is opened by the output signal corresponding to the end of the set sound effect from the end detection circuit 63, the target sound corresponding to the target data is generated from the speaker 18 following the generation of the set sound. be done.

As mentioned above, when the output signal is obtained from the line "3" of the decoder 81, this signal is further supplied to the OR circuit 74, the counter 77 is incremented, and the output signal is obtained from the line "4" of the decoder 81. A key press detection command is given to the key press detection circuit 12, so that the key press operation of the key considered to correspond to the target sound generated from the speaker 18 is performed on the keyboard section as shown in step 205. Become. When the key press operation in step 205 is performed, a key-on signal and sampling data corresponding to the operated key are obtained from the keyboard circuit 11, and key data corresponding to the pitch of the operated key is generated from the key press detection circuit 12. , this key data is supplied to the musical sound generation circuit 17 via the gate circuit 15 and the OR circuit 16 to which the gate signal is applied in the same manner as described above, and a musical sound with a pitch corresponding to the operated key is generated from the speaker 18. be done. In addition, the key press detection circuit 12
The key data from the target data setting circuit 19 is simultaneously supplied to the determination circuit 21 together with the target data from the target data setting circuit 19, and is stored and held as appropriate.

When the key press operation on the keyboard section is completed, a key press END signal is generated from the key press detection circuit 12, and the main control circuit 13 increments the counter 77 via the OR circuit 74, and the decoder 81 reads "5". An output is generated from the line, and a determination command is given to the determination circuit 21 to perform the determination operation shown in step 206. That is, a comparison is made between the target data and the key data associated with the key press, and when a key with a pitch that matches the target tone is operated, a "match" output is obtained from the determination circuit 21. In addition, when a key with a pitch different from the target tone is operated, the determination circuit 2
In addition to the "mismatch" output from 1, outputs of "A1>B>1" and "A1<B1" are generated depending on whether the direction different from the target is on the treble side or the bass side. The related determination output is supplied to the incorrect answer processing circuit 28, and the "match" determination output is supplied to the correct answer processing circuit 29. That is, when the process of step 207 is performed and the correct answer is a "match" output from the determination circuit 21, a signal is input to the OR circuit 51 in the correct answer processing circuit 29 shown in FIG. The counter 53 is incremented by the output. In this case, the counter 53 is reset in the initial state, and the count value is set to "1" by the "coincidence" signal, and a correct signal is output from the "1" line of the decoder 54. In the effect data generation circuit 49, this correct answer signal gives a command to the encoder 56 via the delay circuit 59, and the hit sound data is given to the sound effect data memory 60. In this case, the gate signal is supplied from the NOR circuit 67 to the AND circuit 64 in the absence of an input signal to the encoder 56, and the signal is generated from the end detection circuit 63 in the absence of sound effects.
The address counter 62 is held in a reset state until the correct answer signal is supplied to the encoder 56, and a winning sound selection command is given from the encoder 56 to the sound effect data memory 60.
The address counter 62 starts counting addresses from the initial state, generates hit sound data from the memory 60, generates a hit sound effect from the speaker 18, and executes step 208.

In this way, when the generation of the winning sound effect ends, a detection signal from the end detection circuit 63 rises, a gate signal is applied from the differentiating circuit 65 to the gate group 66, and the OR circuit 69 responds to the correct signal. A signal is given to the correct answer processing circuit 29, and a correct answer/pass signal is given to the correct answer processing circuit 29. In the correct answer processing circuit 29, the correct answer/pass signal is supplied to the OR circuit 55, which increments the counter 53 and generates an output from the "2" line of the decoder 54.
A gate signal is given to AND circuits 42 and 43.

In this case, in the score processing circuit 30, the accumulator 31 remains preset to "100 points", and this score is supplied to the comparison circuit 38,
It is compared with data R2 from memory 36 (R2=79). That is, the operation of step 209 is performed, an output of "A3<B3" is generated, and an output signal is generated from the AND circuit 42.
The output signal from the AND circuit 42 is supplied as a correct score content command to the encoder 56 of the effect data generation circuit 49 as a fanfare selection command, and the fanfare sound data is read out from the effect data memory 60 in the same manner as described above. From step 18, step 210 is executed in which a fan fare effect representing a correct answer is generated.

In addition, in response to the end of the fanfare sound effect, an output signal is obtained from the gate group 60, a correct answer pass signal is supplied from the OR circuit 69 to the correct answer processing circuit 29, the counter 53 is incremented, and the decoder 54
An output signal is generated from line ``3'' of . This "3" line output signal resets and initializes the counter 53, and also outputs the main control circuit 1.
3 as a correct answer signal, and the OR circuits 73, 7
4, the counter 77 is incremented through the decoder 81
An output signal is generated from the line "6" of the score processing circuit 30, and a score display command is given to the score processing circuit 30, the score content of the accumulator 31 at that time is read out to the register 33, and the score display 34 is displayed as shown in step 211. The score will be displayed on the screen.

Further, the correct answer signal from the correct answer processing circuit 29 simultaneously gives a command to the grade setting switch circuit 25 to select a new grade range.

The signal from the "6" line of the decoder 81 is further sent to the counter 7 via an OR circuit 74.
7 and generates an output signal from the "7" line of the decoder 81, and the flip-flop circuit 71
is reset, and about one row of sound guessing gates is completed.

Further, in step 206 of determining the output signal from the line "5" of the decoder 81, if the generated target sound and the sound obtained by pressing the key are different, that is, if the key is pressed incorrectly, Judgment circuit 2
1, a determination output of "inconsistency" and an upper or lower determination output for determining whether the error direction is from the treble side or the bass side are obtained. The "non-coincidence" judgment output is supplied to the OR circuit 44 of the incorrect answer processing circuit 28, which increments the counter 46 initially set by the output of the differentiating circuit 45, and starts from the "1" line of the decoder 47. Command signals can now be obtained. This mismatch command signal gives an operation command EN to the accumulator 31 of the score processing circuit 30, and the memory 3
Add the memorized "-30 points" to 2 to make the cumulative value "70 points." That is, step 212 of deducting points is executed.

The signal on the "1" line of the decoder 47 is simultaneously supplied to the OR circuit 44 via the OR circuit 48, increments the counter 46, and generates an output signal from the "2" line of the decoder 47. A gate signal is given to 39 to 41.

At this time, the comparator circuit 37 uses the accumulator 31 at that time.
The score data “70 points” and the data “R” in memory 35
1=20 points" and generates a comparison output of "A2<B2", AND circuits 39, 40
At this point, a step 213 is executed to determine whether the score is less than or equal to R1, and a "NO" determination is made in step 213. Therefore, an output signal is obtained from the AND circuit 39 or 40 in response to the upper or lower judgment output signal from the judgment circuit 21, and step 214 is executed. The output signal from this AND circuit 39 or 40 is supplied to the encoder 56 via delay circuits 57 and 58.
A selection command for an upper tone or a lower tone is supplied to the sound effect data memory 60, and in the same way as described above, the upper tone or lower tone is selected.
A sound effect indicating the lower error direction is generated from the speaker 18, and step 215 or 216 is executed. In addition, in response to the end of this sound effect, an output signal is obtained from the gate group 66, and upper and lower incorrect answer signals are generated from the OR circuit 68, and are supplied to the incorrect answer processing circuit 28 to increment the counter 46. , an output signal is generated from the "3" line of the decoder 47. The output signal from the "3" line further increments the counter 46 via the OR circuits 48 and 44, and generates an output signal from the "4" line of the decoder 47 to reset the counter 46 and initialize it. At the same time, it is supplied to the main control circuit 13 as an incorrect answer signal, and the flip-flop circuit 78 is set.

When the flip-flop circuit 78 is set, the counter 73 is set to count down, and the differential pulse from the differential circuit 79 is supplied to the OR circuit 76 via the delay circuit 80, causing the counter "77" to count down by one. decoder 81
An output signal is obtained from line "4", and a key press detection command is given to the key press detection circuit 12.
That is, the process returns to step 205, and the key corresponding to the target sound is selected and operated again.
Steps 206 and 207 will be repeated.

And if the correct answer key is manipulated here,
Proceeding to step 208, the comparator circuit 38 compares the score of the accumulator 31 at that time with R2 of the memory 36, but at this time the score of the accumulator 31 is "70 points". From the comparison circuit 38, “A3>
An output signal of "B3" is obtained, an output signal is generated from the AND circuit 43, the counter 53 is incremented, an output signal is generated from the "3" line of the decoder 54, and the process proceeds to step 211.

If the wrong key is operated again in step 205, an incorrect answer is determined in steps 206 and 207, and the accumulator 31 is operated again in step 212.
The cumulative score is deducted, and steps 214 and 215
Alternatively, step 216 is repeated and the process returns to step 205. That is, each time a key with a pitch different from the target tone is operated, the process returns to step 205, and the score in the accumulator 31 is decremented each time this process is repeated. Then, the comparison circuit 37 of the incorrect answer processing circuit 28 can obtain a comparison output of "A2>B2". A disqualification signal is output from the AND circuit 41, and this signal is supplied to the encoder 56, so that the speaker 18 generates the disqualification sound effect of step 217. Then, in response to the end of this disqualification sound effect, the main control circuit 1
3 is supplied with a disqualification signal, the counter 77 is incremented via the OR circuits 73 and 74, and the score is displayed by the signal from the line "6" of the decoder 81, and the counter 77 is further incremented by the signal from this line. Then, the flip-flop circuit 71 is reset by a signal from the line "7" of the decoder 81, and the operation is completed.

FIG. 4 shows an embodiment that is further simplified and can also have a game-like element in combination with a normal electronic musical instrument. is supplied to the musical tone generation circuit 17 via the control switch 102 as shown in the figure.
When a gate signal is applied to the gate circuit 16, a performance sound corresponding to a normal key operation is obtained from the speaker 18. Further, pitch data from the keyboard circuit 11 is supplied to a latch circuit 103. The latch circuit 103 includes, for example, latch memory elements corresponding to the number of keys, and information such as "1" is stored in the latch memory element corresponding to the operated key. A load command is given to perform a storage operation. That is, when a key is operated on the keyboard section while the flip-flop circuit 104 is set, data "1" is stored in the latch memory element corresponding to the pitch of the operated key, and a plurality of data are stored. When a key is operated, data "1" is latched stored in the storage element corresponding to each of the operated keys. The data of the latch storage element corresponding to each of these keys, that is, the pitch data, is supplied to the gate group 105 and the comparison circuit 106, and the gate group 105 outputs the data to the ring counter 107.
Based on the counting data from the latch circuit 103
The data stored in each latch storage element is sequentially read out and supplied to the gate circuit 108. This gate signal 108 is a gate signal given when the control switch 102 is turned to the "GAME" side, and supplies the pitch data read out from the gate group 105 to the OR circuit 109, and further outputs the pitch data read from the gate group 105 to the OR circuit 109. The signal is supplied to the pitch generating circuit 17 via the pitch generating circuit 16, and the sound is generated from the speaker 18.

A signal when the start switch 70 is operated is sent to a flip-flop circuit 111 via a differentiating circuit 110.
Set. This flip-flop circuit 111
is used to give a random number generation start command to the random number generation circuit 19a at the time of setting, and this random number generation circuit 19a generates numerical data in the grade range set by the grade designation switch circuit 25, that is, code data expressing pitch. When , the generated data is fixed and this data is sent to decoder 1.
12. And this decoder 112
Then, pitch data similar to that obtained from the latch circuit 103 is supplied to the comparison circuit 106.

The comparison circuit 106 generates an equal signal EQ when there is data equal to the randomly generated pitch data obtained from the decoder 112 in the pitch data supplied from the latch circuit 103, and outputs an equal signal EQ. A differential pulse is generated from 113. This differential pulse resets ring counter 107, provides a reset command to latch circuit 103 to clear stored data, and also resets flip-flop circuits 104 and 114.

The random number generation circuit 19a generates an end signal when the generated data is fixed as described above, and this end signal is converted into a differentiated pulse by the differentiating circuit 115, and the end signal is converted into a differentiated pulse by the differentiating circuit 115.
Set 4. The output signal from the set flip-flop circuit 114 provides a gate signal to the AND circuit 116. The AND circuit 116 is supplied with the signal from the selector 117, and the output signal from the AND circuit 116 is a ring gate signal. It is supplied to the counter 107 as a count signal.

The selector 117 is supplied with the signal from the variable frequency dividing circuit 118 as an input A, and also with the system clock φ as an input B. When the pitch data is output from the gate circuit 108, This is detected by the OR circuit 119,
The output signal from this OR circuit 119 is sent to the selector 1.
Select command to select input A for 17
Supplied as SA. Here, the variable frequency dividing circuit 11
8 includes a latch circuit 1 along with a system clock φ.
03, sets a frequency division ratio as appropriate in accordance with this pitch number data, divides the clock φ by the selected frequency division ratio, and supplies the divided frequency to the selector 117. It is supplied to the selector 117 as a signal with a period sufficiently larger than at least the system clock φ. The variable frequency dividing circuit 118 is reset and initialized by a differential pulse corresponding to the equal signal EQ from the differentiating circuit 113.

The pitch data from the latch circuit 103 is further supplied to a key-on detection circuit 120, which detects a key-on signal each time a key is operated on the keyboard section and new pitch data is latched into the latch circuit 103. This key-on detection signal is supplied to the flip-flop circuit 121 as a reset command, and to the address counter 122 via the OR circuit 123 as a reset command. Set by the corresponding differential pulse signal. The set output signal of the flip-flop circuit 121 is supplied to the AND circuit 125 together with the tempo clock signal TCL from the tempo clock generation circuit 124, and the output signal from the AND circuit 125 is sent to the address counter 122 via the OR circuit 126. Supplied as an address increment signal. The OR circuit 126 is also supplied with the tempo clock signal TCL, and also couples the output signal from the AND circuit 128 to which the gate signal is applied when the flip-flop circuit 127 is set.
is set by the differential pulse from the differential circuit 113. The differential pulse from the differentiating circuit 113 is supplied to the OR circuit 129 together with the differential pulse from the differentiating circuit 115, and the output signal from the OR circuit 129 resets and initializes the tempo clock generating circuit 124. In addition, the differentiation circuit 115
The differential pulse from the flip-flop circuit 11
Reset 1.

The address data that is incremented together with the tempo clock signal TCL from the address counter 122 is
Sound effect data memory 130 consisting of ROM etc.
This data memory 130 is supplied with read data designation commands for "theme sound" and "hit sound" from flip-flop circuits 121 and 127, respectively. For example, when the flip-flop circuit 121 is set, a "theme sound" is specified in the data memory 130, and a target sound is set from the data memory 130 in response to an address increment from the address counter 122. Theme sound data expressing the theme is read out and supplied to the OR circuit 16 via the decoder 131. Then, the theme sound is generated from the speaker 18.

Further, when data reading from the data memory 130 is finished, a finish detection circuit 132 detects this, and a differentiation circuit 133 obtains a finish data pulse. This end data pulse is supplied to the OR circuit 123, as well as to the flip-flop circuit 127 as a reset command, and further supplied to the AND circuit 134 to which the gate signal is supplied by the set of the flip-flop circuit 121. The output signal from the AND circuit 134 drives the one-shot circuit 27 to open the gate circuit 26 for a specified period of time and open the decoder 11.
2, pitch data set with random numbers, that is, target data, is supplied to the OR circuit 109 so that the speaker 18 generates the target sound.

That is, in the apparatus configured as described above, when the control switch 102 is set to the "PLAY" side as shown in the figure, normal performance is performed on the keyboard section. When playing a sound guessing game, the control switch 102 is turned on to the "GAME" side, and the gate circuit 108 is set to receive a gate signal.

When the start switch 70 is operated in this state, the flip-flop circuit 111 is set, the random number generation circuit 19a is started, and the data is generated while generating random number data within the grade range set by the grade designation switch circuit 25. is fixed and supplied to the comparison circuit 106 via the decoder 112 as pitch data of the target sound. In this way, when the random number generation operation is completed, the differentiating circuit 1
A differential pulse is generated from 15, and the latch circuit 10
3, resets the flip-flop circuit 111, further sets the flip-flop circuits 104, 114, 121,
A gate signal is given to the AND circuit 125. That is, while giving a "theme sound" command to the sound effect data memory 130, the address counter 1
30 is now driven by the tempo clock signal TCL, the decoder 131 generates theme sound data for setting the target sound, and the speaker 18 becomes in a state where the theme sound is played. When the theme sound ends, the end detection circuit 132 generates a detection signal, and the differentiation circuit 133 outputs the end pulse as follows.
The address counter 122 is reset, and the one-shot circuit 27 is driven via the AND circuit 134 whose gate is opened by setting the flip-flop circuit 121, thereby opening the gate circuit 26 for a specified time. That is, the pitch data of the target sound obtained from the decoder 112 is
6 to the musical tone generation circuit 17, and the target tone is generated from the speaker 18 for a specified period of time.

In this way, when the target sound is generated from the speaker 18, the gamer recognizes the pitch of the target sound and operates a key that seems to correspond to the pitch.
In response to this key operation, pitch data is output from the keyboard circuit 11 and is latched and stored in the latch circuit 103 to which the load command has been given as described above. When the pitch data is stored in the latch circuit 103, a detection signal is obtained from the key-on detection circuit 120, and the flip-flop circuit 121 is reset, and the latched pitch data is supplied to the gate group 105. In this state, the flip-flop circuit 114 is set, and since there is no output pitch data from the gate group 105,
Select command SA is not given to selector 117 from OR circuit 119. Therefore, a count signal corresponding to the clock φ is applied from the AND circuit 116 to the ring counter 107, and the count signal corresponding to the clock φ is applied to the ring counter 107.
A gate signal is sequentially applied at high speed to the gate corresponding to the pitch of each key of 5, the pitch data latched and stored in the latch circuit 103 is searched, and when the gate corresponding to the pitch data is opened, the gate signal is applied to the gate corresponding to the pitch of each key. The pitch data is output from 105 and sent to the gate circuit 10.
8. The sound is supplied to the musical sound generation circuit 17 via the OR circuits 109 and 16, and a performance sound corresponding to the pitch of the operating key is generated from the speaker 18. In this case, when such pitch data is output, it is detected by the OR circuit 119, a select command SA is given to the selector 117, and the variable frequency divider circuit 118
A signal is supplied to the ring counter 107 for counting purposes, and a performance sound accompanying the key depression is generated for a sufficiently perceptible period of time. That is, the gate group 105 selects only the gate section where pitch data exists and outputs the pitch data from that gate section for a period that is sufficiently perceptible, and the gate section where pitch data does not exist is output by the clock φ. Searching is performed at high speed, resulting in so-called jump control.

In this way, when a key is pressed and the pitch data corresponding to the operated key is stored in the latch circuit 103, the latch pitch data is compared with the target pitch data from the decoder 112 in the comparator circuit 106. be done. If the pressed key pitch is different from the target pitch, the comparison circuit 106 does not generate an equal signal EQ, and the speaker 18 only obtains the performance sound corresponding to the pressed key pitch, and the game The user further operates another key that is considered to be the target pitch, and the pitch data of the operated key is further latched and stored in the latch circuit 103. If the pressed key pitch is also different from the target pitch, the speaker 18 only generates the performance sound of the pressed key pitch in the same manner as described above.

Then, when the correct key corresponding to the target tone is operated on the keyboard section and the pitch data is latched and stored in the latch circuit 103, the comparison circuit 106 generates an equal signal EQ, and the differentiation circuit 113 generates a differential pulse. be done. This differential pulse resets flip-flop circuit 104 and latch circuit 10.
3 and flip-flop circuit 1
27 to designate the "hit sound" in the sound effect data memory 130, and then input the AND circuit 128.
A gate signal is applied to the address counter 122 to drive the address counter 122 with the tempo clock signal TCL. That is,
Winning sound data is output from the data memory 130, musical sound data corresponding to the winning sound is generated from the decoder 131, and a winning sound indicating the correct key press is played from the speaker 18. When the winning sound ends, a detection signal is obtained from the end detection circuit 132, and the address counter 122 and flip-flop circuit 127 are reset by the output pulse from the differentiating circuit 133, and one sound guessing game operation is completed.

As described above, according to the present invention, a randomly generated target sound is listened to, and a key corresponding to the pitch of the target sound is operated to automatically determine whether accurate pitch discrimination has been performed. The result of the judgment is expressed as a sound effect, and the score in the judgment process is displayed. In particular, according to the embodiment shown in FIG. 1, if the answer is incorrect, it is determined and displayed whether the target tone is located on the higher or lower side of the key pressed sound, and if the answer is correct, the answer is correct. A sound is generated, and if a score above a certain level is obtained, a sound effect by Juan Juare is displayed. Therefore, self-study pitch learning can be carried out effectively while having fun.

In addition, in the explanation so far, the key is pressed after listening to the target sound, but if the target sound is silent and the sound effect is related to the pitch difference from the target sound, this effect can be improved. It is possible to increase the fun of the game by being able to quickly reach the target sound by relying on the sound.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram illustrating a training device according to an embodiment of the present invention, FIG. 2 is a diagram showing the incorrect answer and correct answer processing circuit sections of the device, and FIG. 3 is a diagram explaining the operation of the device. flowchart, 4th
The figure is a configuration diagram illustrating another embodiment of the present invention. 11...Keyboard circuit, 13...Main control circuit, 17...Music tone generation circuit, 18...Speaker, 19...Target data setting circuit, 20...Pseudo random pulse generation circuit,
21... Judgment circuit, 25... Grade designation switch circuit, 28... Incorrect answer processing circuit, 29... Correct answer processing circuit, 30... Score processing circuit, 49... Effect data generation circuit, 70... Start switch, 19a... Random number generation circuit, 103 ... Latch circuit, 106 ... Comparison circuit (correct answer judgment), 130 ... Sound effect data memory.

Claims (1)

[Claims] 1. A target sound data generating means 19 that randomly generates target sound data corresponding to the pitch of a target sound, and pitch data of a sound corresponding to a key selected and specified by an operator. Pitch data generating means 11 that generates
and a comparison determination means 21 for comparing and determining a vertical relationship in pitch between the target sound data and pitch data corresponding to the selected key based on the target sound data and pitch data; and the comparison determination means Display means 4 for displaying the above-mentioned vertical relationship of pitches using sound effects based on the determination result of
9, 17, and a score processing means for calculating and displaying a score related to the number of times that the target sound data and the pitch data corresponding to the selected and designated key do not match, based on the determination result of the comparison and determination means. 30, and a sound guessing training device characterized by comprising the following. 2. The sound guessing training device according to claim 1, wherein the target sound data generating means specifies a setting range thereof. 3. The sound guessing training device according to claim 2, wherein the setting range of the target sound data is changed for each correct key press.