JPH0145750B2 - - Google Patents
Info
- Publication number
- JPH0145750B2 JPH0145750B2 JP14532881A JP14532881A JPH0145750B2 JP H0145750 B2 JPH0145750 B2 JP H0145750B2 JP 14532881 A JP14532881 A JP 14532881A JP 14532881 A JP14532881 A JP 14532881A JP H0145750 B2 JPH0145750 B2 JP H0145750B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- electrode
- memory element
- semiconductor
- ferroelectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 claims description 44
- 239000004065 semiconductor Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 10
- 230000010287 polarization Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims 1
- 239000010408 film Substances 0.000 description 4
- 229910009580 YMnO Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Description
【発明の詳細な説明】
本発明は強誘電体記憶素子に係り、特に素子の
微細化および高速化に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a ferroelectric memory element, and particularly to miniaturization and speeding up of the element.
従来の強誘電体記憶素子としては第１図ａのよ
うに強誘電体基板１ａの一方の面に半導体薄膜２
ａを被着し、共通電極３、読み出し電極５、およ
び基板の反対面に書き込み電極４を形成したも
の、および第１図ｂのように半動体基板２ｂ上に
電界効果トランジスタを形成し、チヤンネル部分
の上に強誘電体薄膜１ｂを形成して共通電極（ソ
ース電極）３、読み出し電極（ドレイン電極）
５、および書き込み電極（ゲート電極）４を形成
したものがある。前者は強誘電体の厚さが厚いた
めに分極ドメインが小さくできず、素子の微細化
が不可能であり、また後者は比較的微細化が容易
であるが、ソース、ドレインの高濃度拡散層６お
よびその両側面に形成される比較的大きなフイー
ルド酸化膜７のために構造が複雑であり、微細化
への制約がある。また両者において、書き込み時
の電流通路は第１図ａ，ｂの矢印８で示されるよ
うに半導体領域の横方向となり、抵抗値が高いた
めに分極反転のスピードが遅くなる。 As shown in FIG. 1a, a conventional ferroelectric memory element has a semiconductor thin film 2 on one surface of a ferroelectric substrate 1a.
A, a common electrode 3, a readout electrode 5, and a write electrode 4 are formed on the opposite side of the substrate, and a field effect transistor is formed on the semi-dynamic substrate 2b as shown in FIG. 1b, and a channel is formed. A ferroelectric thin film 1b is formed on the portion to form a common electrode (source electrode) 3 and a readout electrode (drain electrode).
5 and a write electrode (gate electrode) 4 are formed. In the former case, the polarization domain cannot be made small due to the thickness of the ferroelectric material, making it impossible to miniaturize the device, while in the latter case, it is relatively easy to miniaturize the device, but it requires high concentration diffusion layers in the source and drain. 6 and a relatively large field oxide film 7 formed on both sides thereof, the structure is complicated and there are restrictions on miniaturization. In both cases, the current path during writing is in the lateral direction of the semiconductor region as shown by arrows 8 in FIGS. 1a and 1b, and the speed of polarization inversion is slow due to the high resistance value.
本発明の目的は前記のような制約を除き、微細
化と高速化が可能な素子構造を提供しようとする
ものであり、第２図ａ〜ｃに基づいてその特徴を
説明する。第２図ａは本発明の構造を示す図であ
り、絶縁体基板９上に書き込み電極４、強誘電体
薄膜１ｂ、半導体薄膜２ａ、絶縁体薄膜１０およ
び書き込み電極４を積層し、半導体薄膜２ａの両
端に読み出し電極５を設けている。 An object of the present invention is to eliminate the above-mentioned limitations and provide an element structure that can be miniaturized and increased in speed, and its features will be explained based on FIGS. 2a to 2c. FIG. 2a is a diagram showing the structure of the present invention, in which a write electrode 4, a ferroelectric thin film 1b, a semiconductor thin film 2a, an insulator thin film 10, and a write electrode 4 are laminated on an insulating substrate 9, and a semiconductor thin film 2a Readout electrodes 5 are provided at both ends.
本発明の第１の特徴は前記のように強誘電体を
含む全構成要素を薄膜化し、分極のドメインサイ
ズによる制約を除き、構造を単純化して素子の微
細化を可能とし、また書き込み電圧の印加方向を
第２図ａの矢印８のように膜面を垂直として、分
極反転のピードを向上させることである。 The first feature of the present invention is to reduce the thickness of all the components including the ferroelectric as described above, remove the restrictions imposed by the domain size of polarization, simplify the structure, enable miniaturization of the device, and reduce the write voltage. The purpose of this is to increase the speed of polarization inversion by setting the direction of application perpendicular to the film surface as indicated by arrow 8 in FIG. 2a.
第２図ｂおよびｃはそれぞれ２値信号の“１”
および“０”に対応した記憶状態での各層電荷密
度±Ｑを示す図である。半導体薄膜２ａ中の電荷
密度およびその極性によつて読み出し電極５間の
導電率が決定され、半導体薄膜がｎ型ののときは
マイナス電荷のとき導通、プラス電荷のとき非導
通となる。ここで、半導体薄膜２ａに書き込み電
極４を直接積層すると、同電極に発生する電荷の
ために半動体薄膜中の電荷は打消され、電荷密度
は第２図ｂ，ｃの点線で示した分布曲線となり、
読み出し電極間に導電率変化は極めて小さくな
る。そこで、本発明の第２の特徴は半導体薄膜２
ａと書き込み電極４との間に絶縁体薄膜１０を挿
入し、前記の導電率変化の低下、即ち読み出し出
力信号の低下を防ごうとするものである。 Figure 2 b and c are binary signals of “1” respectively.
FIG. 3 is a diagram showing charge density ±Q of each layer in a storage state corresponding to “0”. The conductivity between the readout electrodes 5 is determined by the charge density in the semiconductor thin film 2a and its polarity, and when the semiconductor thin film is of n-type, conduction occurs when the semiconductor thin film has a negative charge, and non-conduction when the semiconductor thin film has a positive charge. Here, when the write electrode 4 is directly laminated on the semiconductor thin film 2a, the charge generated in the semiconductor thin film 2a cancels the charge in the semi-moving thin film, and the charge density is determined by the distribution curve shown by the dotted lines in FIG. 2b and c. Then,
The conductivity change between the readout electrodes becomes extremely small. Therefore, the second feature of the present invention is that the semiconductor thin film 2
An insulating thin film 10 is inserted between the write electrode 4 and the write electrode 4 in order to prevent the aforementioned decrease in conductivity change, that is, the decrease in the read output signal.
本発明の第３の特徴は実施態様の一つとして、
本記憶素子を後述するように２端子構造とし、ワ
ード線とビツト線のマトリツクスで構成されるメ
モリプレーンの構造を単純化し、高密度化を計
り、メモリープレーンとしての動作スピードを向
上させようとするものである。 The third feature of the present invention is, as one of the embodiments,
As will be described later, this memory element has a two-terminal structure, and the structure of the memory plane, which is composed of a matrix of word lines and bit lines, is simplified to increase the density and improve the operating speed of the memory plane. It is something.
つぎに本発明の一実施例を第２図ａに基づいて
説明する。まず、清浄なガラス基板９に真空蒸着
法によりAlを約1000Å被着し、通常のホトニツ
チング技術により書き込み電極４を形成する。つ
ぎに高周波スパツタリングによりYMnO3を約1μ
ｍ被着し強誘電体層１ｂとし、更に続けてプラズ
マCVD法によりｎ型のアモーフアスシリコンを
約0.5μｍ被着し、半導体層２ａとする。プラズマ
CVDにおける基板温度は通常のポリシリコンを
被着する場合より低く、約200℃とする。つぎに
１ｂおよび２ａの両端膜をフロンガスによるプラ
ズマエツチング法により同一パターンに形成す
る。つぎにSiO2を高周波スパツリングにより0.5μ
ｍ被着し、ホトエツチング技術により絶縁体層１
０とする。最後にAlを空蒸着法により約1000Å
被着し、ホトエツチング技術により書き込み電極
４および読み出し電極５を形成する。 Next, one embodiment of the present invention will be described based on FIG. 2a. First, approximately 1000 Å of Al is deposited on a clean glass substrate 9 by vacuum evaporation, and the write electrode 4 is formed by ordinary photonitching technology. Next, about 1μ of YMnO 3 was deposited by high-frequency sputtering.
Then, approximately 0.5 μm of n-type amorphous silicon is deposited by plasma CVD to form a semiconductor layer 2a. plasma
The substrate temperature in CVD is about 200°C, which is lower than when depositing normal polysilicon. Next, both end films 1b and 2a are formed into the same pattern by plasma etching using fluorocarbon gas. Next, SiO 2 is reduced to 0.5μ by high-frequency sputtering.
Insulator layer 1 is deposited using photo-etching technology.
Set to 0. Finally, Al is applied to approximately 1000Å by empty evaporation method.
Then, a write electrode 4 and a read electrode 5 are formed by photo-etching.
第３図は本発明による他の実施例を示すもので
あり、第２図ａにおける一方の読み出し電極を一
方の書き込み電極に抵抗薄膜１１で結び、他方の
読み出し電極を他方の書き込み電極に導体薄膜で
結ぶことにより２端子構造とし、書き込みおよび
読み出しを同一電極でできるようにしたものであ
る。本実施例は前記実施例で強誘電体薄膜と半導
体薄膜を同一のパターンに形成したところ別々に
パターンニングし、一方の端に第３図のような段
差を設け、ここにTaのスパリツタリングによる
抵抗薄膜を追加形成するだけで、前記の実施例と
同様にして本実施例の素子を形成することができ
る。この場合は抵抗薄膜１１により、書き込みお
よび読み出し若干の損失が加わるが、第４図のよ
うにワード線１２とビツト線１３により記憶素子
１４を挟み込む形でメモリープレーン１５が構成
できるので構造が極めて単純化され、メモリープ
レーンの高密度化が可能となる。従つて記憶装置
としての動作スピードも向上させることが可能で
ある。 FIG. 3 shows another embodiment according to the present invention, in which one read electrode in FIG. 2a is connected to one write electrode with a resistive thin film 11, and the other read electrode is connected to the other write electrode with a conductive thin film By connecting the two terminals, a two-terminal structure is created, and writing and reading can be performed using the same electrode. In this example, the ferroelectric thin film and the semiconductor thin film were formed in the same pattern in the previous example, but they were patterned separately, a step was provided at one end as shown in Figure 3, and Ta was spritzed there. The element of this example can be formed in the same manner as in the previous example by simply additionally forming a resistive thin film according to the above. In this case, the resistance thin film 11 adds some loss in writing and reading, but the memory plane 15 can be configured with the memory element 14 sandwiched between the word line 12 and the bit line 13 as shown in FIG. 4, so the structure is extremely simple. This makes it possible to increase the density of the memory plane. Therefore, the operating speed of the storage device can also be improved.
なお、前記実施例では強誘電体薄膜として
YMnO3を使用したが、BrMnO3、HoMnO3、
TmMnO3、YbMnO3およびLuMnO3も同様に使
用可能である。 In addition, in the above example, as a ferroelectric thin film,
Although YMnO 3 was used, BrMnO 3 , HoMnO 3 ,
TmMnO 3 , YbMnO 3 and LuMnO 3 can be used as well.
第１図ａ，ｂは従来の構造、第２図ａは本発明
による一実施例、第２図ｂ，ｃは本発明の構成に
おける電荷密度±Ｑの分布図、第３図および第４
図は他の実施例を示す図である。ここで１ａは強
誘電体基板、１ｂは強誘電体薄膜、２ａは半導体
薄膜、２ｂは半導体基板、３は共通電極、４は書
き込み電極、５は読み出し電極、６は高濃度拡散
層、７はフイールド酸化膜、８は書き込み電流の
流れる方向、９はガラス基板、１０は絶縁体薄
膜、１１は抵抗薄膜、１２はワード線、１３はビ
ツト線、１４は記憶素子、１５はメモリープレー
ンである。
1A and 1B are conventional structures, FIG.
The figure shows another embodiment. Here, 1a is a ferroelectric substrate, 1b is a ferroelectric thin film, 2a is a semiconductor thin film, 2b is a semiconductor substrate, 3 is a common electrode, 4 is a write electrode, 5 is a read electrode, 6 is a high concentration diffusion layer, and 7 is a A field oxide film, 8 a writing current flowing direction, 9 a glass substrate, 10 an insulating thin film, 11 a resistive thin film, 12 a word line, 13 a bit line, 14 a storage element, and 15 a memory plane.
Claims (1)
の分極により該半導体のキヤリヤ濃度を変化させ
る強誘電体記憶素子において、絶縁基板上に電極
薄膜、強誘電体薄膜、半導体薄膜、絶縁体薄膜お
よび電極薄膜を本記載の順序で積層するか、また
は本記載の逆の順序で積層して形成したことを特
徴とする記憶素子。 ２ 電極薄膜、強誘電体薄膜、半導体薄膜、絶縁
体薄膜および電極薄膜の積層構造を有し、前記各
電極薄膜を書き込み電極とし、前記半導体薄膜に
一対の読み出し電極を設けた記憶素子において、
一方の読み出し電極を一方の書き込み電極に高抵
抗の薄膜で結び、他方の読み出し電極を他方の書
き込み電極に低抵抗の薄膜で結び、両書き込み電
極による２端子構造としたことを特徴とする記憶
素子。 ３ 強誘電体薄膜がYMoO3、ErMnO3、
HnMnO3 TmMnO3、YbMnO3またはLuMnO3
のうちの一つの薄膜であることを特徴とする特許
請求の範囲第１項または第２項記載の記憶素子。 ４ 半導体薄膜がアモーフアスシリコン薄膜であ
ることを特徴とする特許請求の範囲第１項または
第２項記載の記憶素子。[Claims] 1. In a ferroelectric memory element in which a ferroelectric material and a semiconductor are brought into contact with each other and the carrier concentration of the semiconductor is changed by polarization of the ferroelectric material, an electrode thin film and a ferroelectric material are provided on an insulating substrate. A memory element characterized in that it is formed by laminating a thin film, a semiconductor thin film, an insulating thin film, and an electrode thin film in the order described herein or in the reverse order of the description. 2. A memory element having a laminated structure of an electrode thin film, a ferroelectric thin film, a semiconductor thin film, an insulator thin film, and an electrode thin film, each of the electrode thin films serving as a write electrode, and a pair of read electrodes provided on the semiconductor thin film,
A memory element characterized in that one read electrode is connected to one write electrode with a high-resistance thin film, and the other read electrode is connected to the other write electrode with a low-resistance thin film, creating a two-terminal structure with both write electrodes. . 3 The ferroelectric thin film is YMoO 3 , ErMnO 3 ,
HnMnO 3 TmMnO 3 , YbMnO 3 or LuMnO 3
The memory element according to claim 1 or 2, wherein the memory element is one of the thin films. 4. The memory element according to claim 1 or 2, wherein the semiconductor thin film is an amorphous silicon thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145328A JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56145328A JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5846680A JPS5846680A (en) | 1983-03-18 |
| JPH0145750B2 true JPH0145750B2 (en) | 1989-10-04 |
Family
ID=15382619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56145328A Granted JPS5846680A (en) | 1981-09-14 | 1981-09-14 | Memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846680A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2778977B2 (en) * | 1989-03-14 | 1998-07-23 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| US5578846A (en) * | 1995-03-17 | 1996-11-26 | Evans, Jr.; Joseph T. | Static ferroelectric memory transistor having improved data retention |
| JP3137880B2 (en) * | 1995-08-25 | 2001-02-26 | ティーディーケイ株式会社 | Ferroelectric thin film, electronic device, and method of manufacturing ferroelectric thin film |
| JP4247377B2 (en) | 2001-12-28 | 2009-04-02 | 独立行政法人産業技術総合研究所 | Thin film transistor and manufacturing method thereof |
-
1981
- 1981-09-14 JP JP56145328A patent/JPS5846680A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5846680A (en) | 1983-03-18 |
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