JPH0145266Y2 - - Google Patents

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Publication number
JPH0145266Y2
JPH0145266Y2 JP1982199048U JP19904882U JPH0145266Y2 JP H0145266 Y2 JPH0145266 Y2 JP H0145266Y2 JP 1982199048 U JP1982199048 U JP 1982199048U JP 19904882 U JP19904882 U JP 19904882U JP H0145266 Y2 JPH0145266 Y2 JP H0145266Y2
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Japan
Prior art keywords
output
terminal
power supply
diode
rectified
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Expired
Application number
JP1982199048U
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Japanese (ja)
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JPS5999694U (en
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Priority to JP19904882U priority Critical patent/JPS5999694U/en
Publication of JPS5999694U publication Critical patent/JPS5999694U/en
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Description

【考案の詳細な説明】 産業上の利用分野 この考案は整流回路、特に複数個の整流出力を
得る場合等に用いて好適な整流回路に関する。
[Detailed Description of the Invention] Industrial Application Field This invention relates to a rectifier circuit, and particularly to a rectifier circuit suitable for use when obtaining a plurality of rectified outputs.

背景技術とその問題点 従来複数個の整流出力を得る場合として例えば
第1図に示すようなものが提案されている。即
ち、同図において、電源端子1及び2間に交通電
源3が接続され、電源端子1が抵抗器4を介して
ブリツジ整流器5のダイオード5aのアノード及
びダイオード5bのカソードの接続点に接続さ
れ、ダイオード5a及び5cの各カソードの接続
点より出力端子6が取り出され、一方ダイオード
5b及び5dの各アノードの接続点より出力端子
7が取り出される。そして、これら出力端子6及
び7間に主出力である第1の整流出力を得るよう
にしている。
BACKGROUND TECHNOLOGY AND PROBLEMS Conventionally, as a case of obtaining a plurality of rectified outputs, an arrangement as shown in FIG. 1, for example, has been proposed. That is, in the same figure, a traffic power supply 3 is connected between power supply terminals 1 and 2, and power supply terminal 1 is connected to a connection point between an anode of a diode 5a and a cathode of a diode 5b of a bridge rectifier 5 via a resistor 4. An output terminal 6 is taken out from the connection point between the cathodes of the diodes 5a and 5c, and an output terminal 7 is taken out from the connection point between the anodes of the diodes 5b and 5d. A first rectified output, which is a main output, is obtained between these output terminals 6 and 7.

また、出力端子6及び7間にコンデンサ8及び
9の直列回路が接続されこれらコンデンサ81及
び9の接続点がスイツチ10を介してブリツジ整
流器5のダイオード5cのアノード及びダイオー
ド5dのカソードの接続点に接続されると共に電
源端子1に接続されている。又、副出力である第
2の整流出力を得るために電流端子1が抵抗器1
1を介してブリツジ整流器12のダイオード12
aのアノード及びダイオード12bのカソードの
接続点に接続されると共にダイオード12a及び
12cの各カソードの接続点が出力端子13に接
続され、一方ダイオード12b及び12bの各ア
ノードの接続点が出力端子14に接続されてい
る。そして、これ等出力端子13及び14間に副
出力である第2の整流出力を得るようにしてい
る。
Further, a series circuit of capacitors 8 and 9 is connected between the output terminals 6 and 7, and the connection point of these capacitors 81 and 9 is connected to the connection point of the anode of the diode 5c and the cathode of the diode 5d of the bridge rectifier 5 via the switch 10. It is also connected to the power supply terminal 1. In addition, in order to obtain the second rectified output which is the sub-output, the current terminal 1 is connected to the resistor 1.
1 through the diode 12 of the bridge rectifier 12
The connection point between the anode of the diode 12a and the cathode of the diode 12b is connected to the output terminal 13, and the connection point of the cathode of the diodes 12a and 12c is connected to the output terminal 13, while the connection point of the anode of the diodes 12b and 12b is connected to the output terminal It is connected. A second rectified output, which is a sub-output, is obtained between these output terminals 13 and 14.

更に出力端子13及び14間にコンデンサ15
及び16の直列回路が接続され、これらコンデン
サ15及び16の接続点がスイツチ17を介して
ブリツジ整流器12のダイオード12cのアノー
ド及びダイオード12dのカソードの接続点に接
続されると共に電源端子2に接続されるようにな
されている。
Furthermore, a capacitor 15 is connected between output terminals 13 and 14.
and 16 are connected in series, and the connection point of these capacitors 15 and 16 is connected to the connection point of the anode of the diode 12c and the cathode of the diode 12d of the bridge rectifier 12 via the switch 17, and is also connected to the power supply terminal 2. It is designed so that

尚スイツチ10及び17は、ブリツジ整流時と
倍電圧整流時を切り換えるためのもので、共にブ
リツジ整流時にはオフ、倍電圧整流時にはオンと
なるよう連動して作動するようになされている。
The switches 10 and 17 are for switching between bridge rectification and voltage doubler rectification, and are operated in conjunction so that they are turned off during bridge rectification and turned on during voltage doubler rectification.

今ブリツジ整流時には、スイツチ10及び17
がオフ状態とされるので、電源端子1の電位がプ
ラスの時には、実線の矢印で示すように電流i1
が、電源端子1より抵抗器4、ダイオード5a、
コンデンサ8,9及びダイオード5dを介して電
源端子2に流れる。一方、電源端子1の電位がマ
イナスの時には破線の矢印で示すように電流i2
が、電源端子2よりダイオード5c、コンデンサ
8,9、ダイオード5b及び抵抗器4を介して電
源端子1側に流れる。従つて出力端子6及び7に
は全波整流された第1の整流出力が得られる。
又、第2の整流出力を得るためのブリツジ整流器
12側にも電流方向は具体的に図示せずも、上述
と同様に電流が流がれ、もつて出力端子13及び
14間に全波整流された第2の整流出力が得られ
る。
Now, during bridge commutation, switches 10 and 17
is in the off state, so when the potential of power supply terminal 1 is positive, the current i 1
However, from the power supply terminal 1, the resistor 4, diode 5a,
The current flows to the power supply terminal 2 via the capacitors 8 and 9 and the diode 5d. On the other hand, when the potential of power supply terminal 1 is negative, the current i 2
flows from the power supply terminal 2 to the power supply terminal 1 side via the diode 5c, capacitors 8 and 9, diode 5b, and resistor 4. Therefore, the first full-wave rectified output is obtained at the output terminals 6 and 7.
Furthermore, although the current direction is not specifically shown, a current flows in the same manner as described above on the bridge rectifier 12 side for obtaining the second rectified output, resulting in full-wave rectification between the output terminals 13 and 14. A second rectified output is obtained.

一方倍電圧整流時には、スイツチ10及び17
がオン状態とされるので、今ブリツジ整流器12
側を用いて説明すると、電源端子1の電位がプラ
スの時には、電源端子1より実線の矢印で示す様
に電流i3が、抵抗器11、ダイオード12a、コ
ンデンサ15、スイツチ17を介して電源端子2
に流れ、一方電源端子1の電位がマイナスの時に
は破線の矢印で示すように電流i4がスイツチ1
7、コンデンサ16、ダイオード12b及び抵抗
器11を介して電源端子1側に流れる。従つて、
出力端子13及び14には倍電圧整流された第2
の整流出力を得ることができる。又主出力である
第1の整流出力を得るためのブリツジ整流器5側
にも上述と同様に電流が流がれ、従つて出力端子
6及び7間に倍電圧整流された第1の整流出力が
得られる。
On the other hand, during voltage doubler rectification, switches 10 and 17
Since the bridge rectifier 12 is turned on, the bridge rectifier 12 is now turned on.
To explain using the side, when the potential of power supply terminal 1 is positive, current i3 flows from power supply terminal 1 through resistor 11, diode 12a, capacitor 15, and switch 17 to the power supply terminal as shown by the solid arrow. 2
On the other hand, when the potential of power supply terminal 1 is negative, current i4 flows to switch 1 as shown by the dashed arrow.
7, flows to the power supply terminal 1 side via the capacitor 16, diode 12b and resistor 11. Therefore,
The output terminals 13 and 14 have a voltage doubler rectified second
rectified output can be obtained. Similarly to the above, a current also flows to the bridge rectifier 5 side for obtaining the first rectified output which is the main output, and therefore the first rectified output which has been voltage doubled and rectified is output between the output terminals 6 and 7. can get.

ところで第1図のごとき構成をなす従来回路の
場合、主出力である第1の整流出力と電位的に同
一の副出力である第2の整流出力を得るのにブリ
ツジ整流器5及び12が必要であると共に、ブリ
ツジ整流時と倍電圧整流時を切り換えるためにス
イツチ10及び17を必要とするので構成が複雑
になる共にコスト的にも高価となる等の欠点があ
つた。
By the way, in the case of the conventional circuit configured as shown in Fig. 1, the bridge rectifiers 5 and 12 are required to obtain the second rectified output, which is the sub-output, which is electrically the same as the first rectified output, which is the main output. In addition, since switches 10 and 17 are required to switch between bridge rectification and voltage doubler rectification, the structure is complicated and the cost is high.

考案の目的 この考案は斯る点に鑑み、構成簡単にして第1
の整流出力と電位的に同一の第2の整流出力、特
に倍電圧整流出力を容易に得ることのできる整流
回路を提供するものである。
Purpose of the invention In view of these points, this invention has a simple structure and is the first
The purpose of the present invention is to provide a rectifier circuit that can easily obtain a second rectified output, particularly a voltage doubler rectified output, which is electrically the same as the rectified output of the second rectified output.

考案の概要 この考案では交流電源23が接続される第1と
第2の電源端子21,22に対して第1、第2、
第3及び第4のダイオード25a〜25dよりな
るブリツジ整流器25を接続し、第1と第2のダ
イオード25a,25cの接続点を第1の出力端
子26に接続し、第3と第4のダイオード25
d,25bの接続点を共通端子である共通出力端
子27に接続し、第1の出力端子26と共通出力
端子27間に第1と第2のコンデンサ28,29
を直列接続し、第1と第2のコンデンサ28,2
9の接続点をスイツチ30を介して第2と第3の
ダイオード25c,25dの接続点に接続し、第
1の電源端子21を第5のダイオード31を介し
て第2の出力端子33に接続し、第2の出力端子
33と共通出力端子27間に第3のコンデンサ3
4を接続し、上記スイツチ30をオンオフするこ
とによりブリツジ整流と倍電圧整流とを切換える
様に構成することにより、第1の整流出力と電気
的に同一の整流出力、特に同一の複数倍電圧整流
出力を得ることができる。
Summary of the invention In this invention, the first, second,
A bridge rectifier 25 consisting of third and fourth diodes 25a to 25d is connected, the connection point of the first and second diodes 25a and 25c is connected to the first output terminal 26, and the third and fourth diodes are connected to each other. 25
The connection point of d and 25b is connected to the common output terminal 27 which is a common terminal, and the first and second capacitors 28 and 29 are connected between the first output terminal 26 and the common output terminal 27.
are connected in series, and the first and second capacitors 28, 2
9 is connected to the connection point between the second and third diodes 25c and 25d via the switch 30, and the first power supply terminal 21 is connected to the second output terminal 33 via the fifth diode 31. A third capacitor 3 is connected between the second output terminal 33 and the common output terminal 27.
4 and configured to switch between bridge rectification and voltage doubler rectification by turning on and off the switch 30, a rectification output that is electrically the same as the first rectification output, especially multiple voltage doubler rectification that is the same as the first rectification output. You can get the output.

実施例 以下、この考案の一実施例を第2図〜第7図に
基づいて詳しく説明する。
Embodiment Hereinafter, an embodiment of this invention will be described in detail based on FIGS. 2 to 7.

第2図は本実施例の回路構成を示すもので、同
図において、電源端子21及び22の両端に交流
電源23を接続し、電源端子21を抵抗器24を
介してブリツジ整流器25を構成するダイオード
25a〜25dの内のダイオード25aのアノー
ドとダイオード25bのカソードの接続点に接続
し、ダイオード25a及び25cの各カソードの
接続点を出力端子26に接続し、一方ダイオード
25b及び25dの各アノードの接続点を共通端
子である出力端子27に接続する。また出力端子
26及び27間にコンデンサ28及び29を直列
接続し、これらコンデンサ28及び29の接続点
をスイツチ30を介してダイオード25dのカソ
ード及びダイオード25cのアノードの接続点に
接続すると共に電源端子22に接続する。
FIG. 2 shows the circuit configuration of this embodiment. In the figure, an AC power supply 23 is connected to both ends of power supply terminals 21 and 22, and a bridge rectifier 25 is configured by connecting the power supply terminal 21 with a resistor 24. The connection point between the anode of the diode 25a and the cathode of the diode 25b among the diodes 25a to 25d is connected to the connection point of each cathode of the diodes 25a and 25c, and the connection point of each cathode of the diodes 25a and 25c is connected to the output terminal 26. The connection point is connected to the output terminal 27 which is a common terminal. Further, capacitors 28 and 29 are connected in series between the output terminals 26 and 27, and the connection point of these capacitors 28 and 29 is connected via a switch 30 to the connection point of the cathode of the diode 25d and the anode of the diode 25c. Connect to.

又、電源端子21をダイオード31及び抵抗器
32を介して出力端子33に接続し、この出力端
子33と共通端子27との間にコンデンサ34を
接続する。そして本実施例では出力端子26と共
通端子27との間に主出力である第1の整流出力
を得るようにすると共に出力端子33と共通端子
27との間に副出力である第2の整流出力を得る
ようにしている。尚、第1及び第2の整流出力
は、上述の構成により、電位的には同一の整流出
力であるも、波形的には前者が全波整流されたも
のであり、後者が半波整流されたものとなる。
Further, the power supply terminal 21 is connected to an output terminal 33 via a diode 31 and a resistor 32, and a capacitor 34 is connected between this output terminal 33 and the common terminal 27. In this embodiment, a first rectified output, which is the main output, is obtained between the output terminal 26 and the common terminal 27, and a second rectified output, which is the auxiliary output, is obtained between the output terminal 33 and the common terminal 27. I'm trying to get the output. Although the first and second rectified outputs are the same in terms of potential due to the above-described configuration, the former is full-wave rectified and the latter is half-wave rectified. It becomes something.

次に第2図の回路動作を第3図〜第6図に基づ
いて説明する。
Next, the operation of the circuit shown in FIG. 2 will be explained based on FIGS. 3 to 6.

先ず、ブリツジ整流時の動作を第3図及び第4
図を参照しながら説明する。ブリツジ整流時には
スイツチ30がオフ状態とされる。従つて、交流
電源23から供給される交流電圧が、電源端子2
1においてプラス(正の半サイクル)の時には、
実線の矢印で示すように電流i1が、電源端子21
より抵抗器24、ダイオード25a、コンデンサ
28,29及びダイオード25dを介して電源端
子22に流れると共に電源端子21から更に実線
の矢印で示すように電流i2がダイオード31、抵
抗器32、コンデンサ34及びダイオード25d
を介して電源端子22に流れる。従つて、この時
の電位関係は第4図に示すように、共通端子27
の電位0Vに対して出力端子26の電位を+Vと
すると、両端子間には+Vの電位差をもつた整流
出力が得られ、一方、共通端子27の電位0Vに
対して出力端子33の電位を+Vとすると、両端
子間には+Vの電位差をもつた整流出力が得られ
る。
First, the operation during bridge rectification is shown in Figures 3 and 4.
This will be explained with reference to the figures. During bridge rectification, the switch 30 is turned off. Therefore, the AC voltage supplied from the AC power supply 23 is applied to the power supply terminal 2.
When it is positive (positive half cycle) at 1,
As shown by the solid arrow, the current i 1 flows through the power supply terminal 21
The current i 2 flows through the resistor 24, the diode 25a, the capacitors 28, 29, and the diode 25d to the power supply terminal 22, and further flows from the power supply terminal 21 to the diode 31, the resistor 32, the capacitor 34, and as shown by the solid arrow. diode 25d
The current flows to the power supply terminal 22 via. Therefore, the potential relationship at this time is as shown in FIG.
When the potential of the output terminal 26 is +V with respect to the potential of 0V, a rectified output with a potential difference of +V is obtained between both terminals.On the other hand, when the potential of the output terminal 33 is When it is set to +V, a rectified output with a potential difference of +V between both terminals is obtained.

また、電源端子21の電位がマイナス(負の半
サイクル)の時には、破線の矢印で示すように電
流i3が、電源端子22よりダイオード25c、コ
ンデンサ28及びコンデンサ29、ダイオード2
5b及び抵抗器24を介して電源端子21に流れ
る。従つて、この時の電位関係は第4図に示すよ
うに出力端子26の電位0Vに対して共通端子2
7の電位を−Vとすると、両端子間には+Vの電
位差をもつた整流出力が得られ、一方、出力端子
33の電位0Vに対して共通端子27の電位を−
Vとすると、両端子間には+Vの電位差をもつた
整流出力が得られる。この結果、共通端子27と
出力端子26の間には全波整流された第1の整流
出力が得られると共に共通端子27と出力端子3
3の間には半波整流された第2の整流出力が得ら
れることになる。
Further, when the potential of the power supply terminal 21 is negative (negative half cycle), the current i 3 flows from the power supply terminal 22 to the diode 25c, the capacitor 28, the capacitor 29, and the diode 2, as shown by the broken line arrow.
5b and the resistor 24 to the power supply terminal 21. Therefore, the potential relationship at this time is as shown in FIG.
When the potential of the common terminal 27 is -V, a rectified output with a potential difference of +V is obtained between both terminals.On the other hand, the potential of the common terminal 27 is -V with respect to the potential of the output terminal 33 of 0V
When V, a rectified output with a potential difference of +V between both terminals is obtained. As a result, a full-wave rectified first rectified output is obtained between the common terminal 27 and the output terminal 26, and a first rectified output is obtained between the common terminal 27 and the output terminal 3.
3, a second half-wave rectified output is obtained.

次に倍電圧整流時の動作を第5図及び第6図を
参照しながら説明する。倍電圧整流時にはスイツ
チ30をオン状態とする。すると、電源端子21
の電位がプラス(正の半サイクル)の時には実線
の矢印で示すように電流i1が電源端子21より抵
抗器24、ダイオード25a、コンデンサ28及
びスイツチ30を介して電源端子22に流れると
共に実線の矢印で示すように電流i2が電源端子2
1よりダイオード31、抵抗器32、コンデンサ
34,29及びスイツチ30を介して電源端子2
2に流れる。従つてこの場合の電位関係は、第6
図に示すように、共通端子27の電位0Vに対し
て出力端子26の電位を+Vとすると、両端子間
には+Vの電位差をもつた整流出力が得られ、一
方、共通端子27の電位0Vに対して出力端子3
3の電位を+Vとすると、両端子間には+Vの電
位差をもつた整流出力が得られる。
Next, the operation during voltage double rectification will be explained with reference to FIGS. 5 and 6. During voltage double rectification, the switch 30 is turned on. Then, power terminal 21
When the potential of is positive (positive half cycle), the current i1 flows from the power supply terminal 21 to the power supply terminal 22 via the resistor 24, diode 25a, capacitor 28 and switch 30 as shown by the solid line arrow, and the current i1 flows to the power supply terminal 22 as shown by the solid line arrow. As shown by the arrow, current i 2 is connected to power terminal 2
1 through a diode 31, a resistor 32, capacitors 34 and 29, and a switch 30 to a power supply terminal 2.
It flows to 2. Therefore, the potential relationship in this case is the sixth
As shown in the figure, when the potential of the output terminal 26 is +V with respect to the potential of the common terminal 27 of 0V, a rectified output with a potential difference of +V is obtained between both terminals, while the potential of the common terminal 27 is 0V. Output terminal 3 for
3 is set to +V, a rectified output having a potential difference of +V between both terminals is obtained.

次に電流端子21の電位がマイナス(負の半サ
イクル)になると、破線の矢印で示すように、電
流i3が電源端子22からスイツチ30、コンデン
サ29、ダイオード25b及び抵抗器24を介し
て電源端子21に流れる。従つてこの場合の電位
関係を見ると、第6図からも解るように、出力端
子27の電位−Vに対して出力端子26の電位が
+Vとなり、両端子間には+2Vの電位差を持つ
た整流出力、すなわち倍電圧整流出力が得られ、
一方共通端子27の電位−Vに対して出力端子3
3の電位が0Vとなり、こちらの両端子間には+
Vの電位差をもつた整流出力が得られる。
Next, when the potential of the current terminal 21 becomes negative (negative half cycle), the current i 3 flows from the power supply terminal 22 through the switch 30, the capacitor 29, the diode 25b, and the resistor 24, as shown by the dashed arrow. It flows to terminal 21. Therefore, looking at the potential relationship in this case, as can be seen from FIG. A rectified output, that is, a voltage doubler rectified output, is obtained,
On the other hand, for the potential -V of the common terminal 27, the output terminal 3
The potential of 3 becomes 0V, and there is + between these two terminals.
A rectified output with a potential difference of V is obtained.

次に電源端子21の電位が反転してプラス(次
の正の半サイクル)になると上述と同様にして電
流が流れ、この時の電位関係は、第6図の右欄か
らも解る様に、出力端子27の電位−Vに対して
出力端子27の電位が+Vとなり、両端子間の電
位差が+2Vとなる。一方共通端子27の電位−
Vに対して出力端子33の電位が+Vとなり両端
子間の電位差も+2Vとなる。即ちここで初めて
出力端子33側にも倍電圧の整流出力が得られる
わけである。この結果、出力端子26と共通端子
27の間には倍電圧の第1の整流出力が得られる
と共に、出力端子33と共通端子27の間にも同
様に倍電圧の第2の整流出力すなわち第1の整流
出力と同一電圧でしかも倍電圧の整流出力が得ら
れる。そしてこの場合も前者は全波整流されたも
のであり、後者は半波整流されたものである。
Next, when the potential of the power supply terminal 21 is reversed and becomes positive (next positive half cycle), a current flows in the same manner as described above, and the potential relationship at this time is, as can be seen from the right column of FIG. The potential of the output terminal 27 becomes +V with respect to the potential of the output terminal 27 -V, and the potential difference between both terminals becomes +2V. On the other hand, the potential of the common terminal 27 -
The potential of the output terminal 33 becomes +V with respect to V, and the potential difference between both terminals also becomes +2V. That is, for the first time, a rectified output of the doubled voltage is also obtained on the output terminal 33 side. As a result, a first rectified output with doubled voltage is obtained between the output terminal 26 and the common terminal 27, and a second rectified output with doubled voltage is also obtained between the output terminal 33 and the common terminal 27. A rectified output with the same voltage as the rectified output of No. 1 and double the voltage can be obtained. Also in this case, the former is full-wave rectified, and the latter is half-wave rectified.

尚、この倍電圧整流時、即ちスイツチ30がオ
ン状態とされる場合には、第5図からも解るよう
に、ブリツジ整流器25のダイオード25c,2
5dは実質的に使用されていないことが解る。従
つてこれらのダイオード25c,25dとスイツ
チ30を削除して簡略化すると第7図に示すよう
な回路が得られる。
Incidentally, during this voltage doubler rectification, that is, when the switch 30 is turned on, the diodes 25c and 2 of the bridge rectifier 25, as can be seen from FIG.
It can be seen that 5d is not substantially used. Therefore, if these diodes 25c, 25d and switch 30 are removed and simplified, a circuit as shown in FIG. 7 can be obtained.

即ち同図において、電源端子21及び22間に
交流電源23を接続し、電源端子21をダイオー
ド25aを介して出力端子26に接続すると共
に、出力端子27をダイオード25bを介して電
源端子21に接続する。そして、出力端子26及
び27間にコンデンサ28及び29を直列接続
し、これらコンデンサ28及び29の接続点を電
源端子22に接続する。また、電源端子21をダ
イオード31を介して出力端子33に接続し、こ
の出力端子33と共通端子27の間にコンデンサ
34を接続する。
That is, in the figure, an AC power supply 23 is connected between power supply terminals 21 and 22, power supply terminal 21 is connected to output terminal 26 through diode 25a, and output terminal 27 is connected to power supply terminal 21 through diode 25b. do. Capacitors 28 and 29 are connected in series between the output terminals 26 and 27, and a connection point between these capacitors 28 and 29 is connected to the power supply terminal 22. Further, the power supply terminal 21 is connected to an output terminal 33 via a diode 31, and a capacitor 34 is connected between this output terminal 33 and the common terminal 27.

そしてこの場合の動作も第5図の回路の場合と
ほぼ同様である。即ち、電源端子21の電位がプ
ラス(正の半サイクル)の時には、実線で示す電
流i1がダイオード25a及びコンデンサ28を介
して電源端子22に流れると共に電流i2がダイオ
ード31、コンデンサ34及び29を介して電源
端子22に流れる。
The operation in this case is also almost the same as that of the circuit shown in FIG. That is, when the potential of the power supply terminal 21 is positive (positive half cycle), the current i 1 shown by the solid line flows to the power supply terminal 22 via the diode 25a and the capacitor 28, and the current i 2 flows through the diode 31, the capacitor 34, and 29. The current flows to the power supply terminal 22 via.

一方電源端子21の電位がマイナス(負の半サ
イクル)の時には、破線の矢印で示すように電流
i3が、電源端子22よりコンデンサ29及びダイ
オード25bを介して電源端子21側に流れる。
従つてこの場合も共通端子27と出力端子26と
の間には全波整流された倍電圧の第1の整流出力
が得られると共に共通端子27と出力端子33と
の間には半波整流された倍電圧の第2の整流出力
が得られる。
On the other hand, when the potential of the power supply terminal 21 is negative (negative half cycle), the current flows as shown by the dashed arrow.
i 3 flows from the power supply terminal 22 to the power supply terminal 21 side via the capacitor 29 and the diode 25b.
Therefore, in this case as well, a full-wave rectified first rectified output of the doubled voltage is obtained between the common terminal 27 and the output terminal 26, and a half-wave rectified output is obtained between the common terminal 27 and the output terminal 33. A second rectified output with a doubled voltage is obtained.

考案の効果 上述の如くこの考案によれば、交流電源23が
接続される第1と第2の電源端子21,22に対
して第1、第2、第3及び第4のダイオード25
a〜25dよりなるブリツジ整流器25を接続
し、第1と第2のダイオード25a,25cの接
続点を第1の出力端子26に接続し、第3と第4
のダイオード25d,25bの接続点を共通端子
である共通出力端子27に接続し、第1の出力端
子26と共通出力端子27間に第1と第2のコン
デンサ28,29を直列接続し、第1と第2のコ
ンデンサ28,29の接続点をスイツチ30を介
して第2と第3のダイオード25c,25dの接
続点に接続し、第1の電源端子21を第5のダイ
オード31を介して第2の出力端子33に接続
し、第2の出力端子33と共通出力端子27間に
第3のコンデンサ34を接続し、スイツチ30を
オンオフすることによりブリツジ整流と倍電圧整
流とを切換えるように構成したので、主出力であ
る第1の整流出力と電位的に同一の副出力である
第2の整流出力、特に同一の複数倍電圧の整流出
力を、従来に比し数少ない構成部品で得ることが
でき、もつて構成が簡略化されると共にコスト的
にも廉価となる。
Effects of the invention As described above, according to this invention, the first, second, third and fourth diodes 25 are connected to the first and second power supply terminals 21 and 22 to which the AC power supply 23 is connected.
A bridge rectifier 25 consisting of diodes a to 25d is connected, the connection point between the first and second diodes 25a and 25c is connected to the first output terminal 26, and the third and fourth diodes are connected to each other.
The connection point of the diodes 25d and 25b is connected to the common output terminal 27, which is a common terminal, and the first and second capacitors 28 and 29 are connected in series between the first output terminal 26 and the common output terminal 27. The connection point between the first and second capacitors 28 and 29 is connected via the switch 30 to the connection point between the second and third diodes 25c and 25d, and the first power supply terminal 21 is connected via the fifth diode 31. A third capacitor 34 is connected between the second output terminal 33 and the common output terminal 27, and the switch 30 is turned on and off to switch between bridge rectification and voltage doubler rectification. With this configuration, it is possible to obtain a second rectified output as a sub-output having the same potential as the first rectified output as the main output, especially a rectified output with the same multiple voltage multipliers, with fewer components than in the past. This simplifies the configuration and reduces costs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来回路の一例を示す接続図、第2図
はこの考案の一実施例を示す接続図、第3図及び
第5図は夫々第2図の動作説明に供するための接
続図、第4図及び第6図は夫々第3図及び第5図
の動作説明に供するための線図、第7図はこの考
案の他の実施例を示す接続図である。 23は交流電源、25はブリツジ整流器、2
6,33は出力端子、27は共通端子、28,2
9,34はコンデンサ、30はスイツチ、31は
ダイオードである。
FIG. 1 is a connection diagram showing an example of a conventional circuit, FIG. 2 is a connection diagram showing an embodiment of this invention, and FIGS. 3 and 5 are connection diagrams for explaining the operation of FIG. 2, respectively. 4 and 6 are diagrams for explaining the operations of FIGS. 3 and 5, respectively, and FIG. 7 is a connection diagram showing another embodiment of this invention. 23 is an AC power supply, 25 is a bridge rectifier, 2
6, 33 are output terminals, 27 is a common terminal, 28, 2
9 and 34 are capacitors, 30 is a switch, and 31 is a diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 交流電源が接続される第1と第2の電源端子に
対して第1、第2、第3及び第4のダイオードよ
りなるブリツジ整流器を接続し、第1と第2のダ
イオードの接続点を第1の出力端子に接続し、第
3と第4のダイオードの接続点を共通端子である
共通出力端子に接続し、第1の出力端子と共通出
力端子間に第1と第2のコンデンサを直列接続
し、第1と第2のコンデンサの接続点をスイツチ
を介して第2と第3のダイオードの接続点に接続
し、第1の電源端子を第5のダイオードを介して
第2の出力端子に接続し、第2の出力端子と共通
出力端子間に第3のコンデンサを接続し、上記ス
イツチをオンオフすることによりブリツジ整流と
倍電圧整流とを切換えるようにした整流回路。
A bridge rectifier consisting of first, second, third, and fourth diodes is connected to the first and second power supply terminals to which the AC power supply is connected, and the connection point of the first and second diodes is connected to the first and second power supply terminals. Connect the connection point of the third and fourth diodes to the common output terminal, which is the common terminal, and connect the first and second capacitors in series between the first output terminal and the common output terminal. The connection point of the first and second capacitors is connected to the connection point of the second and third diodes through a switch, and the first power supply terminal is connected to the second output terminal through a fifth diode. , a third capacitor is connected between the second output terminal and the common output terminal, and switching between bridge rectification and voltage doubler rectification is achieved by turning the switch on and off.
JP19904882U 1982-12-23 1982-12-23 rectifier circuit Granted JPS5999694U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19904882U JPS5999694U (en) 1982-12-23 1982-12-23 rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19904882U JPS5999694U (en) 1982-12-23 1982-12-23 rectifier circuit

Publications (2)

Publication Number Publication Date
JPS5999694U JPS5999694U (en) 1984-07-05
JPH0145266Y2 true JPH0145266Y2 (en) 1989-12-27

Family

ID=30424599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19904882U Granted JPS5999694U (en) 1982-12-23 1982-12-23 rectifier circuit

Country Status (1)

Country Link
JP (1) JPS5999694U (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51156423U (en) * 1975-06-06 1976-12-13
JPS5771272A (en) * 1980-10-17 1982-05-04 Hitachi Ltd Rectifying circuit

Also Published As

Publication number Publication date
JPS5999694U (en) 1984-07-05

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