JPH0144051B2 - - Google Patents

Description

Detailed Description of the Invention The present invention is mainly used in an A/D converter etc. realized on a semiconductor integrated circuit with a complementary insulated gate configuration, and compares two voltages with a small difference and calculates the voltage according to the magnitude of the difference. The present invention relates to a voltage comparison circuit suitable for outputting a logic voltage.

Conventionally, a voltage comparator circuit used in a semiconductor integrated circuit with a complementary insulated gate configuration has been configured with M1 as a current source, M2 and M3 as input transistors, and M4 and M5 as current mirror loads, as shown in Figure 1. A two-stage amplifier circuit that extracts an output voltage proportional to the difference between the voltages applied to terminals 2 and 3 by a differential amplifier 10 from a terminal 6, and further amplifies this by an inverting amplifier 11 with M6 as a constant current load. was using.

Symbols used in this application, including FIG. 1, define an n-channel transistor as shown in FIG. 2a, and a P-channel transistor as shown in FIG. 2b.
The gate is denoted by G, the source is denoted by S, and the drain is denoted by D. This two-stage amplifier circuit usually provides a gain of 2,000 to 5,000 times, but in order to obtain a gain margin, an inverting amplifier 12 consisting of transistors M8 and M9 is usually added.
One stage is added. 13 is a bias voltage supply circuit for operating M1 and M6 in a constant current region.

In such a voltage comparator circuit, when the input voltage is decreased, the number of amplification stages must be increased accordingly, resulting in an increase in the area occupied within the integrated circuit and an increase in power consumption. Furthermore, the common-mode voltage rejection of the first-stage differential amplifier is not perfect, and if the common-mode component of the input voltage changes, the output voltage at node 6 changes, and this voltage is amplified by the inverting amplifier, so the input power is
In the case of a voltage difference of less than mV, depending on the common mode voltage, the final stage output may be in a logic “1” state or a logic “0” state.
The state of may change. The same phenomenon also occurs when the power supply voltage fluctuates. Therefore,
In such a voltage comparison circuit, it is difficult to compare voltages of 1 mV or less when the common mode voltage of the input voltage changes significantly or when there is a lot of noise in the power supply.
Furthermore, the most important thing is that it is very difficult to match the operating center voltage of the differential amplifier 10 and the operating center voltage of the inverting amplifier 11;
A deviation of 100 mV is normal, and this results in an input offset voltage of around 10 mV. This cannot be controlled with current technology. Therefore, it is necessary to compare voltages that include offsets, and there is a drawback that comparisons based on true voltage differences cannot be performed.

As another voltage comparison method, for example, there is a circuit as shown in Fig. 3, which was presented at the ISSCC by Deingwall in 1979. （´79ISSCC Digest of
(Technical papers pp126) The details of the operation of this circuit are described in the above-mentioned document and will be omitted here. In this circuit, the input voltage from terminals 102 and 103 in the figure is applied to transistors M10, M11 or M1.
2 and M13, which conduct alternately, to one electrode of a capacitor C1, and the other electrode of the capacitor C1 is connected to the input terminal of an inverting amplifier constituted by transistors M14 and M15. The input terminal and output terminal of this inverting amplifier are made conductive and non-conductive in synchronization with the switch. In the figure, φ indicates mutually complementary clocks. For example, when the switch connected to the input terminal 103 is conductive, the switch consisting of transistors M16 and M17 connected between the input terminal 105 and the output terminal 106 of the inverting amplifier is also conductive, and the potential of the terminals 105 and 106 is changed. Equal potential. Next, when the switch connected to the input terminal 102 side is made conductive and the other two switches are made non-conductive, the potential at the terminal 104 changes by the difference between the voltage at the terminal 102 and the voltage at the terminal 103. This change is C1
to the inverting amplifier through the output 106.
This change is then amplified several dozen times and output. The voltage difference between terminals 102 and 103 is therefore amplified. Although this circuit appears simple, it requires a size several times the size of capacitor C1. Further, the gain of the inverting amplifier is several tens of times at most, and when the input voltage difference is less than 1 mV, the output voltage is not sufficient to operate the logic circuit, so the latch 107 also requires a considerable amount of amplification. Furthermore, since the time at which the voltage at the terminal 103 is sampled and the time at which the voltage at the terminal 102 is sampled are different, if the power supply voltage fluctuates at both times, that voltage will be treated equally as the signal input voltage. Therefore, it has the disadvantage of being extremely susceptible to power supply noise.

The present invention aims to eliminate such drawbacks and realize a voltage comparator circuit with very high sensitivity using a small number of elements.

The present invention provides a first flip-flop constituted by a pair of cross-coupled first and second field effect transistors of one conductivity type; third and fourth field effect transistors of the same polarity, each having one end connected to the source electrodes of the third and fourth transistors and the other end having equal resistance values connected to the common source of the first flip-flop. a second flip-flop constituted by first and second resistors, a pair of cross-coupled fifth and sixth field effect transistors having different polarities from the first flip-flop; Seventh and eighth field effect transistors having the same source and drain as the constituent transistors and having the same polarity as the second flip-flop, one each of the pair of drain electrodes of the first flip-flop and the pair of drain electrodes of the second flip-flop. Ninth and tenth field effect transistors having the same polarity as the transistor constituting the first flip-flop and having source and drain electrodes, respectively, and means for generating a pulse;
The gate electrodes of the eighth, ninth and tenth transistors are connected to the pulse generating means, and the third
and a voltage comparison circuit, characterized in that the gate electrode of the fourth transistor is used as a signal input terminal, and the drain electrodes of the ninth and tenth transistors are used as output terminals.

Hereinafter, the present invention will be described in detail using drawings showing embodiments. FIG. 4 is a circuit diagram showing an embodiment of the present invention. This circuit includes a flip-flop composed of n-channel MOS transistors T1 and T2, n-channel MOS transistors T3 and T4 whose drains are common to T1 and T2,
Connect one end to the sources of T3 and T4, and connect the other end to the T3 and T4 sources.
A flip-flop is constructed of resistors R1 and R2 having equal resistance values connected to the common sources of T5 and T2, and p-channel MOS transistors T5 and T6, and a p-channel MOS transistor T7 connected in parallel to T5 and T6, respectively. T8
and n-channel MOS transistors T9 and T10 whose source and drain are one of the drain electrodes of T1 and T2 and one of the pair of drain electrodes of T5 and T6, respectively, and the gate electrodes of T7, T8, T9 and T10 are connected to the terminal 208 for pulse generation. It is configured to be connected to a means for generating. The voltages to be compared are applied to the gate electrodes 202 and 203 of T3 and T4, respectively. Also, in this circuit, terminal 20
1 is connected to the positive power supply _VDD , and the terminal 209 is grounded.

This circuit initially starts with a pulse voltage of zero. In this state, T3, T4, T7, and T8 are in a conductive state, and T9 and T10 are non-conductive. Therefore, the voltage appearing at the output terminals 206, 207 is the power supply voltage V _DD which is equal to the potential of the power supply terminal 201. Further, the nodes 204 and 205 are at zero potential. Next, when a positive pulse is applied to the terminal 208, T9,
T10 is conductive, T7 and T8 are non-conductive, and T
Current flows into the drains of the flip-flops T1 and T2 through T9 and T10. At this time, terminal 2
Assuming that the potential of 02 is higher than the potential of 203, the current flowing through transistor T3 is greater than the current flowing through transistor T4. No current flows through T1 and T2 until the potential at node 205 or 204 exceeds the threshold voltage, respectively. In the initial stage when T9 and T10 become conductive, nodes 204 and 205 are similarly charged, but since node 204 has a larger discharge amount, node 205 exceeds the threshold voltage first. Then, T1 also becomes conductive and starts discharging, and the potential at node 204 no longer increases, but instead decreases. That is, the flip-flops T1 and T2 operate. Here, R1 and R2 are resistors for expanding the input voltage range by preventing excessive current from flowing through T3 and T4 when the input voltage to be compared becomes high.This resistor is used to keep the gate voltage constant. A voltage biased transistor may also be used. This resistance value is determined so that T3 and T4 operate in the pentode region during voltage comparison. Since the discharge current at node 204 is greater than the discharge current at node 205, the current flowing through T5 is greater than the current flowing through T6. Then, the flip-flop constituted by T5 and T6 also operates, accelerating the drop in potential at the output terminal 206, and the voltage rapidly drops to the ground potential.
Then the voltage drop due to T6 becomes very small,
Since T5 is made non-conductive, no current flows through T5. In this way, the state of the output voltage is determined according to the input voltage. Since its operation consists of a double flip-flop, the time required from applying a pulse until the state is determined can be as fast as 20 ns or less even if a MOS transistor with a channel length of about 6 microns is used. Furthermore, since the arrangement is completely symmetrical from input to output, the cause of offset voltage, which is a drawback in conventional circuits, can be eliminated. Furthermore, power supply noise is canceled because it affects both input voltages equally, and there is no risk of malfunction due to noise. Further, since positive feedback is provided by the flip-flop, the gain is infinite, and even if the input voltage is 1 mV or less, a voltage output sufficient for the logic amplitude can be obtained as an output.

Returning to the initial state returns the pulse to zero. Then, T9 and T10 become non-conductive, and T
7, T8 is conductive. Then, nodes 206, 20
7 are quickly charged through T7 and T8, respectively, to return to the supply voltage _VDD . This recovery time can easily be reduced to 10 ns or less using the circuit of the present invention.
Furthermore, the upper limit of the common mode input voltage can be up to the power supply voltage.

This circuit consumes no current at all in its initial state. Also, even during comparison operation, T4 or T
Since only one side of the circuit 5 is allowed to flow, it consumes only a very small amount of current, and has the advantage that the power consumption is less than 1/10 of the conventional circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a comparator circuit that combines a differential amplifier 10 and inverting amplifiers 11 and 12 according to the prior art. FIG. 2a shows a channel transistor, and FIG. 2b shows a p-channel transistor. Figure 3 shows another conventional technology, an inverting amplifier,
A circuit diagram showing a comparator using a transfer gate as a switch. FIG. 4 is a diagram showing a circuit as one embodiment of the present invention. M1 to M17, T1 to T10...MOS transistor, R1, R2...resistance.

Claims (1)

[Claims] 1. A first flip-flop constituted by a pair of cross-coupled first and second field effect transistors of one conductivity type, and a transistor constituting this flip-flop having a common drain and having the same polarity as the first flip-flop. 3rd and 4th
and first and second resistors having equal resistance values, each having one end connected to the source electrode of the third and fourth transistors and the other end connected to a common source of the first flip-flop. , a second flip-flop constituted by a pair of cross-coupled fifth and sixth field effect transistors having a polarity different from that of the first flip-flop; and a transistor constituting the second flip-flop, a source and a drain. seventh and eighth field effect transistors which are common and have the same polarity as the second flip-flop; one side of the pair of drain electrodes of the first flip-flop and the pair of drain electrodes of the second flip-flop are respectively used as a source electrode and a drain electrode of the first flip-flop; 9th and 10th field effect transistors having the same polarity as the transistors constituting the flip-flop, and means for generating a pulse, and the gate electrodes of the seventh, eighth, ninth and tenth transistors are connected to the pulse generator. 1. A voltage comparator circuit connected to means for generating , wherein the gate electrodes of the third and fourth transistors serve as signal input terminals, and the drain electrodes of the ninth and tenth transistors serve as output terminals.