JPH0144022B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a complementary semiconductor integrated circuit comprising a P-channel MOSFET and an N-channel MOSFET, and more particularly to a complementary semiconductor integrated circuit with improved latch-up generation voltage at a power supply terminal. It is.

[Prior Art] In complementary semiconductor integrated circuits, latch-up may occur due to noise applied to the power supply line. These include things that occur in circuits, such as output buffers, and things that occur between peripheral circuits and internal circuits. Latch-ups that occur in peripheral circuits or between peripheral circuits and internal circuits can be prevented by increasing the distance between the transistors that cause the latch-up, or by providing a guard with a potential such as V _CC level or GND level. , it is possible to deal with the latch-up voltage of the power supply terminal relatively easily.

On the other hand, regarding latch-up that occurs in internal circuits, generally speaking, due to the need to increase the degree of integration in this type of circuit, the P-channel MOSFET and N-channel MOSFET that make up the internal circuit
It is not easy to provide sufficient space between the MOSFET and a sufficient guard between them.

Conventionally, countermeasures have been taken to improve the latch-up voltage at the power supply terminals by adding a resistor, etc. to the power supply line that supplies power to the internal circuit, or by supplying the source potential of the MOSFET in the internal circuit through a well or substrate. It has been taken.

FIG. 1 schematically shows an example of the above countermeasures in which a diffused resistor is added to the power supply line that supplies power to the internal circuit. Below, the complementary semiconductor integrated circuit is P
An example will be explained in which the method is an N-type well type having a type substrate and a P-type substrate is electrically connected to the GND potential. In Figure 1, 1 is a V CC terminal which is a power supply terminal for externally applying a positive potential V _CC with respect to the GND potential of a complementary semiconductor integrated circuit (not shown), and 2 is a V _CC terminal from an appropriate location. A peripheral power supply line that supplies a potential to peripheral circuits such as an output buffer of a semiconductor integrated circuit; 3 is an N-type diffused resistor;
4 is a power supply line that electrically connects the V _CC terminal 1 and the N diffused resistor 3, 5 is an internal power supply line that supplies potential to the internal circuit from an appropriate point, and 6 is a P-type board that has the same potential as the GND potential. (not shown) and the N-type diffused resistor 3.

In FIG. 1, a peripheral power supply line 2, a power supply line 4, and an internal power supply line 5 are usually formed using a wiring material mainly made of metal such as aluminum, and have a finite resistance value. Further, the power supply line 4 is often branched from the vicinity of the V _CC terminal 1. Further, the parasitic diode 6 becomes reverse biased when a positive voltage with respect to the GND potential is applied to the V _CC terminal 1. For example, peripheral output buffers and internal circuits are electrically connected to the peripheral power supply line 2 and the internal power supply line 5, respectively, and generally N
Since the potential of the type well is also supplied from the power supply line, the well capacitance of the N type well with respect to the substrate is electrically connected to the peripheral power supply line 2 and the internal power supply line 5.

Let us now consider the case where pulse-like noise having a positive value is applied to the V _CC terminal 1 in a manner superimposed on the V _CC voltage level. Note that here we will only consider the latch-up that occurs in the internal circuit. When a noise voltage is superimposed and applied to the V _CC terminal 1, the applied noise voltage may be caused by a voltage drop due to the N-type diffused resistor 3, a breakdown of the reverse biased parasitic diode 6, or a breakdown of the peripheral power supply line 2 or internal Unless sufficient absorption is achieved by the resistance and capacitance components associated with the power supply line 5, latch-up will occur in the internal circuit due to carriers injected from the internal power supply line 5 into the well or substrate.

For example, as a method to sufficiently absorb noise voltage having a positive value applied to V _CC terminal 1,
First, it is possible to make the resistance value of the N-type diffused resistor 3 sufficiently large, but this method increases the resistance component of the power source impedance of the internal circuit, which mainly limits the operating speed of the internal circuit.

Furthermore, if the breakdown voltage of the reverse-biased parasitic diode 6 can be lowered, the noise applied from the outside to the V _CC terminal 1 can be reduced by the breakdown operation of the parasitic diode 6. The breakdown voltage of the diode 6 is determined by the manufacturing process, and if it is set too low, the upper limit of the operating voltage of the entire semiconductor integrated circuit will be restricted. Additionally, if a noise voltage with a positive value is applied that is sufficient to cause this breakdown, carriers may be injected from the junction with the substrate, which may further cause latch-up. .

Also, as a component that absorbs the noise voltage applied to the V _CC terminal 1, there is a capacitance attached to the peripheral power supply line 2, but when the power supply line 4 is taken from near the V _CC terminal 1, the peripheral power supply Since the line 2 has a finite resistance value, the filter effect due to the impedance of the peripheral power supply line 2 itself cannot be fully utilized, and the effect as a countermeasure against latchup is weak. In other words, the voltage value of the noise applied to the N-type diffused resistor 3 will not be sufficiently lower than that of the V _CC terminal 1, and the voltage value of the noise applied to the V CC terminal 1 will not be sufficiently lower than that of the V _CC terminal 1 due to the impedance attached to the peripheral power supply line 2. Before the noise voltage is absorbed, the noise voltage becomes N
Therefore, the potential of the internal power supply line 5 connected to the output side of the N-type diffused resistor 3 fluctuated, and the latch-up voltage was not sufficiently improved.

Another method for making latch-up less likely to occur in the internal circuit and improving the latch-up voltage seen from the power supply terminal is to supply the source potential through the well or substrate as described above. In this case, in P-type substrate N-well type circuits, the source potential of the N-channel MOSFET is generally supplied from the substrate, and this is because the lateral This is equivalent to adding a resistor to the emitter of the NPN transistor that exists in the direction, and by making it difficult for the NPN transistor to become active,
This prevents latch-up from occurring.
However, although this method can improve the latch-up voltage of the internal circuit as seen from the power supply terminal, it has drawbacks such as a reduction in the operating speed of the circuit and a tendency to cause malfunctions because the circuit propagation characteristics are no longer steep. It was hot.

[Summary of the invention]

The present invention has been made in view of the above points, and is configured to supply power from the peripheral power supply system to the internal circuitry by the internal power supply system in a complementary semiconductor integrated circuit, and to supply power to the internal circuit by the internal power supply system. It is an object of the present invention to provide a complementary semiconductor integrated circuit which can suppress the occurrence of latch-up in an internal circuit by providing attenuation means for actively attenuating the noise voltage and supplying the noise voltage to the internal power supply system.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows a complementary semiconductor integrated circuit according to an embodiment of the present invention, and this is an example applied to a complementary semiconductor integrated circuit having a P-type substrate and an N-type well structure, and the substrate is a complementary semiconductor integrated circuit. integrated circuit
Assume that it is electrically connected to the GND line. In the figure, the same reference numerals as in FIG. 1 indicate the same elements as in the same figure, and 7 is an N-channel MOSFET, the drain of which is electrically connected to V _CC terminal 1, and the source of the complementary semiconductor integrated circuit. It is connected to the GND line, and its gate is electrically connected to its source. Reference numeral 8 denotes a resistance component that electrically connects the peripheral power supply line 2 and the internal power supply line 5. 9 is an N channel whose drain is electrically connected to the internal power supply line 5 side of the resistance component 8.
MOSFET, which is the N channel mentioned above.
Similar to MOSFET7, its source is electrically
It is connected to the GND line, and its gate is electrically connected to its source.

Next, the operation will be explained.

In this circuit, noise is attenuated using four methods.

That is, in FIG. 2, the first circuit that functions to attenuate noise is the N-channel MOSFET 7.
This is mainly due to the complementary semiconductor integrated circuit.
This is to attenuate the noise voltage applied to the V _CC terminal 1 from the outside. That is, a noise voltage with a positive value is applied to V _CC terminal 1, and the N channel
In MOSFET 7, when the voltage between its drain and source exceeds its breakdown voltage, N-channel MOSFET 7 breaks down, thereby attenuating the noise voltage on peripheral power supply line 2.

The reason why the N-type diffused resistor 3 shown in FIG. 1 is not used to perform this function is that the N-channel
By shortening the gate length of MOSFET7,
The reason is that the breakdown voltage can be made lower than the breakdown voltage using the parasitic diode 6 in the N-type diffused resistor 3. Also, it is desirable to lower the impedance of the N-channel MOSFET 7 during breakdown, but to do so, the gate width of the N-channel MOSFET 7 can be made longer, and this will result in a larger drain-to-gate capacitance. can be added to the peripheral power supply line 2.

On the other hand, a complementary semiconductor integrated circuit is connected to V _CC terminal 1.
When a noise voltage having a negative value with respect to the GND potential is applied and its value reaches a value sufficient to make the N-channel MOSFET 7 conductive, the N-channel MOSFET 7 becomes conductive.
MOSFET 7 becomes conductive, and the noise voltage applied to V _CC terminal 1 is attenuated. At this time, N channel
Since MOSFET 7 functions as a normal MOS transistor, it becomes conductive in a short time. N channel
Since the MOSFET 7 is added for the purpose of absorbing the noise voltage applied to the V _CC terminal 7 in this way, it is desirable to add it at a position where the impedance is small when viewed from the V _CC terminal 1.

Further, in FIG. 2, a second circuit having the function of attenuating the noise applied to the V _CC terminal 1 is located on the peripheral power supply line 2. That is, peripheral power line 2
Generally, circuits with large N-type wells such as output buffers, input/output buffers, or input protection diodes are connected to the circuit, and the capacitance between the well and the board is inevitably added to the peripheral power supply line 2. It turns out. Further, the peripheral power supply line 2 is generally made of a low-resistance metal wiring mainly made of aluminum or the like, and has a finite resistance value itself. Therefore, the connection point between the resistance component 8 and the peripheral power supply line 2 is
By setting it at a location where the impedance is large when viewed from the V _CC terminal 1, a filter circuit consisting of the resistance and capacitance of the peripheral power supply line 2 itself can be constructed.

Furthermore, in FIG. 2, the third circuit having the function of attenuating noise is the resistive component 8. That is, the resistance component 8 has the function of attenuating the noise component riding on the peripheral power supply line 2 by its voltage drop. Generally, the peripheral power supply line 2 has a large capacitance component, but a small resistance component, so the resistance component 8 serves to supplement this. As a method of configuring the resistance component 8,
For example, polysilicon, N-type diffusion, etc. can be used. In the case of polysilicon, carrier injection due to its own breakdown does not occur, as occurs, for example, with N-type diffused resistors. Furthermore, when the resistance component is formed by diffusion, such as N-type diffusion, it is possible to further add junction capacitance to the junction portion.

Furthermore, in FIG. 2, the fourth circuit that functions to attenuate noise is an N-channel
It is MOSFET9. This N-channel MOSFET
The first function of element 9 is to configure a filter mainly consisting of resistance and capacitance together with resistance component 8 due to its drain-gate capacitance. The second function of the N-channel MOSFET 9 is to prevent noise applied externally to the complementary semiconductor integrated circuit from V _CC
For example, the peripheral power supply line 2 near the resistance component 8 comes in not only from the terminal 1 but also from the output terminal, input/output terminal, or input terminal.
In addition, the noise applied to the above-mentioned terminal may be added to the MOSFET 7, and this is attenuated by the same operation as the N-channel MOSFET 7.

With the above circuit, potential fluctuations on the peripheral power line 2 caused mainly by noise voltage applied to the power supply terminal 1 are sufficiently attenuated in the internal power supply line 5, and therefore the latch-up voltage at the power supply terminal is sufficiently improved. Become.

In this circuit as described above, the resistance and capacitance components of the complementary semiconductor integrated circuit itself are utilized, and a circuit for attenuating noise is added, so that the noise applied to the V _CC pin in the complementary semiconductor integrated circuit is reduced. The resulting latch-up voltage can be improved.

In addition, in this circuit, in order to suppress the occurrence of latch-up, the noise on the internal power supply line is attenuated. This means that there is no need to take measures against latch-up, which worsens the situation.

In the above embodiment, a P-type substrate N-well type circuit was described, but the present invention is applicable to, for example, an N-type substrate P.
It can be used in any complementary semiconductor integrated circuit such as a well type semiconductor integrated circuit.

Furthermore, in the above embodiment, a method of improving the latch-up voltage mainly caused by noise applied to the V _CC terminal was shown by combining four methods, but the present invention does not require the use of all of these methods, and any combination of four methods can be used. It is also possible to implement it in combination, and therefore, the present invention naturally includes the case where the resistance component 8 is not used.

Further, in the above embodiment, the resistance component and capacitance component of the peripheral power supply line are used, but a capacitance load may be created to add a new capacitance component, for example. Furthermore, although the peripheral power supply line is used in the above embodiment, a new circuit having a corresponding resistance or capacitance component may be added.

Furthermore, in the above embodiment, N-channel MOSFET 7
Although only one is added to the peripheral power supply line, one or more may be added to the peripheral power supply line. In addition, in the above embodiment, only one N-channel MOSFET 9 was added, but
One or more of these may be added on the internal power supply line.

〔Effect of the invention〕

As described above, according to the complementary semiconductor integrated circuit according to the present invention, the internal power supply system is provided to feed the voltage from the peripheral power supply system to the internal circuit, and the voltage of the peak peripheral power supply system is actively reduced by the noise voltage. Since the attenuation means is provided to attenuate the power and supply it to the internal power supply system, it is possible to sufficiently prevent the occurrence of latch-up in the internal circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional complementary semiconductor integrated circuit, and FIG. 2 is a block diagram of a complementary semiconductor integrated circuit according to an embodiment of the present invention. 1...V _CC terminal (power supply terminal), 2...Peripheral power supply line (peripheral power supply system), 5...Internal power supply line (internal power supply system), 7...N-channel MOSFET, 8
...Resistance component, 9...N-channel MOSFET. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. In a complementary semiconductor integrated circuit comprising an internal circuit and a peripheral circuit, a peripheral power supply system that supplies voltage applied to a power supply terminal from the outside to the peripheral circuit;
The device is characterized by comprising: an internal power supply system that supplies the voltage of the peripheral power supply system to the internal circuit; and attenuation means that attenuates voltage fluctuations in the voltage of the peripheral power supply system and supplies the voltage to the internal power supply system. Complementary semiconductor integrated circuit. 2. The complementary semiconductor integrated circuit according to claim 1, wherein the attenuation means is a normally cut-off MOSFET electrically connected between the peripheral power supply system and its return line. 3. The complementary semiconductor integrated circuit according to claim 1, wherein the attenuation means is a resistance component provided at a location where the impedance of the peripheral power supply system becomes high when viewed from the power supply terminal. 4 The attenuation means is electrically connected between the internal power supply system and the return line and is in a normally cut-off state.
The complementary semiconductor integrated circuit according to claim 1, which is a MOSFET.