JPH0142053Y2 - - Google Patents
Info
- Publication number
- JPH0142053Y2 JPH0142053Y2 JP3809377U JP3809377U JPH0142053Y2 JP H0142053 Y2 JPH0142053 Y2 JP H0142053Y2 JP 3809377 U JP3809377 U JP 3809377U JP 3809377 U JP3809377 U JP 3809377U JP H0142053 Y2 JPH0142053 Y2 JP H0142053Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- under test
- switch
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005259 measurement Methods 0.000 claims description 14
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 9
- 238000012360 testing method Methods 0.000 claims description 9
- 238000004804 winding Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
Description
【考案の詳細な説明】
本考案は、漂遊容量の影響を除去するオフセツ
ト補正回路を具えた回路素子定数測定装置に係
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit element constant measuring device equipped with an offset correction circuit that eliminates the influence of stray capacitance.
回路素子たる抵抗器、コンデンサ、インダクタ
等の定数を測定する回路素子定数測定装置は周知
である(例えば、特公昭50−27741号、特公昭53
−9539号)。かような測定装置には、測定線路に
分布する容量の影響を除去せんがためのオフセツ
ト補正回路を具えている。またこの容量は経時的
に装置の周囲温度等で変化するため、前記オフセ
ツト補正の設定を経時的にやり直す必要があつ
た。 Circuit element constant measuring devices for measuring the constants of circuit elements such as resistors, capacitors, and inductors are well known (for example, Japanese Patent Publication No. 50-27741, Japanese Patent Publication No. 53
-9539). Such a measuring device is equipped with an offset correction circuit for eliminating the influence of capacitance distributed on the measuring line. Furthermore, since this capacity changes over time due to factors such as the ambient temperature of the device, it is necessary to re-set the offset correction over time.
本考案は上記欠点を解消するためになされたも
ので、被測定素子が逐時接続される度に自動的に
オフセツト補正がなされる回路素子定数測定装置
を提供せんとするものである。 The present invention has been devised to eliminate the above-mentioned drawbacks, and is intended to provide a circuit element constant measuring device that automatically performs offset correction each time a device under test is connected.
図は本考案の一実施例による回路素子定数測定
装置の回路図である。図において、一方の測定端
子11は同期整流器13の一方の入力端子15
に、また他方の測定端子17は標準素子(抵抗
器)19を介して同期整流器13の他方の入力端
子21にそれぞれ接続される。同期整流器13の
出力端子は計算回路23に接続されると共に、開
閉スイツチ25、ホールドコンデンサ27、入力
インピーダンスが十分に大きい高利得増幅器29
で構成される電圧保持回路31に接続される。電
圧保持回路31の出力端子は、オフセツト制御回
路33における抵抗器34を介し、更に変成器3
5の中間タツプが接地された二次巻線の両端子に
それぞれ電圧可変容量素子37およびコンデンサ
39を介して接続される。電圧可変容量素子3
7、コンデンサ39の共通接続点41は測定端子
17と標準素子19との共通接続点43に直流阻
止用コンデンサ45を介して接続される。測定端
子11に接続された入力端子61には測定電圧源
1から交流電圧erが供給される。共通接続点43
は仮想接地となるようになつている。なお、この
理由については前記特許公告公報にも詳述されて
いるが、これを略記すれば次のとおりである。共
通接続点43に生じた電圧は一方の入力端子が接
地された高増幅度を持つ増幅器(例えば、演算増
幅器や、AC→DC→AC変換形増幅器)で検出、
増幅される。そして該増幅器の出力は標準素子1
9の他方の端子63に与えられ、測定端子11,
17間に流れる電流と標準素子19に流れる電流
とが等しくなるように、換言すれば共通接続点4
3の電圧が零電圧(仮想接地)となるように制御
される。また、端子61と接地との間に変成器3
5の1次巻線が接続される。なおスイツチ51,
53の開閉動作はタイミング回路65によつて制
御されて、被測定素子(ここではコンデンサ)6
7が逐時測定端子11,17間に接続される。な
お、スイツチ51,53は必ずしも必要ではな
く、被測定素子67を測定端子11,17間に接
続する動作が可能であればよい(例えば、手動操
作による)。 The figure is a circuit diagram of a circuit element constant measuring device according to an embodiment of the present invention. In the figure, one measurement terminal 11 is one input terminal 15 of the synchronous rectifier 13.
In addition, the other measurement terminal 17 is connected to the other input terminal 21 of the synchronous rectifier 13 via a standard element (resistor) 19. The output terminal of the synchronous rectifier 13 is connected to a calculation circuit 23, as well as an on/off switch 25, a hold capacitor 27, and a high gain amplifier 29 with a sufficiently large input impedance.
It is connected to a voltage holding circuit 31 consisting of. The output terminal of the voltage holding circuit 31 is connected to the transformer 3 via the resistor 34 in the offset control circuit 33.
The intermediate tap 5 is connected to both terminals of the grounded secondary winding via a voltage variable capacitance element 37 and a capacitor 39, respectively. Voltage variable capacitance element 3
7. A common connection point 41 of the capacitor 39 is connected to a common connection point 43 between the measurement terminal 17 and the standard element 19 via a DC blocking capacitor 45. An input terminal 61 connected to the measurement terminal 11 is supplied with an AC voltage e r from the measurement voltage source 1 . Common connection point 43
has become a virtual ground. The reason for this is also explained in detail in the above-mentioned patent publication, but it can be abbreviated as follows. The voltage generated at the common connection point 43 is detected by an amplifier with a high amplification degree (for example, an operational amplifier or an AC→DC→AC conversion type amplifier) whose one input terminal is grounded.
amplified. And the output of the amplifier is standard element 1
9 to the other terminal 63 of the measuring terminal 11,
In other words, the common connection point 4
The voltage of No. 3 is controlled to be zero voltage (virtual ground). Also, the transformer 3 is connected between the terminal 61 and the ground.
5 primary windings are connected. In addition, switch 51,
The opening/closing operation of 53 is controlled by a timing circuit 65, and the device under test (here, a capacitor) 6
7 is connected between the successive measurement terminals 11 and 17. Note that the switches 51 and 53 are not necessarily necessary, and may be sufficient as long as they are capable of connecting the device to be measured 67 between the measurement terminals 11 and 17 (for example, by manual operation).
次に上記構成の動作を説明する。先ず、スイツ
チ51,53を開いた状態でスイツチ25を閉じ
る補正モードについて説明する。この場合端子6
3における電圧ex1は、
ex1=jωC0・1/Gr・er (1)
となる。ここで。C0は測定端子11,17間の
漂遊容量値、Grは標準素子19のコンダクタン
スである。すなわち、電圧ex1は漂遊容量のアド
ミタンスに比例しているので、電圧er(一定)を
基準として電圧ex1を同期整流器13で整流する
と、前記漂遊容量値C0に比例した大きさの電圧
Vr1が得られる。この電圧Vr1はホールドコンデ
ンサ27にストアされて、該電圧Vr1に応じたオ
フセツト制御電圧V0が電圧保持回路31から発
生される。この制御電圧V0に応じて電圧可変容
量素子37の容量値が変化し、これに応じて変成
器35を介して標準素子19の電流と逆方向に供
給される電流が変化する。かようにして標準素子
19に流れる電流が零となるように制御される。
オフセツト制御電圧V0は次の測定モードの期間
中も電圧保持回路31から発生され続ける。 Next, the operation of the above configuration will be explained. First, a correction mode in which switch 25 is closed while switches 51 and 53 are open will be described. In this case terminal 6
The voltage e x1 at 3 is e x1 =jωC 0 ·1/G r ·e r (1). here. C 0 is the stray capacitance value between the measurement terminals 11 and 17, and G r is the conductance of the standard element 19. That is, since the voltage e x1 is proportional to the admittance of the stray capacitance, when the voltage e x1 is rectified by the synchronous rectifier 13 using the voltage e r (constant) as a reference, a voltage proportional to the stray capacitance value C 0 is generated.
V r1 is obtained. This voltage V r1 is stored in the hold capacitor 27, and an offset control voltage V 0 corresponding to the voltage V r1 is generated from the voltage holding circuit 31. The capacitance value of the voltage variable capacitance element 37 changes according to this control voltage V 0 , and the current supplied through the transformer 35 in the opposite direction to the current of the standard element 19 changes accordingly. In this way, the current flowing through the standard element 19 is controlled to be zero.
The offset control voltage V 0 continues to be generated from the voltage holding circuit 31 during the next measurement mode.
次に、スイツチ25を開き、そしてスイツチ5
1,53を閉じる測定モードについて説明する。
この場合も被測定素子67に流れる電流と標準素
子19に流れる電流とは等しくなるように制御さ
れまた漂遊容量C0による影響は前述補正モード
で補正されているので、端子63における電圧
ex2は、
ex2=jωCX・1/Gr・er (2)
の関係が成立する。ここで、CXは被測定素子6
7の容量値である。(2)式には漂遊容量C0は含ま
れていないので、電圧erを基準にして電圧ex2を
同期整流すれば被測定容量値CXに応じた電圧Vr2
が得られる。従つて、この電圧Vr2に基いて計算
回路23による被測定容量値CXが求まる。 Next, open switch 25, and switch 5
The measurement mode in which 1 and 53 are closed will be explained.
In this case as well, the current flowing through the device under test 67 and the current flowing through the standard device 19 are controlled to be equal, and the influence of the stray capacitance C 0 is corrected in the correction mode described above, so the voltage at the terminal 63 is
For e x2 , the following relationship holds true: e x2 = jωC X・1/G r・e r (2). Here, C X is the device under test 6
The capacitance value is 7. Since the stray capacitance C 0 is not included in equation (2), if the voltage e x2 is synchronously rectified with the voltage e r as a reference, the voltage V r2 corresponding to the measured capacitance value C
is obtained. Therefore, the measured capacitance value C X is determined by the calculating circuit 23 based on this voltage V r2 .
再びスイツチ51,53を開き、次いでスイツ
チ25を閉じて補正モードに入る。その補正動作
後次の被測定素子を接続して測定動作を行う。 Open the switches 51 and 53 again, then close the switch 25 to enter the correction mode. After the correction operation, the next device to be measured is connected and a measurement operation is performed.
以上詳述する如く本考案によれば、特に逐時被
測定素子を代えて測定する場合、例えば複数個の
コンデンサを連続的に検査する場合、その都度漂
遊容量の影響を除去した回路素子定数測定ができ
実用に供して極めて効果大である。 As detailed above, according to the present invention, the circuit element constants can be measured by removing the influence of stray capacitance each time, especially when measuring by changing the device under test, for example, when testing multiple capacitors in succession. It is extremely effective in practical use.
図は本考案の一実施例による回路素子定数測定
装置の回路図で、1:測定電圧源、13:同期整
流器、19:標準素子、23:計算回路、31:
電圧保持回路、33:オフセツト制御回路、6
7:被測定素子である。
The figure is a circuit diagram of a circuit element constant measuring device according to an embodiment of the present invention, in which 1: measurement voltage source, 13: synchronous rectifier, 19: standard element, 23: calculation circuit, 31:
Voltage holding circuit, 33: Offset control circuit, 6
7: Element to be measured.
Claims (1)
流を供給すると共に、該直列回路の共通接続点
が仮想接地点になるように制御し、前記被測定
素子の両端電圧と前記標準素子の両端電圧とに
基づいて同期整流し、同期整流出力信号に応じ
て前記被測定素子の回路定数を測定する装置に
おいて、同期整流回路の出力に接続されたスイ
ツチおよび前記スイツチに接続されたホールド
回路を含み、前記被測定素子が測定端子間に接
続されない期間中前記スイツチを閉成して前記
同期整流出力信号を保持する保持回路と、前記
保持回路の出力信号に応じて、前記標準素子に
流れる電流と逆位相の電流を前記共通接続点に
供給する制御回路とより成るオフセツト補正回
路を具えた回路素子定数測定装置。 (2) 前記制御回路は、両測定端子と並列的に接続
された一次巻線を具えた変成器の二次側中間タ
ツプが接地された該二次側巻線の両端子と、前
記保持回路からの出力信号が供給される第2共
通接続点と、の間に電圧可変容量素子およびコ
ンデンサをそれぞれ接続して成る実用新案登録
請求の範囲第1項記載のオフセツト補正回路を
具えた回路素子定数測定装置。[Claims for Utility Model Registration] (1) The same current is supplied to the series circuit of the device under test and the standard device, and the common connection point of the series circuit is controlled to become a virtual ground point, A device for performing synchronous rectification based on the voltage across an element and the voltage across the standard element, and measuring circuit constants of the element under test according to a synchronous rectification output signal, comprising: a switch connected to the output of the synchronous rectification circuit; a hold circuit connected to the switch, which closes the switch and holds the synchronous rectified output signal during a period when the device under test is not connected between measurement terminals; Accordingly, a circuit element constant measuring device comprising an offset correction circuit comprising a control circuit that supplies a current having an opposite phase to the current flowing through the standard element to the common connection point. (2) The control circuit connects both terminals of the secondary winding of the transformer, which has a primary winding connected in parallel to both measurement terminals, to which the intermediate tap on the secondary side is grounded, and the holding circuit. A circuit element constant comprising an offset correction circuit according to claim 1 of the utility model registration claim, comprising a voltage variable capacitance element and a capacitor respectively connected between a second common connection point to which an output signal is supplied from the offset correction circuit. measuring device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3809377U JPH0142053Y2 (en) | 1977-03-29 | 1977-03-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3809377U JPH0142053Y2 (en) | 1977-03-29 | 1977-03-29 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS53133678U JPS53133678U (en) | 1978-10-23 |
JPH0142053Y2 true JPH0142053Y2 (en) | 1989-12-11 |
Family
ID=28902393
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3809377U Expired JPH0142053Y2 (en) | 1977-03-29 | 1977-03-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0142053Y2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58124969A (en) * | 1982-01-21 | 1983-07-25 | Yokogawa Hewlett Packard Ltd | Measuring device of electrostatic capacity |
-
1977
- 1977-03-29 JP JP3809377U patent/JPH0142053Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS53133678U (en) | 1978-10-23 |
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