JPH0142019B2 - - Google Patents

Info

Publication number
JPH0142019B2
JPH0142019B2 JP5548183A JP5548183A JPH0142019B2 JP H0142019 B2 JPH0142019 B2 JP H0142019B2 JP 5548183 A JP5548183 A JP 5548183A JP 5548183 A JP5548183 A JP 5548183A JP H0142019 B2 JPH0142019 B2 JP H0142019B2
Authority
JP
Japan
Prior art keywords
mask
vector
instruction
processing
statement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5548183A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59180668A (ja
Inventor
Koichiro Hotsuta
Yukio Kamya
Masaaki Takiuchi
Toshihiro Hirabayashi
Masaki Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5548183A priority Critical patent/JPS59180668A/ja
Publication of JPS59180668A publication Critical patent/JPS59180668A/ja
Publication of JPH0142019B2 publication Critical patent/JPH0142019B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/80Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP5548183A 1983-03-31 1983-03-31 条件付命令の実行時命令選択方式 Granted JPS59180668A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5548183A JPS59180668A (ja) 1983-03-31 1983-03-31 条件付命令の実行時命令選択方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5548183A JPS59180668A (ja) 1983-03-31 1983-03-31 条件付命令の実行時命令選択方式

Publications (2)

Publication Number Publication Date
JPS59180668A JPS59180668A (ja) 1984-10-13
JPH0142019B2 true JPH0142019B2 (en, 2012) 1989-09-08

Family

ID=12999807

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5548183A Granted JPS59180668A (ja) 1983-03-31 1983-03-31 条件付命令の実行時命令選択方式

Country Status (1)

Country Link
JP (1) JPS59180668A (en, 2012)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9652284B2 (en) * 2013-10-01 2017-05-16 Qualcomm Incorporated GPU divergence barrier

Also Published As

Publication number Publication date
JPS59180668A (ja) 1984-10-13

Similar Documents

Publication Publication Date Title
EP0515016B1 (en) Instruction scheduler for a computer
US5051896A (en) Apparatus and method for nullifying delayed slot instructions in a pipelined computer system
CA1256216A (en) Program switching with vector registers
US5761514A (en) Register allocation method and apparatus for truncating runaway lifetimes of program variables in a computer system
JP3311462B2 (ja) コンパイル処理装置
KR100616722B1 (ko) 수퍼스칼라프로세서내의파이프라인명령디스패치유닛
US6851045B2 (en) Microprocessor having delayed instructions with variable delay times for executing branch instructions
US20020019910A1 (en) Methods and apparatus for indirect VLIW memory allocation
US5790826A (en) Reduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writes
US6061367A (en) Processor with pipelining structure and method for high-speed calculation with pipelining processors
JPH0581016A (ja) プログラム実行制御方式
EP0742517B1 (en) A program translating apparatus and a processor which achieve high-speed execution of subroutine branch instructions
US11481223B2 (en) Reducing operations of sum-of-multiply-accumulate (SOMAC) instructions
EP0140299A2 (en) Vector mask control system
JPH0142019B2 (en, 2012)
JPS623336A (ja) 条件付きブランチ方式
US11416261B2 (en) Group load register of a graph streaming processor
JPH0346863B2 (en, 2012)
Jacobi Code generation and the Lilith architecture
KR19980034436A (ko) 듀얼 파이프라인 프로세서에서 로드 명령의 병렬 수행 장치
CN112506642A (zh) 信息处理设备、信息处理程序的记录介质和信息处理方法
JPS6319906B2 (en, 2012)
JPS6321946B2 (en, 2012)
JPH046020B2 (en, 2012)
JPS6319908B2 (en, 2012)