JPH0140517B2 - - Google Patents
Info
- Publication number
- JPH0140517B2 JPH0140517B2 JP56142934A JP14293481A JPH0140517B2 JP H0140517 B2 JPH0140517 B2 JP H0140517B2 JP 56142934 A JP56142934 A JP 56142934A JP 14293481 A JP14293481 A JP 14293481A JP H0140517 B2 JPH0140517 B2 JP H0140517B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film
- resistive
- integrated circuit
- space
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 30
- 239000010409 thin film Substances 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 239000002131 composite material Substances 0.000 claims description 11
- 238000005259 measurement Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 20
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910001120 nichrome Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- 238000009966 trimming Methods 0.000 description 2
- 238000007743 anodising Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Description
【発明の詳細な説明】
本発明は薄膜混成集積回路、特にCR複合素子
を含む薄膜集積回路モジユールを１枚の基板上に
形成して作成される薄膜混成集積回路の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film hybrid integrated circuit, and more particularly to a method for manufacturing a thin film hybrid integrated circuit that is produced by forming a thin film integrated circuit module including a CR composite element on a single substrate.
薄膜混成集積回路において、コンデンサ素子と
抵抗素子とが接続形成されてなる薄膜CR複合素
子は、一般に第１図に示す如くグレーズドアルミ
ナ基板１の上にタンタル酸化膜（Ta2O5）にてな
る絶縁層２を被着し、その上にタンタル（β−
Ta又はα−Ta）薄膜にてなる下部電極３と下部
電極３の一部表層を陽極酸化してなる誘電体層
（Ta2O3）４が形成される。そして、下部電極３
から少し離れた側方には窒化タンタル（Ta2N）
薄膜にてなる抵抗層５を形成し、抵抗層５の中央
露呈部窒化タンタルの酸化膜（Ta2NxOy）８を
形成させたのち、ニクロム（NiCr）を密着層６
とし金（Au）にてなる上部電極７は下部電極３
の露呈部上面と、誘電体層４から抵抗層５の一端
に連らなる上面と、抵抗層５の他端上面とにパタ
ーン形成される。次いで、CR積値が規格値とな
るように抵抗層５をレーザトリミングを施して完
成される。 In a thin film hybrid integrated circuit, a thin film CR composite element in which a capacitor element and a resistor element are connected is generally made of a tantalum oxide film (Ta 2 O 5 ) on a glazed alumina substrate 1 as shown in FIG. An insulating layer 2 is deposited, and tantalum (β-
A lower electrode 3 made of a Ta (Ta or α-Ta) thin film and a dielectric layer (Ta 2 O 3 ) 4 formed by anodizing a part of the surface layer of the lower electrode 3 are formed. And the lower electrode 3
Tantalum nitride (Ta 2 N) is placed on the side slightly away from the
After forming a resistive layer 5 made of a thin film and forming a tantalum nitride oxide film (Ta 2 NxOy) 8 on the central exposed part of the resistive layer 5, nichrome (NiCr) is applied to the adhesive layer 6.
The upper electrode 7 made of gold (Au) is the lower electrode 3
A pattern is formed on the upper surface of the exposed portion, the upper surface extending from the dielectric layer 4 to one end of the resistive layer 5, and the upper surface of the other end of the resistive layer 5. Next, the resistor layer 5 is completed by laser trimming so that the CR product value becomes a standard value.
第２図は上記CR複合素子の形成工程を順次示
したものであり、まず第２図ａに示す如く、下部
電極３の一部に誘電体層４を形成したのち、全面
を覆うようにして窒化タンタル膜５′が被着され
る。次いで、窒化タンタル膜５′を選択的に除去
して第２図ｂに示す如く、抵抗層５をパターン形
成したのち、第２図ｃに示す如き密着層６と上部
電極７とが積層形成される。 FIG. 2 shows the steps for forming the above-mentioned CR composite element. First, as shown in FIG. 2a, a dielectric layer 4 is formed on a part of the lower electrode 3, and then the dielectric layer 4 is formed to cover the entire surface. A tantalum nitride film 5' is deposited. Next, the tantalum nitride film 5' is selectively removed and the resistive layer 5 is patterned as shown in FIG. 2b, after which an adhesive layer 6 and an upper electrode 7 are laminated as shown in FIG. Ru.
かかる薄膜構成にてなるCR複合素子を含み１
枚の基板から複数個採取する薄膜混成集積回路に
おいて、抵抗層５の抵抗値を所望値とするため抵
抗膜５′の面積抵抗値（Ω／□）を、複数個の薄
膜集積回路モジユールを隣接し、かつ、コンデン
サ素子用誘電体層４がすでに形成された基板１の
上面で測定することは、誘電体層４の影響を受け
て正しく測定することができない。そのため、従
来はコンデンサ素子構成膜を被着しないダミー基
板上に、抵抗膜５′の被着と同時に抵抗膜を被着
させ該抵抗膜の面積抵抗値を測定していた。 Including a CR composite element with such a thin film configuration 1
In order to obtain the desired resistance value of the resistive layer 5 in thin film hybrid integrated circuits in which multiple thin film integrated circuits are sampled from a single substrate, the sheet resistance value (Ω/□) of the resistive film 5' is adjusted to However, if the measurement is performed on the upper surface of the substrate 1 on which the capacitor element dielectric layer 4 has already been formed, the measurement cannot be performed correctly due to the influence of the dielectric layer 4. Therefore, conventionally, a resistive film was deposited on a dummy substrate on which no capacitor element constituent film was deposited at the same time as the resistive film 5' was deposited, and the sheet resistance value of the resistive film was measured.
しかし、ダミー基板上の抵抗膜の面積抵抗値と
製品基板上の抵抗膜５′の面積抵抗値とは許容範
囲を越えて異なることがあり、CRモジユールの
特に固定容量値、固定抵抗値からはずれるものが
あり、そのことによる不良率は数％に及ぶことが
あつた。 However, the sheet resistance value of the resistive film on the dummy board and the sheet resistance value of the resistive film 5' on the product board may differ beyond the permissible range, which may deviate from the fixed capacitance value and fixed resistance value of the CR module. This caused the defective rate to reach several percent.
本発明の目的は上記欠点を除去することであ
り、この目的は複数個の薄膜集積回路モジユール
が形成される絶縁基板の中央部に抵抗膜の面積抵
抗測定用スペースを設け、前記各モジユールの
CR複合素子用誘電体層及び前記スペースを覆う
抵抗膜を被着し、その抵抗膜の面積抵抗値は誘電
体層を形成しない前記スペースにおいて測定する
ことを特徴とした薄膜混成集積回路の製造方法を
提供して達成される。 An object of the present invention is to eliminate the above-mentioned drawbacks, and the object is to provide a space for measuring the area resistance of a resistive film in the center of an insulating substrate on which a plurality of thin film integrated circuit modules are formed, and to measure the area resistance of each of the modules.
A method for manufacturing a thin film hybrid integrated circuit, characterized in that a dielectric layer for a CR composite element and a resistive film covering the space are deposited, and the sheet resistance value of the resistive film is measured in the space where the dielectric layer is not formed. This is achieved by providing.
以下、図面を用いて本発明方法を説明する。 The method of the present invention will be explained below using the drawings.
第３図は本発明の一実施例に係わる面積抵抗測
定用スペースを設けた絶縁基板の平面図であり、
グレーズドアルミナ基板１０の上面にはＸ方向へ
５個、Ｙ方向へ９個の薄膜集積回路モジユール領
域１１が設定され、斜線で示す中央領域１２は抵
抗膜の面積抵抗測定用スペースである。そして44
個のモジユール領域には前述したCR複合素子を
含む集積回路が形成されるが、CR複合素子の形
成過程において第２図ａに示す如く、抵抗膜５′
を被着したときスペース１２では、基板１０上の
絶縁層２の上に抵抗膜５′が同時被着される。従
つて、抵抗膜５′の面積抵抗値を例えば四探針法
で測定しようとするときは、スペース１２上で測
定すれば誘電体層４に影響されることなく正確な
値が得られる。 FIG. 3 is a plan view of an insulating substrate provided with a space for sheet resistance measurement according to an embodiment of the present invention;
Five thin film integrated circuit module areas 11 are set in the X direction and nine in the Y direction on the upper surface of the glazed alumina substrate 10, and the central area 12 shown by diagonal lines is a space for measuring the sheet resistance of the resistive film. and 44
An integrated circuit including the above-mentioned CR composite element is formed in each module area, but in the process of forming the CR composite element, as shown in FIG. 2a, the resistive film 5'
When the resistive film 5' is deposited, the resistive film 5' is simultaneously deposited on the insulating layer 2 on the substrate 10 in the space 12. Therefore, when measuring the sheet resistance value of the resistive film 5' using, for example, the four-probe method, an accurate value can be obtained without being affected by the dielectric layer 4 by measuring on the space 12.
第４図は前記基板１０に抵抗膜を被着するスパ
ツタリング時間と、基板スペース１２で測定した
前記抵抗膜の面積抵抗値との関係例を示す図であ
る。ただし、図中のＸ印はダミー基板を使用した
基準抵抗値であり、・印は基板上スペース１２に
おける実測抵抗値をプロツトしたものである。従
つて、スパツタリング中の異常放電等により面積
抵抗値が大きくなつた異常抵抗膜（測定点Ａ）、
又は小さくなつた異常抵抗膜（測定点Ｂ）は、そ
の実測値に基づき、抵抗層５にパターン形成した
のちの抵抗化成時に、形成されるタンタル酸化膜
８の厚さを調整することにより所望抵抗値のCR
複合素子が得られるようになる。 FIG. 4 is a diagram showing an example of the relationship between the sputtering time for depositing the resistive film on the substrate 10 and the sheet resistance value of the resistive film measured in the substrate space 12. However, the X mark in the figure is a reference resistance value using a dummy board, and the * mark is a plot of the actually measured resistance value in the space 12 on the board. Therefore, an abnormal resistance film (measurement point A) whose sheet resistance value has increased due to abnormal discharge during sputtering, etc.
Alternatively, the abnormal resistance film (measurement point B) which has become smaller can be made to have a desired resistance by adjusting the thickness of the tantalum oxide film 8 formed during resistance formation after patterning the resistance layer 5 based on the actual measurement value. CR of value
Composite elements can now be obtained.
以上説明した如く本発明方法によれば、製品基
板に被着した抵抗膜特性を検知できるため、該特
性に基ずくトリミングを可能ならしめ、CR複合
素子を含み複数個取りしてなる薄膜混成集積回路
の製造歩留りを向上し得た効果がある。 As explained above, according to the method of the present invention, the characteristics of the resistive film adhered to the product substrate can be detected, so trimming can be performed based on the characteristics. This has the effect of improving the manufacturing yield of circuits.
なお、本発明は上記実施例に限定するものでな
く、「特許請求の範囲」内において適宜実施し得
るものである。 It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented as appropriate within the scope of the claims.
第１図は薄膜混成集積回路に膜形成されたCR
複合素子の一般的構造を示す側断面図、第２図は
前記CR複合素子の形成工程を順次示した側断面
図、第３図は本発明の一実施例に係わる面積抵抗
測定用スペースを設けた薄膜混成集積回路用基板
の平面図、第４図は第３図に示した基板に抵抗膜
を被着するスパツタリング時間と該基板の所定ス
ペースで測定した前記抵抗膜の面積抵抗値との関
係例を示す図である。
なお、図中において、１，１０はグレーズド基
板、５は抵抗層、５′は抵抗膜、８は抵抗化成に
よる窒化タンタル酸化膜、１１は薄膜集積回路モ
ジユール、１２は面積抵抗測定用スペース、Ａ，
Ｂは異常抵抗測定値を示す。
Figure 1 shows CR film formed on a thin film hybrid integrated circuit.
2 is a side sectional view showing the general structure of the composite element, FIG. 2 is a side sectional view sequentially showing the steps of forming the CR composite element, and FIG. FIG. 4 is a plan view of a thin film hybrid integrated circuit substrate shown in FIG. 3, and shows the relationship between the sputtering time for depositing a resistive film on the substrate shown in FIG. It is a figure which shows an example. In the figure, 1 and 10 are glazed substrates, 5 is a resistive layer, 5' is a resistive film, 8 is a tantalum nitride oxide film formed by resistor formation, 11 is a thin film integrated circuit module, 12 is a space for measuring sheet resistance, A ，
B shows abnormal resistance measurements.
Claims (1)
てなるCR複合素子を含む複数個の薄膜集積回路
モジユールが１枚の絶縁基板上に形成されて作成
される薄膜混成集積回路の製造方法において、絶
縁基板の中央部に抵抗膜の面積抵抗測定用スペー
スを設け、各薄膜集積回路モジユールのCR複合
素子用誘電体層及び前記スペースを覆うように被
着した抵抗膜の面積抵抗値は、誘電体層を形成し
ない前記スペースにおいて測定することを特徴と
した薄膜混成集積回路の製造方法。1. In a method for manufacturing a thin film hybrid integrated circuit in which a plurality of thin film integrated circuit modules including a CR composite element formed by connecting a capacitor element and a resistor element are formed on a single insulating substrate, the insulating substrate A space for measuring the area resistance of the resistive film is provided in the center of the area. A method for manufacturing a thin film hybrid integrated circuit, characterized in that measurement is performed in the space that is not formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56142934A JPS5844760A (en) | 1981-09-10 | 1981-09-10 | Manufacture of thin film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56142934A JPS5844760A (en) | 1981-09-10 | 1981-09-10 | Manufacture of thin film hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5844760A JPS5844760A (en) | 1983-03-15 |
| JPH0140517B2 true JPH0140517B2 (en) | 1989-08-29 |
Family
ID=15327036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56142934A Granted JPS5844760A (en) | 1981-09-10 | 1981-09-10 | Manufacture of thin film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5844760A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0748407B2 (en) * | 1989-06-16 | 1995-05-24 | 株式会社日立製作所 | Method of manufacturing thin film resistor |
| JPH0319301A (en) * | 1989-06-16 | 1991-01-28 | Hitachi Ltd | Film formation for thin film resistor |
-
1981
- 1981-09-10 JP JP56142934A patent/JPS5844760A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5844760A (en) | 1983-03-15 |
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