JPH0139539B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a combination weighing method for quantitatively weighing fruits and vegetables, fresh foods, secondary processed products, confectionery, etc., which have large unit weight variations, with high precision and high capacity.

A weighing method in which the weight of objects to be weighed supplied to each weighing hopper of a plurality of weighing machines is weighed, and each weighing value is added for each different combination to obtain a predetermined weight or a combination of weights closest to it, and the above-mentioned weighing method. Counting methods for obtaining a predetermined number of objects by dividing each weighing value by the weight of the object to be weighed, converting it into a piece value, and adding each different combination of each piece value, have already been established. The applicant is a special public official in 1974.
Disclosed in No. 14946 and Special Publication No. 55-4824.

This type of method for obtaining a predetermined amount of weight or number of objects to be weighed by a combination calculation does not affect the measurement accuracy due to variations in the individual weights of the objects to be weighed, and it is possible to perform extremely high-precision weighing. Disturbances in supply and alignment do not directly lead to miscalculation or errors,
High accuracy can be maintained even if the set value becomes large, and
There are many advantages, such as errors in the settings of each weighing machine do not affect the final error.

As mentioned above, a major feature of combination weighing is that high-precision weighing can be performed, but in addition to this feature, there has recently been a demand for further improvements in weighing ability.

Therefore, the present applicant proposed in Japanese Patent Application No. 157394/1983 that the objects to be weighed are discharged from the weighing hopper in an optimal combination that is equal to or closest to the set value, and that the weighing hopper is emptied after being discharged. When a new object to be weighed is supplied to the old weighing hopper and the value of the object fed to the weighing hopper participates in the combination calculation again, the next combination calculation is performed and the value obtained in the previous combination calculation is calculated. A combination weighing method and apparatus have already been disclosed for obtaining the next optimal combination that is equal to or closest to the set value from the values of the objects to be weighed that do not correspond to the optimal combination.

This invention further develops the above-mentioned invention, and the objects to be weighed that correspond to the optimal combination that is equal to or close to the target set value are discharged from the weighing machine,
By the time a new object to be weighed is supplied to the weighing machine and the value of the object to be weighed that was supplied to the weighing machine participates in the combination calculation again, the value of the remaining object to be weighed that is currently being supplied to the weighing machine will be The operation is performed a predetermined number of times to obtain the optimal combination that is equal to or close to the set value, and the objects to be weighed that correspond to the optimal combination obtained in each calculation are discharged from the weighing machine. This provides a combination weighing method that further improves the weighing ability.The details of this invention will be explained below with reference to embodiments shown in the drawings.

FIG. 1 is a schematic configuration diagram showing an example of a collection mechanism of a weighing machine used in the present invention, and in the figure A ₁ , A ₂
... A _o is a weighing machine, B ₁ , B ₂ ... B _o is a weighing hopper of the weighing machine, C ₁ , C ₂ , ... C _o is a pool hopper, D is a conveyor linked to a packaging machine, etc., and a plurality of buckets E ₁ , E ₂ , ...E _o . In addition, F is a slit plate _F1 that rotates in synchronization with the conveyor D and a floodlight.
1 is an ejection timing pulse generator comprising F ₂ and a photoreceiver F ₃ .

Each of the above pool hoppers is equipped with an independent supply device (not shown) for the object to be weighed, and the feeding operation of each feeding device is performed when the corresponding pool hopper is empty after discharging the object to be weighed. The weighing machine starts at a certain time and stops after supplying one object, a set number of objects, or approximately a set weight, and
When each weighing hopper has finished discharging the object to be weighed and is empty, a conventionally known type of feeding device and weighing mechanism are used to open and close the corresponding pool hopper and discharge the object to be weighed into the weighing hopper.

Each bucket E ₁ , E ₂ ,...E _o runs continuously,
The structure is such that objects to be weighed discharged from the weighing hopper can be sequentially collected in synchronization with the discharge timing pulse TP of the discharge timing pulse generator F.

Each of the weighing machines A ₁ , A _{2 ,} . Let the measurement value signals output by the weighing machines A ₁ , A ₂ , ... A _o be a ₁ , a ₂ , ... a _o .

FIG. 2 is a block diagram showing the above-mentioned electronic calculation circuit of the present invention, in which G indicates each weighing machine.
A ₁ , A ₂ , ... Weighing value signals a ₁ , a ₂ , output from A _o
...A addition code selection circuit that selects a combination of addition codes for selectively adding _o ; The addition value α and the set measurement value _a0 are compared, and each measurement value signal is added based on the optimal addition code stored in the addition code storage circuit J, which will be described later, and this addition value β and the above addition value α are added. , a lower limit set value b, and an upper limit set value c.

J is an addition code storage circuit J-1, J-2 which stores a combination code having a value closest to the desired set weight according to the comparison result of the addition comparison circuit H and the check result of the bit check circuit L described later. ,…
J-m is the first point to store the optimal addition code stored in the addition code storage circuit J using a storage command pulse CP output from the storage command signal generation circuit G2, which will be described later, when all the combinations of addition codes are completed. These are first, second, . . . m-th addition code storage circuits.
The first, second, ... m-th addition code storage circuit J
-1, J-2,...J-m, the object to be weighed is discharged from the weighing hopper, a new object to be weighed is supplied to the weighing hopper, and the value of the object to be weighed that was supplied to the weighing hopper is changed again. Before participating in the combination calculation, the optimal addition code corresponding to the optimal combination obtained through each combination calculation performed a predetermined number of times based on the values of the remaining objects to be weighed that are currently being supplied to the weighing hopper. , and the optimum addition code corresponding to the weighing hopper currently discharging.

The number of combination calculations that are performed between the time a weighing hopper performs a discharge operation and the time it participates in the next combination calculation depends on the number of weighing hoppers and the result of one combination calculation. , and the collection capacity of the collection mechanism that collects the objects to be weighed discharged from the weighing hopper.

L is a combination of the addition codes of the addition code selection circuit G and the first, second... m-th addition code storage circuits J-1, J-2,...J- which are inputted via the selection pattern register K. m is a bit check circuit that performs a bit check with the stored optimal addition code, and R is a bit check circuit that performs a bit check with the stored optimal addition code, and R is a bit check circuit that performs a bit check with the stored optimal addition code. This is a decoder counter that outputs a control signal.

G1 is a preset signal generation circuit that outputs a preset signal to any of the first, second, ... m-th addition code storage circuits J-1, J-2, ... J-m;
2 is the first, second, . . . m-th addition code storage circuit J
-1, J-2, . . . J-m is a storage command signal generation circuit that outputs a storage command signal to any one of J-m.

When all the combinations of addition codes are completed and there is no optimal addition code, FF is sent to the first, second, . . . mth addition code storage circuits J-1, J- via the preset signal generation circuit G1. 2, . . . is a flip-flop for presetting any of Jm.

M is when all combinations of addition codes are completed,
Even when the calculation end signal is received, the optimal addition code stored in any one of the first, second, ... m-th addition code storage circuits J-1, J-2, ... J-m is read out, and the corresponding weighing hopper is read out. Discharge signals d ₁ , d ₂ ,...
This is an emission control circuit that emits dn.

The above-mentioned addition code refers to a code number attached to each weighing machine or each weighing hopper, and the combination of these code numbers. Now, if the code numbers of each weighing machine are X ₁ , X ₂ ,...X _o , then n
The total number of combinations in which one item is extracted from these items is n. Further, there are n(n-1)/2×1 combinations in which two items are extracted from n items. Further, there are n(n-1) (n-2)...(n-γ+1)/γ ₁ ' combinations for extracting γ from n items. Any one of these combinations is outputted from the addition code selection circuit G of the electronic calculation circuit.

Next, the specific configuration of each of the above-mentioned circuits constituting the electronic calculation circuit will be explained as follows.
In addition, the figures showing the specific configuration of the weighing machine are
The figure shows the case where the machine is used.

As shown in FIG. 3, the addition code selection circuit G consists of a clock pulse oscillator 1 that oscillates a clock pulse in response to a calculation start pulse, and a clock pulse oscillator 1 which takes this output as an input and has four stages of binary counters connected in series.
Each bit output of the counter 2 changes as shown in FIG. 13 for each clock pulse output from the clock pulse oscillator 1 to generate a combination pattern.
Now, each bit output Q ₁ , Q ₂ , ...Q _o of counter _{2 is} converted _to the code number X ₁ ,
If X ₂ ,...X _o are made to correspond, the above combination pattern will be as shown in Fig.
In the case of a machine, the total number of combinations is 4095. Then, the inverted outputs ₁ , ₂ , ... _o of each bit output Q ₁ , Q ₂ , ... Q _o of the counter 2 are added to the code storage circuit J,
Connected to addition/comparison circuit H and bit check circuit L, respectively.

On the other hand, as shown in FIG. 2, the output of the clock pulse oscillator 1 and the second bit output of the counter 2
Q ₂ is connected to the input of AND circuit 3, the output of clock pulse oscillator 1 and the n+1 bit output Q _o +1 of counter 2 are connected to the input of AND circuit 4, and the calculation is completed using the output of AND circuit 4. It is connected as a signal to the clock pulse oscillator 1, and is also connected to each input of AND circuits 5 and 6, which receive a check signal _S3 of an allowable error range from an addition/comparison circuit H, which will be described later. The outputs of the AND circuits 3 and 5 are connected to the R and S terminals of the flip-flop FF, respectively, as shown in FIG. 2, and the Q output of the flip-flop FF is connected to the AND circuit 7. It is set as.

As shown in FIG. 4, the decoder counter R is
It consists of a binary counter 8, a decoder 9, an overlap number change switch 10, and an OR circuit 11 that outputs a clear signal to the binary counter 8. When the clear signal CLR is input to the binary counter 8, only the first step becomes "1". Next, when the clock signal CLK is input, only the second step becomes "1", and along with the clock signal CLK,
Move one after another and return to the original position after m steps. The decoder output of the decoder counter R is input to the preset signal generation circuit G1, the storage command signal generation circuit G2, and the selection pattern register K, and is also input to the clock terminal CLK of the binary counter 8 via the delay circuit 12.
The output of AND circuit 6 is made to be input.

As shown in FIG. 5, the preset signal generation circuit G1 includes m AND circuits 13a, 13b...13.
It is composed of m, m OR circuits 14a, 14b...14m, and the decoder output of the decoder counter R mentioned above is input to one input terminal of the AND circuit 13, and the other terminal is The output of the AND circuit 7 is inputted. on the other hand,
The output of the AND circuit 13 is input to the input terminal of the OR circuit 14, and the initial clear signal is input to the other input terminal. Then, the outputs of the m OR circuits 14a, 14b...14m are sent to the preset terminals of the first, second...m-th addition code storage circuits J-1, J-2...J-m, respectively.
Connect to PR.

As shown in FIG. 6, the storage command signal generation circuit G2 consists of m AND circuits 15a, 15b, . and the other input terminal is
The output of the AND circuit 6 is inputted.
And m AND circuits 15a, 15b...15m
are connected to the clock terminals CLK of the first, second...m-th addition code storage circuits J-1, J-2...J-m, the emission control circuit M, and the OR circuit 24. .

As shown in FIG. 7, the addition/comparison circuit H receives each measured value signal a ₁ , a ₂ . _. . _{a o} and the inverted outputs ₁ , 2 . a first adder N- that adds each measurement value signal based on the combination pattern (see Fig. 14);
1, each measurement value signal a ₁ , a ₂ ...a _o , and the optimal combination code output x ₁ , x _{2 ...} A second adder N-2 that adds, and a double adder N
-1, N-2, an addition value comparator P that compares the outputs α and β, and a measurement value comparator Q that compares the output α of the first adder N-1 and the set measurement value _a0 . , second
A lower limit set value comparator r that compares the output β of the adder N-2 with the lower limit set value b and the upper limit set value c, respectively.
and an upper limit set value comparator s.

The output _S1 of the added value comparator P becomes "1" when the output α of the first adder N-1 is smaller than the output β of the second adder N-2, that is, when α<β,
In a case other than α<β, that is, in a case α≧β, it becomes “0”. Further, the output _S2 of the measured value comparator Q becomes "1" when the output α of the first adder N-1 is greater than or equal to the set measured value _a0 , that is, when α≧ _a0 ,
If α<a ₀ , it becomes "0" and negative weighing is cut off. Furthermore, a second adder N-2
If the output β is greater than or equal to the lower limit set value b and less than or equal to the upper limit set value c,
In other words, when the error is within the tolerance range (b≦β≦c), the output _S3 of the AND circuit 16 that receives the outputs of both comparators r and s becomes “1”, and when it is outside the tolerance range (β<b
Or, in the case of β>c), the output S ₃ becomes “0”. The lower limit set value b is set to a value somewhat smaller than the set weighing value a ₀ in order to loosen the allowable error range a little, taking into account that each weighing hopper may oscillate to some extent.

Then, the output _S1 of the addition value comparator P, the output _S2 of the measured value comparator Q, the output of the clock pulse oscillator 1, and the output BCK of the bit check circuit L described later.
and are respectively connected to the inputs of the AND circuit 17, and the check output _S3 of the allowable error range is connected to the AND circuit 17 as described above.
Connect to each input of circuits 5 and 6 (see Figure 2).

The addition code storage circuit J is used to store the combination code of the set weighing value a ₀ , that is, the value closest to the desired set weight, and as shown in FIG. If there are 12 units, then 2
) and an addition code selection circuit G on the input side.
The inverted outputs ₁ , ₂ ... _o of
...mth addition code storage circuit J-1, J-2...J
-m respectively, and the outputs x ₁ , x ₂ ... x _o are the inputs.
They are made to correspond to Q ₁ , ₂ ... _o , that is, to the code numbers X ₁ , X ₂ ... X _o of each weighing machine. Then, when the output of the AND circuit 17 (Fig. 2) is "1", one of the inputs ₁ , ₂ ... _o that is "1" is read, that is, the combination code selected by the addition code selection circuit G is stored. , output this combination code.

Incidentally, in this addition code storage circuit J, all code outputs x ₁ , x ₂ . _. .

On the other hand, the first, second...m-th addition code storage circuits J-1, J-2...J-m all have the same configuration, and as shown in FIG. , 19..., and each code output _x1 , _x2 ... of the addition code storage circuit J is connected to each input side.
x _o is connected, and each output is connected to a selection pattern register K and a discharge control circuit M, respectively. Then, the optimum combination codes stored in the addition code storage circuit J are determined by the _first , _second , ... CP _n of the storage command pulse of "1" outputted from the storage command signal generation circuit G2. m addition code storage circuit J-
1, J-2...J-m is stored, and the output corresponding to the stored combination code becomes "1".

In addition, each addition code storage circuit J-1, J-2...J
-m is preset by either the initial clear pulse or the "1" output of the preset signal generating circuit G1, and each output thereof becomes "0" and is placed in a state in which no combination code is stored.

As shown in FIG. 10, the selection pattern register K is a wired connection of m AND circuits 20a, 20b, .
The decoder output of the decoder counter R mentioned above is inputted to one input terminal of a, 20b...20m, and the first, second...mth addition code is stored in the other input terminal. Circuit J-1, J
-2...J-m outputs are respectively input, and each AND circuit 20a, 20b...20
The output of m is input to a bit check circuit L. All the memory data of the addition code storage circuits other than the addition code storage circuit currently selected by the decoder 9 of the decoder counter R are sent to the bit check circuit.

The bit check circuit L receives the inverted outputs ₁ , ₂ ... _o of the addition code selection circuit G and the code outputs Kx ₁ , Kx ₂ of the selection pattern register K, as shown in FIG.
...Kx _o is input, and both inputs are used in the logic circuit 21 to check each bit of Q ₁ and Kx ₁ , Q ₂ and Kx ₂ ...Q _o and Kx _o , and each set ( ₁ , Kx ₁ , ₂ , Kx ₂ ...
If even one set of Q _o and Kx _o becomes "1" at the same time and a match is found, the output BCK of the bit check circuit L becomes "0", and if no match is found, the output BCK becomes "0". The circuit is configured so that it becomes "1".

Furthermore, the emission control circuit M has m control circuits M _a as shown in FIG.
M _a , M _b -M _n correspond to the first, second, . . . m-th addition code storage circuits J-1, J-2, . . . J-m, respectively. Then, these m control circuits M _a ,
M _b ...M _n receives the output of the storage command signal generation circuit G2 and the discharge timing pulse TP from the discharge timing pulse generator F shown in FIG. A pulse generation circuit 22 that sequentially outputs pulses from outputs Q _A , Q _B .
Q ^A , Q ^B and _the code outputs x 1 , x from the corresponding addition code storage circuits among the first, second...m-th addition code storage circuits J-1, J-2...J-m ₂ ... _xo
is input, matches Q ^A and x ₁ , Q ^B and x ₂ , etc., and outputs discharge signals _d1 , _d2 ...d _o to the corresponding weighing machine when both inputs are "1" at the same time. logic circuit 23
It consists of

In addition, the logic circuit 23 of each control circuit Ma, Mb...Mm
The discharge signals d ₁ , d ₂ , . . . d _o outputted from the output terminals are configured to be outputted via an OR circuit.

The operation of the present invention having the above-described configuration will now be described in the case where 12 weighing machines are used to obtain the value closest to the set weight a ₀ .

First, turn on the power and generate an initial clear pulse automatically or manually by turning on a dedicated switch. Then, counter 2 of addition code selection circuit G
Each output Q ₁ , Q ₂ ...Q ₁₃ of is cleared to "0", and each code output of addition code storage circuit J
x ₁ , x _{2 .} . . x ₁₂ are cleared to "1", and all codes are placed in a selected state. At the same time, the decoder counter R becomes "1" only in the first step and "0" in the second to mth steps, and the Q output of the flip-flop FF is cleared to "0" (wire connections not shown). Furthermore,
First, second... m-th addition code storage circuit J-1,
The code outputs x ₁ , x ₂ , _. . . Then, each output of the storage command signal generation circuit G2 becomes "0",
Further, the output of the OR circuit 24 is also "0" and the conveyor D does not run. In other words, the ejection timing pulse
Since TP is not output, no pulse is output from each output Q ^A , Q ^B . . . Q ^L of each pulse generating circuit 22 of the discharge control circuit M. Therefore, the discharge signals d ₁ , d _{2 .} . . d ₁₂ are also not output. Also, since the first step of the decoder counter R is set to "1", the selection pattern register K is set to the second,
3rd...m-th addition code storage circuit J-2, J-3
…Bit check circuit L for each “0” output of J-m
On the other hand, since the inputs from the addition code selection circuit G of the bit check circuit L are all "0", the two inputs cannot match, and the output BCK of the bit check circuit L becomes "1". Furthermore, among the inputs in the addition/comparison circuit H, inputs ₁ , ₂ ... ₁₂ from the addition code selection circuit G are each "0", and each code input from the addition code storage circuit J
_{Since x 1 , x 2} ... On the other hand, the output of the second adder N-2 also becomes β=0. Therefore, the output _S1 of the addition value comparator P is "0", the output _S2 of the measured value comparator Q is also "0", and the output of the upper limit set value comparator S and the output of the lower limit set value comparator r are The output _S3 of the AND circuit 16, which is used as an input, also becomes "0". Therefore, AND
The output of the circuit 17 becomes "0", and the addition code storage circuit J remains in the all-code selected state. Also, as mentioned above, since the output _S3 of the AND circuit 16 is "0", one input of the AND circuit 5 becomes "1", and the other input becomes "1" because the output of the AND circuit 4 is "0". Therefore, the output of the AND circuit 5 becomes "0", and the Q output of the flip-flop FF remains cleared to "0".

Next, the weighing hopper B ₁ of each weighing machine A ₁ , A ₂ ...A ₁₂ ,
Objects to be weighed are thrown into B ₂ ... B ₁₂ from each pool hopper C ₁ , C ₂ ... C ₁₂ , and the weight of each object is measured. When the weighing is completed, either this completion signal or the signal from the packaging machine is used to input a calculation start signal to the electronic calculation circuit shown in FIG. The calculation start signal is input as a clear signal to the counter 2 of the addition code selection circuit G and the addition code storage circuit J, but as described above, each of these has already been cleared by the initial clear pulse. In addition, the calculation start signal is also input to the AND circuit 7,
Since the Q output of the flip-flop FF is cleared to "0", the output of the circuit 7 remains "0". On the other hand, when the calculation start signal is input to the clock pulse oscillator 1 of the addition code selection circuit G, the clock pulse is sent to the counter 2 as shown in FIG. 13, and the counter 2 outputs the combination pattern, that is, the addition combination code Q. ₁ , _Q2 ...
Occurs from Q ₁₂ .

Now, enter the code numbers of each weighing machine A ₁ , A ₂ ...A ₁₂ .
Assuming X ₁ , X ₂ ...X ₁₂ , the measured values are a ₁ , a ₂ ... respectively.
If a _{is 12} , the addition combination code output from counter 2 is X ₁ , X ₂ , X ₁ as shown in FIG.
+X _{2 .} . . and calculations are performed in this order by the addition and comparison circuit H. First, in the case of X ₁ , in Figure 7,
The addition value α of the first adder N-1 is α=a ₁ ,
Since the addition code storage circuit J is now in the all-code selection state, the addition value β of the second adder N-2 is β=a ₁ +a ₂ +...a ₁₂ . Then, α and β are compared in addition value comparator P, and the result is α<β
Therefore, the output _S1 of the comparator P becomes "1".
Also, the set measurement value a ₀ is a set of each measurement value, for example, 2
If the weighing range of each weighing machine is determined in advance so as to obtain a combination of ~4 weighing machines, the comparison result of α and a ₀ in the weighing value comparator Q becomes α<a ₀ , and the output S ₂ becomes "0". ”
becomes. Furthermore, the comparison result of the lower limit set value comparator r is b<β, and the comparison result of the above set value comparator S is c
<β, and the output _S3 of the AND circuit 16, which is the result of checking the allowable error range for the set measurement value _a0 , becomes "0".

On the other hand, the input from the counter ₂ of the addition code selection circuit G to the bit check circuit L is "1",
Q ₂ ... ₁₂ are each "0", and the second, third ... mth
Each code output Kx ₁ , Kx 2...Kx ₁₂ from the addition code storage circuit J-2, J- ₃ ...J-m is all "0"
Therefore, each bit check in the logic circuit 21 does not match, and the output of the bit check circuit L
BCK becomes "1". This state of "1" is maintained at least until all the first combination calculations are completed. Therefore, each input S ₁ of the AND circuit 17,
As for S ₂ and BCK, S ₂ is "0", S ₁ and BCK are each "1", the output of this circuit 17 remains "0", and the addition code storage circuit J is connected to the addition code selection circuit G. Does not memorize the selected code X ₁ . Furthermore, the output _S3 of the AND circuit 16, which is the result of checking the tolerance range of the addition/comparison circuit H, is "0", which is inverted and input to the AND circuit 5.
Since the other input is “0”, the flip-flop
The Q output of FF remains "0".

In this way, the addition combination codes X ₂ , X ₁ + output from the counter 2 of the addition code selection circuit G
According to X _{2 .} . . , the addition and comparison circuit H sequentially performs addition and comparison, and at the same time, the bit check circuit L performs a bit check. As mentioned above, since the output BCK of the bit check circuit L is "0" until all combination calculations are completed, the output _S1 of the addition value comparator P and the measured value comparator Q
When the outputs _S2 of both are "1", that is, α<β and α≧a ₀ , at the timing of the next clock pulse from the clock pulse oscillator 1 of the addition code selection circuit G.
The output of the AND circuit 17 becomes "1", and this "1"
As for the output, the addition combination code selected by the addition code selection circuit G is stored in the addition code storage circuit J.

On the other hand, when at least one of the outputs S ₁ of the addition value comparator P and the output S ₂ of the measurement value comparator Q is "0", the memory code of the addition code storage circuit J is not updated and the next Shift to the combinatorial calculation of the code.

When all the combination calculations are completed as described above, the 13th bit output _Q13 of counter 2 of the addition code selection circuit G becomes "1", and the calculation end signal is output at the timing of the next clock pulse.
It is output from the AND circuit 4 and stops sending out the clock pulse from the clock pulse oscillator 1. At this time, the output _S3 of the allowable error range check of the addition comparison circuit H is "1", that is, the addition value β of the addition combination code stored in the addition code storage circuit J is the upper limit setting value c and the lower limit setting value. b, that is, if b≦β≦c, the output of the AND circuit 6 becomes “1”, and the storage command signal generation circuit G
AND circuits 15a, 15b...15m constituting 2
Among them, the output of the AND circuit 15a corresponding to the first addition code storage circuit J-1 to which the "1" output of the first step of the decoder counter R is input becomes "1", and the first addition code is Memory circuit J-
1, a memory command pulse CP ₁ is output. Next, this pulse CP ₁ causes the first addition code storage circuit J-1 to store the addition combination code stored in the addition code storage circuit J, and also stores the addition combination code stored in the addition code storage circuit J through the emission control circuit M and the OR circuit 24. This pulse CP ₁ is then sent to the drive motor of the conveyor D. Then, the conveyor D starts running, and a discharge signal d is sent from the control circuit Ma of the discharge control circuit M to the weighing machine corresponding to the addition combination code stored in the first addition code storage circuit J-1 as described below. ₁ , _d2
..., and the objects to be weighed are sequentially discharged from the weighing hopper of the corresponding weighing machine into the bucket _E1 of the conveyor D and collected. The weight of the object to be weighed collected in the bucket E ₁ is within the tolerance range and is equal to or closest to the set weight value a ₀ .

On the other hand, when the calculation end signal is output from the AND circuit 4, the output of the addition and comparison circuit H is now
Since _S3 is "1", the Q output of the flip-flop FF remains unchanged and remains "0". On the other hand, even in the delay operation of the delay circuit 12, the clock signal CLK is input to the binary counter 8 of the decoder counter R after the delay time, so the decoder output of the decoder counter R is "1" only in the second step.
becomes. Therefore, the selection pattern register K sends all the memory data of the addition code storage circuits other than the second addition code storage circuit J-2 selected by the decoder output of the decoder counter R to the bit check circuit L. In this case, the combination code stored in the first addition code storage circuit J-1, that is, the combination code closest to the set measurement value _a0 , is sent to the bit check circuit L.

Then, the conveyor D runs and buckets.
While the objects to be weighed are being sequentially collected in _E1 , a calculation start signal is again applied from the packaging machine to the electronic calculation circuit shown in FIG. 2, for example, to perform a second combination calculation. That is, in the second combination calculation, the code currently stored in the first addition code storage circuit J-1 is within the allowable error range from the remaining addition combination codes excluding the related addition combination code, and within the setting. Weighing value
Select the optimal combination code that is equal to or closest to a ₀ .

Now, the optimal addition combination code stored in the first addition code storage circuit J-1 as a combination code within the tolerance range and having a value equal to or closest to the set measurement value a ₀ is, for example, X ₁ +X ₂ Then, from among _{the remaining 10 combinations of code numbers X 3 to} X ₁₂ excluding each code number _{X 1} and This is to select the optimal combination that results in a value.

When the second calculation start signal is input, the counter 2 of the addition code selection circuit G is activated again as described above.
The outputs Q ₁ , Q ₂ ...Q ₁₃ of Q 1 , Q ₂ , .
Q ₂ ...occurs from Q ₁₂ . At the same time, each code output x ₁ , x ₂ , . _. . Also, the calculation start signal is also sent to the AND circuit 7,
Since the Q output of the flip-flop FF remains at "0", the output of the circuit 7 remains at "0". On the other hand, the selection pattern register K is stored in the first addition code storage circuit J-1 because the decoder output of the decoder counter R has been switched to "1" only in the second step at the end of the previous combination calculation. The addition combination code X ₁ +X ₂ is sent to the bit check circuit L. In other words, the circuit L
Each input of Kx ₁ and Kx ₂ is set to "1".

Then, in the same manner as the previous combination calculation, in the addition comparison circuit H, the addition combination codes sequentially output from the counter 2 of the addition code selection circuit G are added by the first adder N-1 of the combination codes at that time. The value α is compared with the added value β of the second adder N-2 of the addition combination code stored in the addition code storage circuit J by the added value comparator P, and the added value α is compared with the set measurement value. A ₀ is compared with the measured value comparator Q, and the added value β is compared with the lower limit setting value b and the upper limit setting value c using the lower limit setting value comparator r and the upper limit setting value comparator S, respectively, and a bit check is performed. The current combination code of each combination code in circuit L,
A bit check is performed with the optimum combination code in the first combination calculation stored in the first addition code storage circuit J-1.

As a result, α<β, α≧a ₀ , that is, the comparison output
S ₁ and S ₂ are both “1” and bit check output
When BCK is also "1", the combination code at that time is stored in the addition code storage circuit J at the timing of the next clock pulse, and the above three outputs S ₁ ,
If at least one output of S ₂ and BCK is "0", the combination code at that time is not stored in the addition code storage circuit J. In other words, the process moves to the next code combination calculation without updating the stored code.

The output BCK of the above bit check circuit L is “0”
The reason why I decided not to update the memory code at this time was when the objects to be weighed selected in the first combination calculation were being collected one after another into the bucket _E1 .
Since the combination calculation is performed from the second time onwards, the optimal combination code selected before the previous time or the additive combination code related to each code number will not be selected as the optimal combination code in the next combination calculation. This is to make it so.

When all the combination calculations for the second time are completed in this way, the 13th bit output _Q13 of the counter 2 of the addition code selection circuit G becomes "1", and the calculation end signal is output from the AND circuit 4. The clock pulse oscillator 1 stops sending out clock pulses, and the decoder counter R now reads:
Since the second bit output is "1", the storage command pulse _CP2 is output from the storage command signal generation circuit _G2 to the second addition code storage circuit J-2. Then, even with this pulse CP ₂ , the combination code that is within the tolerance range stored in the addition code storage circuit J and that is equal to or closest to the set measurement value a ₀ , that is, the optimal combination code, is selected as the 2 is stored in the addition code storage circuit J-2, and this pulse CP ₂ is also stored in the emission control circuit M.
It is sent to the conveyor D via the OR circuit 24, and is now weighed from the weighing hopper of the weighing machine corresponding to the optimal combination code stored in the second addition code storage circuit J-2 in the same way as the previous time, as described below. Items are sequentially discharged into bucket E ₂ and collected.

On the other hand, as in the case of the previous combinational calculation, since the output _S3 of the addition/comparison circuit H is now "1", the Q output of the flip-flop FF remains "0" and remains unchanged. . On the other hand, even with the delay operation of the delay circuit 12, the binary counter 8 of the decoder counter R receives the clock signal after the delay time.
Since CLK is input, the decoder output of the decoder counter R becomes "1" only in the third step. Therefore, the selection pattern register K transfers all the memory data of the addition code storage circuits other than the third addition code storage circuit J-3 selected by the decoder output of the decoder counter R to the bit check circuit L.
In this case, the two types of combination codes stored in the first and second addition code storage circuits J-1 and J-2 are sent to the bit check circuit L.

Then, while the conveyor D is running and collecting the objects to be weighed selected in the first and second combination calculations into the buckets _E1 and _E2 ,
For example, a calculation start signal is input again from the packaging machine to the electronic calculation circuit shown in FIG. 2, and a third combination calculation is performed. In this third combination calculation, the addition combination code related to the codes currently stored in the first and second addition code storage circuits J-1 and J-2 is calculated using the same method as described above. From the remaining addition combination codes, select the optimal combination code that is within the tolerance range and is equal to or closest to the set weighing value a ₀ , and the object to be weighed selected by this combination calculation is placed in a bucket. Collect within ₃ .

In this way, the collection of the objects to be weighed selected in the first combination calculation is completed, and the objects to be weighed are again supplied from the pool hopper to the weighing hopper that has been emptied after discharge, and the weighing hopper is The combination calculation is performed m times until it becomes possible to participate in the combination calculation again, and each time the combination calculation is completed, the collection operation of the objects to be weighed selected in the combination calculation of that time is started.

Then, when the mth combination calculation is completed,
The decoder counter R returns to its initial state, and the decoder output becomes "1" only in the first step.
After this, the (m+1)th combination calculation is started. At this time, the bit check circuit L operates on the second, third,... m-th addition code storage circuits J-2, J-3,...
The addition code stored in J-m, that is, the addition code selected in the second to m-th combination calculations, is sent to the first addition code storage circuit J.
The addition code selected in the first combination calculation stored in -1 will not be sent to the bit check circuit, but when the m+1th combination calculation starts, the addition code selected in the first combination calculation will not be sent to the bit check circuit. The selected weighing hopper is again supplied with the object to be weighed and is ready to participate in the combination calculation, so there is no problem.

From then on, the above operations are automatically repeated and m
+ 2nd time, m + 3rd time... 2m + 1st time, 2m + 2nd time, etc. The combination calculation is performed.

Therefore, β obtained by the second adder N-2 in the addition/comparison circuit H is the addition value with the smallest error with respect to the set measurement value other than the addition value for the addition combination code to which each combination code and each code number are related. , and indicates the value closest to the set measurement value. Therefore, the addition code storage circuit J stores the addition combination code that is closest to the set measurement value among the combination codes other than the optimal combination code selected in the previous combination calculation and the addition combination code to which each code number relates. , the optimal combination code is stored, and the addition value comparator P compares the addition value of the current combination code with the value that was closest to the previous set measurement value, and the comparison Stored only if the current value is closer to the set value than the past value and the result is other than the optimum combination code selected in the previous combination calculation and the value for the related addition combination code of each code number. The update is performed.

On the other hand, in each combination calculation, when all the combination calculations are completed, if the output _S3 of the allowable error range check in the addition comparison circuit H is "0", that is, the addition code storage circuit Weighing value set to J
If the addition value β for the addition combination code stored as the combination closest to a ₀ is smaller than the lower limit setting value b or larger than the upper limit setting value c, that is, in the case of β<b or β>c, Even with the computation end signal output from the AND circuit 4, the Q output of the flip-flop FF becomes "1", but the output of the AND circuit 6 remains "0" and the clock signal CLK is not input to the decoder counter R. ,
The decoder output of decoder counter R does not change. Therefore, the storage command pulse CP is not output from the storage command signal generation circuit G2, and the addition combination code stored in the addition code storage circuit J is the first,
2nd...m-th addition code storage circuit J-1, J-2
.

Then, when the next calculation start signal is input, each code output x ₁ , x ₂ , _... When the output of the AND circuit 7 becomes "1", the preset signal generation circuit G1
Among the AND circuits 13a, 13b...13m, the output of the AND circuit selected by the decoder counter R becomes "1", and the first, second...m-th addition codes input the output of the circuit. Memory circuit J-
Each code output of any one of 1, J-2...J-m is preset to "0". And after this,
Subsequently, combination calculations are performed to recalculate the optimal combination code. Immediately after the start of the combination calculation, the Q output of the flip-flop FF is returned from "1" to "0" again by the Q output of the counter 2 of the addition code selection circuit G and the clock pulse from the clock pulse oscillator 1 (second (see figure).

When this combination calculation is completed, it is determined that the combination code stored as the optimal combination code in the addition code storage circuit J does not fall within the allowable error range, and the output _S3 of the allowable error range check becomes "0". If this occurs, either stop the operation of the entire weighing device and issue an alarm, or run the conveyor D in reverse to collect the objects to be weighed from all weighing hoppers into a bucket, and then remove the objects from one end of the conveyor D to a suitable location. After discharging the objects to be weighed and re-supplying all the weighing hoppers with the objects to be weighed, recombination calculations are performed for all the weighing values, or after additionally feeding objects to be weighed to at least one weighing hopper, the recombination calculation is performed for all the weighing values. A circuit for performing recombination calculations shall be provided.

As mentioned above, since the combination calculation is performed on the weight contained in each weighing hopper, that is, the weighing value, each weighing machine may set the weight independently, and
Since the number of items can be set, if a weight signal of the contents of each weighing hopper is sent out, items of a set weight can be automatically selected and taken out. In addition, in addition to weight setting, when limiting the number of pieces, set the number of pieces to be weighed at one time in each weighing hopper as a constant number, and combine the addition codes so that the number of combination codes becomes the desired number. , and then calculate the set weight as described above.

Note that the addition and comparison circuit H in the embodiment of this invention
Although addition and comparison are performed for analog values as shown in FIG. 7, it goes without saying that a circuit that performs these operations for digital values may also be used.

Furthermore, in the embodiment of the present invention, an N+1-bit binary counter is used in the addition code selection circuit G to generate the combination pattern of addition codes, but in this case, the first weighing machine and the Nth weighing machine The temporal changes in selection opportunities in combination calculations are very different, and the selection and non-selection of the first weighing machine differs each time due to changes in the clock pulse, but the selection opportunities of the Nth weighing machine are selected from ^{the 2N-1st} time onwards. (See Figure 14). Therefore, the combination calculation speed is
This is determined by the analog addition/comparison circuit (Figure 7) and this clock pulse, and since the window time for external noise is different, the probability of all weighing machines being selected is not equal, which affects the durability of the device. It may be harmful. Therefore, in order to equalize the above-mentioned probabilities, it is also possible to use a combination pattern generation method using a pseudo-random signal such as an M-sequence signal.

Furthermore, the electronic calculation circuit of FIG. 2 according to the present invention divides each measurement value measured by each weighing machine by the single weight of the object to be weighed, converts it into a piece value, and performs a combination calculation for the piece value. It can also be applied to a so-called combination counting device that obtains a set number of objects or the number closest to it. In this case, instead of each weighing value a ₁ , a ₁ ...a _o , All you have to do is input the number of items to be weighed.

Next, open the weighing hopper of the weighing machine that corresponds to the optimal combination code obtained by the combination calculation, and transfer the objects in the weighing hopper to each bucket of conveyor D.
The case of collecting in one bucket among E ₁ , E ₂ . . . E _o will be explained.

First, when the calculation end signal is issued, one bucket E ₁ of the conveyor D shown in FIG. 1 is located _directly below the weighing hopper B ₁ of the first weighing machine A 1.
When the bucket E ₁ travels and comes directly below the seventh weighing hopper B ₇ , the next bucket E ₂ is located directly below the first weighing hopper B ₁ ,
At this time, the positions of the buckets E ₁ , E ₂ , . . . E _o are mechanically determined in advance so that the next calculation end signal is output.

Then, a calculation end signal is output from the AND circuit 4,
Storage command pulse from storage command signal generation circuit G2
When CP is output, the optimum combination code stored in the addition code storage circuit J as described above for the pulse is transferred to the first, second...mth addition code storage circuits J-1, J-2...J. At the same time, the pulse is sent to the conveyor D and the discharge control circuit M, and the conveyor D starts running. A discharge timing pulse TP is sent to the discharge control circuit M every time the discharge timing pulse TP comes directly below the discharge control circuit M. On the other hand, for example, if a storage command pulse CP ₁ is output from the storage command signal generation circuit G2, the discharge control circuit _M shown in FIG.
is input to the pulse generation circuit 22 of the control circuit Ma corresponding to the first addition code storage circuit J-1, and at this time, for example, the bucket E ₁ is positioned directly below the first weighing hopper B ₁ . Therefore, for each input of the discharge timing pulse TP that is input when the bucket _E1 travels and comes directly below the weighing hopper, the pulses are sent to the logic circuit in chronological order from output Q ^A to output Q ^L. 23.

Even with the storage command pulse CP ₁ , the optimal combination code transferred and stored from the addition code storage circuit J to the first addition code storage circuit J-1 is, for example, X ₂ +
If it is X ₅ , each input of x ₂ and x ₅ of control comparison Ma will be "1", and bucket E ₁ will be the second, 5
When the weighing hoppers B ₂ and B 5 come directly under each of the weighing hoppers B 2 and B ₅ , a match is made with each "1" output of Q ^B and Q ^E of the pulse generation circuit 22, and the corresponding weighing hoppers are sequentially removed from the logic circuit 23. Ejection signals d ₂ and d ₅ are sent to B ₂ and B ₅ . The objects to be weighed are sequentially discharged from each weighing hopper B ₂ and B ₅ into the bucket E ₁ and collected. The value of the object to be weighed collected in the bucket E ₁ is within the tolerance range and is equal to or closest to the set weight.

It should be noted that the other control circuits Mb...Mm also perform the same operation as the control circuit Ma described above when the respective storage command pulses _CP2 ... _CPn are input to the pulse generation circuit 22.

In addition, if the optimal combination code exists for each combination calculation, the storage command pulses CP ₁ , _{CP 2} . While driving, the objects to be weighed are transferred into separate buckets from the weighing hoppers corresponding to the optimal combination codes stored in the first, second...m-th addition code storage circuits J-1, J-2...J-m. will be collected.

In the embodiment shown in FIG. 1, one conveyor D and a plurality of buckets E ₁ , E ₂ . _. . With 12 weighing machines, one conveyor collects the objects to be weighed from the 1st to 6th weighing hoppers, and the other conveyor collects the objects to be weighed from the 7th to 12th weighing hoppers. This can also improve collection efficiency.

In addition, instead of the main stage for collecting objects to be weighed using a conveyor, each weighing machine is arranged around the circumference, and the objects to be weighed that correspond to the optimal combination code are simultaneously discharged from the weighing hopper and delivered to one place via one collection chute. However, in this case, the head distance in the collection chute becomes large, so the collection chute is set so that the objects to be weighed that were discharged last time do not mix with the objects that will be discharged next time. Requires special ingenuity or equipment.

The above explanation was based on the case where combined weighing was performed using 12 weighing machines, but the object to be weighed is discharged from the weighing hopper, the object to be weighed is supplied to the weighing hopper, and In order to perform the combination calculation a predetermined number of times using the remaining weighing hopper before the weighing machine can participate in the combination calculation again, it is actually necessary to perform the combination calculation using many weighing machines. It's better.

Furthermore, although the electronic calculation circuit shown in Fig. 2 is shown as a hardware circuit in order to specifically explain its operation, in reality it is necessary to add various check functions, and therefore a microcomputer or microprocessor is required. It is preferable to perform software processing using, for example. As an example of a program in this case, the flowchart in FIG. 15 is shown.

As explained above, in the combination weighing method of the present invention, objects to be weighed that correspond to the optimal combination are discharged from the weighing machine, and after being discharged, new objects to be weighed are supplied to the empty weighing machine, and the weighing objects are then weighed. By the time the value of the object to be weighed that has been supplied to the weighing machine becomes ready to participate in the combination calculation again, the value of the remaining objects to be weighed that is currently being supplied to the weighing machine must be equal to or close to the set value. The operation of obtaining the optimum combination is performed a predetermined number of times, and the objects to be weighed corresponding to the optimum combination obtained in each calculation are sequentially discharged from the weighing machine, so that high-speed weighing can be performed. Measurement ability will be improved.

In addition, the advantage of conventional combination calculations is that variations in unit weight do not directly affect weighing accuracy, making it possible to perform very high precision weighing.
Disturbances in supply and alignment do not directly lead to measurement errors, and even if the set value becomes large, high accuracy can be maintained.Also, since it is a combination of the actual weighing values of each weighing machine, the accuracy of each weighing machine is Errors in settings do not affect the final error, and each unit weight, single item, one bag,
It is ideal for assembling or packaging items to be weighed that vary in weight per bucket to a predetermined weight or number of items.In particular, the error curve has an extremely large number of items near zero, which is ideal, and it is ideal for items that deviate from the optimal combination. Since the object to be weighed remains as it is for the next combination calculation without being processed, it has the effect that the advantages such as not damaging the object to be measured can be utilized as is.

[Brief explanation of drawings]

The drawings all show one embodiment of the present invention; FIG. 1 is a schematic diagram of the weighing and collection mechanism for objects to be weighed, and FIG. 2 is a block diagram of the electronic calculation circuit. Figures 3 to 11 show more detailed block circuit diagrams of individual circuits in the electronic calculation circuit of Figure 2. Figure 3 is an addition code selection circuit diagram, and Figure 4 is a decoder counter circuit diagram. Figure 5 is a preset signal generation circuit diagram, Figure 6 is a storage command signal generation circuit diagram, Figure 7 is an addition/comparison circuit diagram, and Figure 8 is a circuit diagram of a preset signal generation circuit.
The figure is an addition code storage circuit diagram, and Figure 9 shows the first and second
... FIG. 10 is a circuit diagram of the m-th addition code storage circuit, FIG. 10 is a circuit diagram of a selection pattern register, FIG. 11 is a bit check circuit diagram, and FIG. 12 is a discharge control circuit diagram. Also, Fig. 13 is a diagram of the output waveform of the addition code selection circuit in the electronic calculation circuit of Fig. 2, Fig. 14 is a diagram of the combination pattern of code numbers attached to each weighing machine or each weighing hopper, and Fig. 15 is a diagram of the combination pattern of code numbers attached to each weighing machine or each weighing hopper. 1 is a flowchart showing an example of a program when processing software using a microcomputer, microprocessor, etc. A ₁ ~ A _o ... Weighing machine, B ₁ ~ B _o ... Weighing hopper, C ₁
~C _o ...pool hopper, D...conveyor, E ₁ ~ _{E 4}
...bucket, F...discharge timing pulse generator,
G... Addition code selection circuit, G1... Preset signal generation circuit, G2... Storage command signal generation circuit, H... Addition comparison circuit, J... Addition code storage circuit, J-1,
J-2...J-m...1st, 2nd...m-th addition code storage circuit, K...selection pattern register, L...bit check circuit, M...discharge control circuit, Ma, Mb
...Mm...Control circuit, N-1...First adder, N-
2...Second adder, P...Additional value comparator, Q...Measurement value comparator, R...Decoder counter, r...Lower limit set value comparator, S...Upper limit set value comparator, FF...Flip-flop, _a0 ... Set weighing value, a ₁ ~ a _o ... Weighing value (signal), b... Lower limit set value, c... Upper limit set value, d ₁ -
d _o ...discharge signal, _S1 ...added value comparison output, _S2 ...weighed value comparison output, _S3 ...tolerance range check output,
CP ₁ , CP ₂ ...CP _n ...memory command pulse, TP...discharge timing pulse, BCK...bit check output,
x ₁ ~ x _o , Kx ₁ ~ Kx _o ... code output.

Claims (1)

[Claims] 1. The measurement values obtained by weighing multiple objects to be weighed or the number of objects obtained from these measurement values are combined and calculated by comparing them with the set values, and the optimum combination is obtained and the weight of the weighing machine corresponding to this is calculated. In a combination scale that discharges objects to be weighed, there is a process of combining based on weighing signals from a plurality of weighing machines, a process of comparing the combined weight or number of pieces with a set value to find the optimal combined weight or number, and a process of combining the above-mentioned items. The process of storing the combination code of the weighing machines in one of the many disposed addition code storage sections by a storage command signal, and discharging the object to be weighed from the weighing machines participating in the above combination by a discharge control signal; While discharging objects, the remaining weighing machines that did not participate in the above combination are compared with the set value to find the optimal combination of combination weight or number of pieces, and this combination code is stored in the above-mentioned large number of addition codes by the above-mentioned storage command signal. The object to be weighed is then stored in another storage section of the unit, and the object to be weighed is ejected from the weighing machine that participated in the second combination using the discharge control signal, and the weighing machine that participates in the above combination is repeatedly repeating the above operation until the weighing machine becomes empty. A combination weighing method characterized by supplying objects to be weighed to a weighing machine and having them participate in a weighing combination when they are ready to participate in the combination.