JPH0136736B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a logic circuit miniaturized by a combination of complementary MOS transistors. Conventionally, when obtaining two or more logic outputs from several types of inputs, complementary MOS transistor circuits with symmetrical configurations were required for each input signal, equal to the number of logic outputs, and several transistors with the same configuration were created. I had to. The above will be explained using the drawings. The conventional logic circuit, as shown in FIG.
The circuit of X=・ in Figure a and Y= in Figure 1 b
It consists of A, B+C, D, and E circuits. In order to obtain these two outputs, conventionally, two mutually independent and symmetrical complementary MOS transistor circuits are generally used, and the logic thereof is as shown in the truth table shown in Table 1.

【table】

[Table] In this case, P type inputs A and B to the gate.
The disadvantage was that MOS transistors had to be made in common, and a large number of transistors were required to obtain the same logical output. An object of the present invention is to eliminate such drawbacks and provide a logic circuit that is miniaturized by combining integrated circuits. A logic circuit according to the present invention includes a first MOS transistor of a first conductivity type having a source-drain path connected between a first power supply terminal and a first output terminal; a second MOS transistor of the first conductivity type having a source-drain path connected between the output terminal and the second output terminal; and a source-drain path connected between the second output terminal and a second power supply terminal. a third MOS transistor of a second conductivity type; a fourth MOS transistor of the second conductivity type having a source-drain path connected between the first output terminal and the second power supply terminal;
a fifth MOS transistor of the second conductivity type, the fifth MOS transistor having a source-drain path connected in parallel with the source-drain path of the third MOS transistor between the second output terminal and the second power supply terminal;
means for commonly supplying an input signal to the gates of the first, fourth and fifth MOS transistors, and means for commonly supplying a second input signal to the gates of the second and third MOS transistors. Features. In this way, according to the present invention, complementary types of predetermined logic
Since a MOS transistor circuit can have as many different logic outputs as its nodes (output points), the number of transistors required to configure the logic of conventional symmetrical complementary MOS transistors can be reduced by using P-type MOS transistors in common. Therefore, the number of transistors can be reduced by that number, and as a result, the degree of integration for the same function can be improved. Next, the present invention will be explained in detail using the drawings. FIG. 2 is a circuit connection diagram showing one embodiment of the present invention. As shown in this figure, according to the asymmetrical complementary circuit according to the present invention, the number of transistors is 12, which is higher than the number of transistors (14) in the conventional configuration shown in Figures 1a and 1b. , the number of MOS transistors required to obtain the same logic output can be reduced by two. Next, it will be explained that the logic circuit shown in FIG. 2 has the same output as the two logic circuits shown in FIGS. 1a and 1b. This circuit is a symmetrical complementary logic circuit that obtains one logic output
MOS transistor source and another P type
The connection point with the drain of the MOS transistor is set as one output point X, and a P-type MOS is connected to this output point.
It is constructed by adding an output point Y of a transistor circuit. The logic obtained by adding a load resistance between this output point Y and the reference potential is Y=・+・
D and E, and the n-type complementary to this logic
A MOS transistor circuit is installed between the output point Y and the reference potential. It will be explained that such logical outputs X and Y in the present invention are obtained mutually independently and without interference. In FIG. 2, the sources and drains of transistors Q _PA and Q _PB are connected, and the sources and drains of transistors Q _PC , Q _PD , and Q _PE are connected, respectively. In addition, the transistor Q _oe has Y as the source and Z ₁ as the drain, and the transistor
Q _oD has Z ₁ as the source and Z ₂ as the drain, and transistor Q _oE has Z ₂ as the source and the reference potential as the drain. Transistor Q _oA uses Y as the source
The transistor Q _oB has Z ₃ as its drain and _the reference potential as its drain.
Q _oA ' has X as the source and Z ₄ as the drain, and transistor Q _oB ' has Z ₄ as the source and the reference potential as the drain. Figure 3 shows these transistors Q _PA and Q _PB .
HA, transistors Q _PC , Q _PD , Q _PE to HB, transistors Q _oC , Q _oD , Q _oE to HC, transistors Q _oA ,
This is an equivalent circuit diagram in which Q _oB is replaced with HD, and transistors Q _oA ′ and Q _oB ′ are replaced with HD′. This transistor HA
When is conducting, transistor HD, HD′ is non-conducting,
When transistor HA is non-conducting, the transistor
HD, HD′ are conductive, when transistor HB is conductive, transistor HC is non-conductive, transistor HB
When is non-conductive, transistor HC is conductive and transistors HA, HD, HD′ and transistor HB,
HCs are independent of each other. Regarding the output X, if the transistor HB is conductive, the transistor
Since HC is non-conducting and transistors HD and HD′ have the same input and common source and drain, ・If transistor HB is non-conducting, the output will occur regardless of whether transistors HC and HD are “0” or “1”. becomes ・, and the output X is HB,
Does not depend on HC. Regarding the output Y, when the transistor HA is conductive, the transistor HD' is non-conductive, so it does not depend on the transistor HD'.When the transistor HA is non-conductive, the transistor HD is conductive and outputs a low level with a sufficiently low potential Y Y becomes the reference potential. As a result, Y becomes independent with respect to the transistor HD', and the logic circuits a and b in FIG. 1 and the logic circuit in FIG. 2 can be said to be equivalent. In this way, the MOS logic circuit of the present invention has a complementary MOS transistor circuit having a predetermined logic output, and another logic output including the logic output at the node of the output point where the source and drain of the P-type MOS transistor are connected. is realized by adding an N-type MOS transistor logic circuit that is complementary to the logic of the P-type MOS transistor, and the number of other logic outputs that can be obtained from one logic output is determined by the source and drain nodes of the P-type MOS transistor logic circuit. Match the score.

[Brief explanation of drawings]

Figures 1a and 1b are circuit diagrams of conventional MOS logic circuits,
FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is an equivalent circuit diagram illustrating FIG. 2. In the figure,
Q _PA , Q _PB , Q _PC , Q _PD , Q _PE ... P-type MOS transistor, Q _oA , Q _oB , Q _oC , Q _oD , Q _oE , Q _oA ′,
Q _oB '... n-type MOS transistor, X, Y... output point (node), Z ₁ , Z ₂ , Z ₃ , Z ₄ ... contact.

Claims (1)

[Claims] 1 a first MOS transistor of a first conductivity type having a source-drain path connected between a first power supply terminal and a first output terminal; a second MOS transistor of the first conductivity type having a source-drain path connected thereto; a second MOS transistor of the second conductivity type having a source-drain path connected between the second output terminal and a second power supply terminal; a 3MOS transistor of the second conductivity type having a source-drain path connected between the first output terminal and the second power supply terminal;
4MOS transistor, the second conductivity type transistor having a source-drain path connected in parallel with the source-drain path of the third MOS transistor between the second output terminal and the second power supply terminal;
5MOS transistor, means for commonly supplying a first input signal to the gates of the first, fourth and fifth MOS transistors, and means for commonly supplying a second input signal to the gates of the second and third MOS transistors. A MOS logic circuit having at least