JPH0136292B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel multiplexed loop transmission system.

FIG. 1 is a block diagram showing an example of the configuration of a loop transmission system to which the present invention is applied.
1c is a transmission device, and when it generally means any one transmission device, it is written as transmission device 1.
2 indicates a transmission line, and 3 indicates a frame that circulates in the direction of the arrow on the transmission line 2. In the example shown in the figure, frame 3 includes four data transfer channels CH0 to CH3, and 4 is a management device. be.

Figure 2 is a format diagram showing the structure of frame 3, in which a frame synchronization word (hereinafter abbreviated as SYN) is placed at the beginning of the frame outside of data transfer channels CH0 to CH3, and is transmitted using a word with a special bit pattern. The device 1 and the management device 4 detect this bit pattern to detect the position of the channel within the frame and the position of the field within the channel. In addition to the information field, an access key K is placed on each data transfer channel.
For example, is a 1-bit signal, and when it is logic 0, it indicates that the channel is unused and accessible, and when it is logic 1, it indicates that the channel is used and cannot be accessed. show.

In many cases, the transmission device 1 and the management device 4 include a shift register having a parallel signal output terminal and a parallel signal input terminal, and a frame shown in FIG. 2 is connected from the transmission line 2 to the serial signal input terminal of the shift register. Each bit is sequentially inputted, shifted within the shift register by a predetermined clock, outputted from the serial signal output terminal of the shift register to the transmission line 2, and inputted to the subsequent transmission device 1. Therefore, the signal that has been attenuated and waveform distorted by the transmission line 2 becomes a waveform-shaped signal at the output end of the transmission device 1 or the management device 4. The transmission device 1 receives necessary information from the parallel signal output terminal of its own shift register, inputs the information to be transferred from the parallel signal input terminal of the shift register to the shift register, and transmits the information to the transmission line 2.
Send to. The calling/receiving address is placed in the information field and sent.

The transmission device 1 with a signal transfer request checks the logic of the access key K, and if it detects an access key K with logic "0" indicating that the channel is unused, it changes the logic of the access key K to "1". , then transfer data using that channel, and when the transfer is completed, the access key K for that channel is
Return the logic to "0".

Since the conventional data transfer method is performed as described above, bit errors may occur due to noise etc. while frame 3 is circulating on transmission path 2. If the access key K becomes a logic "1" instead of a logic "0", then the access key K remains at a logic "1" and no transmission device 1 can use the channel. This has the disadvantage that the transfer capacity of the transmission line 2 is reduced.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method.
Even if the access key K indicates that the channel is still in use (a channel in this state is called a blocked channel), the logic of the access key K is forcibly changed after a predetermined period of time. 0'' and can recover a blocked channel.

Embodiments of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram showing an embodiment of the present invention, in which 2a and 2b indicate the input end portion and output end portion of the transmission line 2 to the management device 4, respectively, 10 is a shift register, 11 is a buffer, and 12 is a block diagram showing an embodiment of the present invention. 13 is a synchronization circuit, 13 is an access key identification circuit, 14 is a timer, 15 is a detection unit, 16 is a recovery unit, 100 to 11
0 is a signal line.

FIG. 4 is a flowchart for explaining the operation of the circuit shown in FIG. 3, and (400) to (409) indicate each step. The operation of the circuit shown in FIG. 3 will be explained below using FIG. 4.

(b) After confirming that all blocked channels have been recovered in step (409), the signal line 101 is
The timer 14 is activated by the signal on the signal line 100 or by the signal on the signal line 100 when starting the operation in step (400).

(b) When the timer 14 is started, the signal logic on the signal line 102 becomes "1", and the detection unit 15 and the recovery unit 1
6 is initialized (step (402)) and the detection unit 15
Set the display flag in to indicate that all channels are in use.

(c) When the frame 3 shown in FIG. 2 arrives from the transmission line 2a to the management device 4 with SYN (frame synchronization word) at the beginning and passes through the shift register 10, the access of each channel is sent from the parallel signal output terminal of the shift register 10. The contents of the key K are temporarily stored in the buffer 11 via the signal line 103. The contents of the access key K stored in the buffer 11 are input to the access key identification circuit 13 via a signal line 107. Access key identification circuit 13
checks the logic of the access key K, and if the logic is "0", it notifies the detecting unit 15 via the signal line 108 that the channel passing through the shift register 11 is empty (step (403)).

(d) The detection unit 15 receives an empty channel notification from the access key identification circuit 13 via the signal line 108;
The display flag of the corresponding channel is set to an unused state by a signal transmitted from the synchronization circuit 12 via the signal line 105 and indicating the number of the channel currently in the shift register 10 (step (404)). Once the display flag is set to an unused state, its contents will not be changed until the next step (401). The above operation is timer 1
4 is repeated for all channels until the operation is completed (step (405)).

(e) When the timer 14 stops (step (405)),
In accordance with step (406), the detection unit 15 investigates whether there is a channel whose display flag is set to the in-use state, that is, a blocked channel, and if there is no blocked channel, the process returns to step (401). If there is a blocked channel, this is transmitted to the recovery unit 16 via the signal line 109.

(f) In the recovery unit 16, the detection unit 1 is connected to the signal line 109.
When the information of the blocked channel is transmitted from 5, the channel number indicated by the signal line 105,
That is, it is determined whether the channel number in the shift register 10 and the blocked channel number match (step (407)).

(G) When the number of the arrived channel matches the number of the blocked channel transmitted from the detection unit 15, the recovery unit 16 sets a logic “0” to the bit of the access key K in the shift register 10 via the signal line 110. Set. The timing of this setting is determined by connecting the access key K from the synchronous circuit 12 to the signal line 106.
It is determined by the signal output as the setting timing (step (408)). This causes the channel to recover from the blocked state,
It is output to the transmission line 2b. Further, the number of the channel recovered from the blocked state is transmitted to the detection unit 15 through the signal line 109, and the display flag of the corresponding channel is set to the unused state. Steps (407) and (408) are repeated for all blocked channels transmitted from the detection unit 15, and when the recovery operation is completed, the timer 14 is activated via the signal line 101 (step (409)).

5 is an operation time chart explaining the operation of the circuit shown in FIG. 3, in which FIG. 5a shows the logic of the signal on the signal line 102, and FIG. Figure c shows frame 3 at the serial signal output terminal of the shift register 10, and the shaded channels are in use,
Channels without diagonal lines indicate an empty state. Figure d shows only the channel CHO, and Figures b and c are displayed together, and Figure e shows the progression of the logic of the display flags for the channel CHO in the detection unit 15. Similarly, f, g in the same figure, h, i in the same figure, j, k in the same figure are channels CH1, CH2, CH, respectively.
3, b and c of the same figure are displayed together to show the logical progression of the display flags. Time _t1 in FIG. 5 indicates the time when the timer ends at step (405) in FIG. 4, and at this point, only the display flag for channel CH1 is at logic "1" as shown in g in FIG. .

Therefore, by checking the point in time when channel CH1 is being input to the shift register 10 between _t1 and _t2 , the signal line 110 is changed by the operation of step (408) in FIG.
Logic “0” is applied to the access key K of channel CH1 from the parallel signal input terminal of shift register 10 through
Set the signal. At time t ₂ , timer 14 is activated again.
is activated (step (401)), and all display flags (e, g, i, k in FIG. 5) are set to logic "1".

In the above description, a case has been described in which the blocked channel recovery function is provided in the management device 4, but the same operation can be performed even if the above function is provided in any of the transmission devices 1.

As described above, in the method of the present invention, the usage status of all channels is monitored for a certain period of time, and a channel that has never become free during this period is determined to be in a blocked state, and the channel is restored to a normal state in a short time. Therefore, the transfer capacity and utilization rate of the transmission path will not be reduced. Furthermore, the method of the present invention can be implemented with a simple circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a loop transmission system to which the present invention is applied, FIG. 2 is a format diagram showing a frame configuration, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. This figure is a flow chart explaining the operation of the circuit shown in FIG. 3, and FIG. 5 is an operation time chart explaining the operation of the circuit shown in FIG. 3. 1a, 1b, 1c...transmission device, 2,
2a, 2b...transmission line, 3...frame, 4...
Management device, 10...shift register, 12...synchronization circuit, 13...access key identification circuit, 14...
...Timer, 15...Detection section, 16...Recovery section,
CH0, CH1, CH2, CH3...each channel, K...access key. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 Multiple transmission devices and one management device are connected in a circular cascade via transmission lines, and a frame configured by arranging multiple channels in a time-division multiplexing system is used to transmit data under the control of the management device. In a data transfer method for transferring data between transmission devices, the steps include setting a signal indicating whether the channel is in use or unused as an access key for each of the plurality of channels; The transmission device requesting the transfer accesses the channel for which the access key is displayed as unused, sets the access key to display the used state, transfers data through the channel, and when the transfer ends, accesses the channel as described above. A step of returning the key to an unused state display, a detection step of detecting an access key that has never been shown to be an unused state within a predetermined period of time, and a detection step of detecting that the access key detected in this detection step is a false display. A data transfer method characterized by comprising the step of determining and returning the unused state display.