JPH01318560A - High-frequency power source - Google Patents

Abstract

PURPOSE:To prevent the overload of a switching element by lowering a supply voltage while the operating frequency of an inverter deviates from a target. CONSTITUTION:A high-frequency power source equipment is composed of an ordinary commercial AC power source 1, a DC power circuit 2 and an inverter circuit 3 to supply a series resonance circuit load 4 with power. Also, the equipment is furnished with an output frequency control circuit 11, a DC power control circuit 15, a driver circuit 16 for the inverter circuit 3 and an output current control circuit 21. The output frequency control circuit 11 is composed of a current phase sensor 111, a voltage phase sensor 112, etc., and the output current control circuit 21 is constituted by an analog switch 212, comparators 213, 217, output clamp diodes 219, 220, etc. Thus, when the operating frequency of an inverter reaches a desired value, the output thereof is regulated not by regulation of the duty of the inverter circuit 3 through PWM control but by regulation of an inverter input power source, and a frequency control system and an output control system are separated from each other to eliminate their mutual intervention.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high frequency power source used as a drive power source for a load having a resonant frequency such as an induction heating or an ultrasonic oscillator. A means is provided to prevent transient overload that is likely to occur in the switching elements constituting the inverter.

[Prior Art] When a load includes an inductive component and a capacitive component, it forms a resonant circuit, which is divided into a series resonant circuit and a parallel resonant circuit depending on the connection state. According to the formula of electric circuit theory, in the former series resonant circuit, the load impedance is lowest at the supplied power supply frequency fO and the resonance frequency fL,
Resonant frequency f.

Since the load impedance increases as it deviates from the range, the substitute load current will not increase even if the '1tg1f number set as the resonant frequency deviates slightly. Conversely, in a parallel resonant circuit, when the frequency deviates from the resonant frequency, the load impedance gradually decreases, resulting in an increase in load current, which may lead to an overload condition.

On the other hand, if we focus on the current flowing through the switching elements that make up Inpar 1, we can see that even in a load with a series resonant circuit, a large peak current flows through the switching elements depending on the power supply frequency (inverter operating frequency), resulting in large power losses in each element. may occur.

FIG. 4 is a connection diagram of an example of a conventional device shown to explain the above phenomenon. In the figure, 1 is an AC power source, and a commercial three-phase or single-phase power source is used. 2 is a DC power supply circuit which includes a rectifier circuit and a smoothing circuit. 3 is an inverter circuit, and is a bridge-connected transistor 3a.

It consists of diodes 3b, 3c, 3d and diodes 3e, 3f, 3g, 3h connected in antiparallel to these.

A load 4 is connected to the output terminal of the inverter circuit 3, and in the figure, the load 4 constitutes a series resonant circuit by a capacitive component 4c and an inductive component 4L. A transformer may be provided between the inverter circuit 3 and the load 4 as necessary.

Reference numeral 5 designates a control circuit for the inverter circuit 3, and its operating frequency is determined by combining the phase of the output f of the oscillation 'a6 which oscillates at the reference frequency with the output phase of the inverter circuit 3 and the signal fo detected by the phase detector 7. The output current is determined by a known PLL control system that operates to match the phases, and the output current is determined by the output Ir of the reference current setter 8 and the output Ir of the output current detector 9.
The output pulse width is determined by a PWM control system in which the output pulse width is controlled by the output of the comparator 10 which compares the output pulse width with the output signal f and obtains the difference signal I=Ir-If.

In the device shown in FIG. 4, the operating frequency f of the inverter circuit
The relationship between the magnitude of o and the resonant frequency fL of the load 4 and the current flowing through the transistors constituting the inverter circuit 3 will be explained with reference to waveform diagrams in FIGS. 5(a) to fcl.

In each waveform diagram, the inverter circuit 3 is shown at maximum output.

FIG. 5 (ml is the output voltage waveform eo of the inverter circuit 3, the output current waveform io, and the current 11 flowing through the transistors 3a and 3b when fo<fL, that is, the load 4 exhibits 6 density).
The current 12 flowing through the transistors 3c and 3d is shown along with the time axis. Similarly, Fig. 5 (powder is fo=fL
, and FIG. 5 shows the waveforms when f is greater than f, that is, the load 4 is inductive. When fQ<fL,
As shown in the figure (at), in the second half of the voltage waveform, current is regenerated from the load 4 side to the DC power supply side through the diode that is inversely parallel to the transistor that was conducting in the first half of the waveform.Now, transistor 3a , 3b are conductive and diodes 3e and 3f are conductive after time t1, this state continues until time t2, and at time t!, transistor 3c replaces transistors 3a and 3b.
, 3d are conductive. Therefore, a reverse voltage is applied to the diodes 3e and 3f and they immediately turn off, but during the period td (reverse recovery time) until the diodes 3e and 3f completely recover from the blocking state, the output of the DC power supply circuit 2 are a diode 3e, a transistor 3c, and a transistor 3d that are conductive in the reverse direction because a reverse recovery current is flowing;
A complete short circuit occurs through the diode 3f, and an abnormally large current flows through these elements. This phenomenon occurs every time a conducting transistor is reversed, and greatly increases the loss of the transistor or diode.

The above phenomenon also occurs when fo=fL for the same reason as shown in FIG. 5 (bl).

Next, fo > fL, and the current waveform lags behind the voltage waveform (more precisely, it lags longer than the reverse recovery time of the diode mentioned above)
When the polarity of the voltage is reversed, only the transistors 3a, 3b or 3c, 3d are conducting, and in the first half of the next half-wave of the voltage waveform, the current flows through the diode to maintain the current that was flowing in the previous half-wave. is regenerated into DC power supply 2.

The diode that is conducting at this time is a diode that is connected in a reverse meandering manner to the transistor that is newly becoming conductive, so even if it takes some time for the diode to recover at the end of the regenerative current, the DC power supply 2 remains connected to Himeji. It never happens. For example, when the transistors 3a and 3b are conductive first and are replaced by the transistors 3c and 3d, the regenerative current due to the back electromotive force of the inductive load is transferred from the load 4 to the diode 3.
h - DC power supply 2 - flows through diode 3g;

When this regenerative current ends, a current in the opposite direction begins to flow from the DC power supply 2 to the load 4 through the transistors 3c and 3d (to which a conductive signal is already supplied) connected in parallel to the diodes 3g and 3h. At this time, since the transistors 3a and 3b have been cut off before this, there is no problem even if the reverse recovery of the diodes 3g and 3h is delayed. In this case, diodes 3g, 3h and transistors 3c, 3
Since the initial current flows through both of the diodes 3g and 3h, the reverse recovery current of the diodes 3g and 3h acts in a direction that helps the load current rise.

On the other hand, in this case, the current flowing when each transistor is cut off is a considerable value (unlike the case of (a) (bl) above, so a loss occurs at turn-off to cut off the current. The loss increases as the current phase delay increases.

FIG. 6 is a diagram showing the relationship between the power loss generated in each transistor constituting the inverter and the operating frequency fo of the inverter. In the same figure, (a) is the average value of the loss generated at turn-on, (b) is the average value of the loss generated at turn-off, (c) is the average value of the loss generated at saturation, and (b) is the above (a). This is the total loss that combines all of the above. As mentioned above, the turn-on loss occurs when the operating frequency fo is slightly larger than the resonance frequency f.

=f! It decreases rapidly after that, and becomes almost negligible after that. This means that the generation of peak current at turn-off as shown in Figure 5 (al and (bl)
This is for naku at f2. In addition, the turn-off loss is a monotonically increasing curve that is approximately proportional to fo when fo≧f2, and becomes an almost negligible value at f, (fL. Roughly speaking, the saturation loss is f.

= h, the conduction period is the longest, and the peak value is limited to a constant value due to constant current control.
It becomes a curve that gradually decreases on both sides of o=fL. As shown in (a) in the figure, the total loss that combines these (a) to c) forms a curve that has a minimum point at a frequency slightly higher than the resonant frequency fL, and increases quite rapidly before and after that point.

Since the conventional device operates as described above, the operating frequency of the PLL yarn control is determined so that in a series resonant load, the operating frequency of the inverter is slightly higher than the resonant frequency of the load to minimize the generated loss.

On the other hand, in a parallel resonant load, the operating frequency f.

If fo deviates from the resonant frequency fL, the load current increases rapidly, so it is controlled so that fo=fL.

[Problem to be solved by the invention]

Since the conventional device operates as described above, it is operated at a frequency set so that the generated loss is minimized during steady operation.

However, when starting up the power supply, it takes some time for the PLL control system to reach the target frequency, and during this transient period, overcurrent flows through the switching elements as described above, and losses increase. It will pass through the overhead of such a frequency.

In general, even after reaching a -degree steady state of operation, there may be sudden changes in the load, such as sudden changes in the distance between the induction coil and the heated object when used for induction heating, or magnetic transformation due to the progress of heating. When the resonant frequency of the load changes suddenly, as when the load exceeds the point, even if this is detected and the frequency of the reference oscillator is changed, the PLL 1 will change to this new resonant frequency.
Until the lilJ control system follows suit and stabilizes, the switching elements are in a dangerous state, just like at startup. A similar situation also occurs when some kind of disturbance occurs in the control system due to the introduction of noise or the like.

As a method to solve the above problem, the duty of the PWM control system of the inverter is made small at startup, and the output current is gradually increased from a small value to a target value. It is being considered to adopt a so-called soft start method.

However, even in this soft start method, fo<fL
The peak current described above in FIG. 5 occurs in the frequency range of . T-fatty. Furthermore, if the frequency deviates from the desired optimum frequency due to disturbances after startup, the soft start method cannot solve the problem at all. Therefore, in order to solve all of these problems, there is no other way than to use a switching element with a large capacity that far exceeds the output power. Furthermore, even if large-capacity switching elements were used, in conventional devices, both output control and frequency control were performed by inverter control circuits, so the two split aI systems were likely to interfere with each other. In order to prevent this, it is necessary to make one of the two control systems the main one, and make the other one the slave control system, and take measures to avoid interference by slowing down the response speed or lowering the gain of the slave control system. ,
For this reason, there was a drawback that the desired function could not be sufficiently obtained.

[Means to solve the problem]

In the present invention, the inverter is operated at a constant duty regardless of the output, and the output voltage of the DC power source that is the power source of the inverter is reduced during startup or while the operating frequency of the inverter deviates from the target frequency due to some reason. While the operating frequency of the inverter matches the target value, the above restriction on the DC power supply is canceled and the output of the DC power supply, that is, the input power of the inverter, is By adjusting K, the above-mentioned drawbacks of the conventional device are solved.

[Effect]

The present invention prevents overloading of the switching elements constituting the inverter by lowering the power supply voltage while the operating frequency of the inverter deviates from the target, and
When the operating frequency reaches the target value, adjust the output by P
Rather than adjusting the inverter duty using WM control, this is done by adjusting the input power source of the inverter, separating the frequency control system and output control system to eliminate mutual interference and achieve optimal response for both. The feed rate and gain can be set.

〔Example〕

FIG. 1 is a connection diagram showing an embodiment of the present invention.

In the figure, reference numeral 1 denotes an AC power source, and a commercial AC power source is usually used. Reference numeral 2 denotes a DC power supply circuit, which is composed of a thyristor type or a control rectifier circuit using a rectifier diode, a transistor, etc. whose output can be adjusted by an external command signal, and an output smoothing circuit. 3 is an inverter circuit composed of switching elements, and in the case of the figure, bridge-connected transistors 3a, 3b, 3c, 3d
and a diode 3e connected in antiparallel to each transistor.
, 3f, 3g, and 3h. 4 is a load, which constitutes a series resonant circuit in which a capacitive component 4C and an inductive component 4L are connected in series. Reference numeral 11 denotes an output frequency control circuit, which determines the operating frequency of the inverter 3.

This output frequency control circuit 11 includes a current phase detector 111,
It is composed of a voltage phase detector 112, a phase comparator 113, a phase difference setter 114, a comparator 115, an error amplifier 116, a voltage controlled oscillator 117, and a lock detector 118.

These phase detectors, phase comparators, voltage-controlled oscillators, etc. can be easily manufactured by combining known four-way elements for PLL control circuit configuration, and can be easily manufactured by applying ready-made PLL integrated circuits. It is also possible to convert

21 is an output current control circuit, and an output current setting device 211
, the output l of the lock detector 118 of the output frequency control section 11
Analog switch 212, comparator 213, 2
17, error amplifier 214°218, output current detection circuit 1
A rectifier circuit 215 that rectifies the output of #4 to obtain a DC voltage, an initial voltage setting circuit 216, and error amplifiers #214 and 218.
an output clamp diode 219 for selectively outputting the larger of the output signals;
220. Further, 12 is a first voltage detection circuit that detects the output voltage of the DC power supply circuit 2 and outputs a signal vf to the comparator 217 of the output current control circuit 21;
14 is a second voltage detection circuit that detects the output voltage of the inverter circuit 3 and supplies it to the voltage phase detector 112 of the output frequency control circuit 11; 14 is a current phase detector 111 of the output frequency control circuit 11 that detects the load current; and an output current detection circuit that supplies the rectifier circuit 215 of the output current control circuit 21. 15 is a DC power supply control circuit that receives the output of the output current control circuit 21 and controls the output of the DC power supply circuit 2; when the DC power supply circuit 2 uses a thyristor to perform secant rectification of the AC power supply, the firing phase of the thyristor; This is a phase control circuit for determining the phase difference, and when using a transistor, the base drive circuit becomes the main part. Reference numeral 16 denotes a drive circuit for the inverter circuit 3, which outputs an inverter drive signal for alternately conducting the transistors 3a, 3b or 3c, 3d constituting the inverter circuit 3 at a cycle according to the output of the output frequency control circuit 11. .

In the device shown in FIG. 1, the inverter circuit 3 is inactive until a startup command signal is supplied to the drive circuit 16 from the startup circuit (not shown), and the second voltage detection circuit 1
3 and output current detection circuit 14 do not generate any output, output frequency ms circuit 11 is in an uncontrolled state, and lock detector 118 does not generate lock signal l. Therefore, the analog switch 212 of the output current control circuit 21 remains open, and the output If of the rectifier circuit 215 that rectifies the output of the output current detection circuit 14 is also zero, so the error amplifier 2
14 also produces no output. On the other hand, the output voltage VOC of the DC power supply circuit 2 is detected by the first voltage detection circuit 12 and becomes a signal f.
7, it is compared with the output Vr of the initial voltage setter 216 and the difference signal ΔV=Vr-V (is obtained, which is appropriately amplified by the error amplifier 218 and becomes the signal a!).The DC power supply control circuit 15
supplied to As a result, the DC Wl source circuit 2 generates a voltage FEvl)c corresponding to the set value Vr of the initial voltage setting circuit 216.
will be output. Here, the initial voltage setting circuit 216
The set value vr is set to a relatively low voltage.

Next, when a start command signal is supplied to the drive circuit 16, the drive circuit 16 starts supplying drive signals to the transistors 3a to 3d of the inverter circuit 3 by the output of the voltage controlled oscillator 117 which is free-running in an uncontrolled state. . As a result, the inverter circuit 3 starts operating and generates an output voltage vo, and the load 4
Start supplying current 1o to . At this time of startup, the output frequency control circuit 11 starts from a non-controlled state, so the output frequency of the inverter circuit 3 is likely to be a frequency that deviates from the resonant frequency of the load 4. For this reason, the lock detector 118 does not generate the lock signal l, and the analog switch 212 remains open, resulting in a low voltage corresponding to the set value Vr of the initial voltage setter 216, as in the case of starting #l. The DC power supply circuit 2 is controlled as follows. In this state, the second voltage detection circuit 13 and the output current detection circuit 14
Each output of the voltage phase detector 1 of the output frequency control circuit 11
12 and a current phase detector 111, and the output P1, h of the rain detector is converted by a phase comparator 113 into a voltage s1 corresponding to the phase difference. The output S1 of this phase comparator 113 is the output Sr of the phase difference setter 114 and the comparator 11.
5, and the difference signal 5=Sr-Ss is appropriately amplified by an error amplifier 16 to become a signal Ss. Voltage controlled oscillation! 117 oscillates a signal having a frequency corresponding to this signal S3, and the drive circuit 16 supplies the inverter circuit 3 with a rectangular wave drive signal having a frequency corresponding to the frequency of the output signal of this voltage controlled oscillator. In this output frequency control circuit 11, the output signal P! of the current phase detector 111! is the output signal P! of the voltage phase detector 112. The output polarity of the phase comparator 113 is determined so that the output S1 of the phase comparator 113 becomes negative when the current phase is ahead of the current phase, and positive when the current phase is in the opposite direction (when the current phase is delayed). 117 is set so that when the input signal S3 is positive, the oscillation frequency is high (and when S3 is negative, the oscillation frequency is low).When the current phase is leading, that is, as shown in FIG. In a case like at, the operating frequency fO of the inverter is lower than the resonant frequency fL of the load (fo<fL), so 5r-3t>O, the signal Ss becomes positive, and the output frequency of the voltage controlled oscillator 117 becomes different. The output frequency of the inverter circuit 3 increases by an amount corresponding to No. 43 S3.
When o=f(, the signal S1 becomes zero, but the comparator 115
Since the output Δ5=Sr-St=Sr>0, 83 is still positive, and the operating frequency of the inverter circuit 3 continues to rise. Next, when fo > fL, Fig. 5 (cl
Current phase as shown in ? , gradually becomes the voltage phase P! Although the delay becomes longer, the operating frequency continues to rise because Ss>0 until the difference SR reaches the set value Sr of the phase difference setter 114.

The operating frequency fo of the inverter circuit 3 increases and the phase difference S
When l becomes approximately equal to the set value Sr, the output S3 of the error amplifier 116 becomes approximately zero, and the voltage controlled oscillation W 117 stops at the oscillation frequency at that time. Furthermore, if the operating frequency fO of the inverter circuit 3 becomes excessive and the phase difference becomes large, S
>Sr, the output SS of the error term I booster 116 becomes negative, and in response to this negative signal input, the voltage controlled oscillator 117
The output frequency decreases and is controlled so that S+=SrK.

In this way, the output frequency of the inverter circuit 3 changes to the load 4.
Since the period until the current phase of the load 4 becomes slightly higher than the resonant frequency of and reaches a state where the current phase of the load 4 lags the voltage phase by the set Sr is Sr+431, the frequency lock detection circuit 118 outputs the lock signal l. do not. For this reason, the analog switch 212 of the output current control circuit 21 remains open, so the DC power supply circuit 2 is maintained at the low voltage set by the initial voltage setter 216 as before startup. Therefore, even if the output frequency of the inverter circuit 3 deviates from the target frequency that minimizes loss, which has a constant relationship with the resonant frequency of the load, the output voltage of the DC power supply 2 supplied to the inverter circuit is low. The switching elements will not be overloaded.

When the operating frequency fo of the inverter circuit 3 reaches the target value and the output Sl of the phase comparator 113 becomes approximately equal to the set value Sr of the phase difference setter 114, the frequency lock detection circuit 118
is a lock signal! Output. This lock signal l closes the analog switch 212, and output current setting a211
The set value 1r is transmitted to the comparator 213. In the comparator 213, the feedback signal If obtained by rectifying the output of the output current detection circuit 14 in the rectifier circuit 215 is compared with the output current setting value Ir, and the difference signal al=Ir-I(
is outputted via the error amplifier 214. This output signal a
1 is the output a! of the error amplifier 218 for initial voltage control. Therefore, the current error signal at is supplied to the DC power supply control circuit 15, and the DC power supply circuit 2 supplies the inverter circuit 3 with a high output voltage that allows a predetermined output current to be obtained.

Note that, after the output frequency of the inverter circuit 3 reaches the target value in this manner, if the resonant frequency of the load 4 changes suddenly and deviates from the optimum frequency.

The frequency lock detection circuit 118 thereby stops outputting the lock signal l, and the analog switch 212 is opened, so feedback control of the output current to the DC power supply circuit 2 is interrupted as before and immediately after startup, and the initial voltage setting is The control method is switched to maintain the low output voltage set by the device 216. When the output frequency control circuit 11 responds and the output frequency of the voltage controlled oscillator 117 reaches the optimum frequency corresponding to the resonant frequency of the load, the lock signal l is output again, and the DC power supply circuit 2 changes the output current setting from the low voltage output. The control method is switched to match the set value of the device 211.

FIG. 2 shows the power loss generated in the transistors of the inverter circuit in the embodiment of FIG. 1, with the operating frequency fO plotted on the horizontal axis, similar to FIG. 6. In the figure, the solid line shows the change in power loss in the device of the present invention, and the broken line shows the change in power loss in the conventional device of FIG. Further, in the figure, the voltage controlled oscillator 117 is shown as oscillating at a free-running oscillation frequency fl slightly lower than the resonant frequency fL of the load 4 when it is not controlled, that is, when the input signal is zero. Voltage controlled oscillation n 117
is uncontrolled, the frequency f3 is higher than the resonant frequency fL.
When it oscillates, it will look like the dashed-dotted line shown on the right side of the figure.

As shown in the figure, the power burden of the transistors constituting the inverter circuit is low, corresponding to the low voltage set by the initial voltage setter 216, until the target optimum frequency f2 is reached. The value can be made extremely smaller than that in the device.

In FIG. 1, a series resonant load 4 has been described, but the present invention can be implemented with a similar device even if the load 4 is a parallel resonant load.

In the case of a parallel resonant type load, as described above, the current flowing through the transistors forming the inverter circuit rapidly increases before and after the resonant frequency.

Therefore, the operating frequency of the inverter circuit may be set to a frequency equal to the resonant frequency of the load. Therefore, by setting the output Sr of the phase difference setting device 114 to zero in the embodiment shown in FIG. 1, the embodiment can be applied to a parallel resonant load. FIG. 3 shows transistors 3a to 3 of the inverter circuit 3 in this case.
The change in the current IT flowing through d is expressed as the operating frequency f of the inverter.
It is a diagram showing [7] for o-ki #≠don.

In the figure, the solid line shows the change in the current Ip flowing through the transistor in the device of the present invention, and the broken line shows the change in the current flow T in the conventional device. As can be seen from the figure, in the present invention, by setting the set value Vr of the initial voltage setter 216 to a low value, the current flowing through the transistor can be suppressed to a sufficiently low and safe value.

Furthermore, when it is necessary to obtain a constant voltage output as the output of the inverter, the output voltage is fed back instead of the output current, and the output voltage of the DC power supply circuit 2 is adjusted so that the difference signal decreases compared to the base 1m. The output control unit 21 and the DC power supply control circuit 1
5 may be configured.

Note that the DC/AC conversion circuit used in the present invention is not limited to one using the full brittle type inverter shown in FIG. It is possible to apply various types of inverters such as various type or current type inverters.

〔Effect of the invention〕

Since the device of the present invention operates as described above, the switching elements constituting the inverter are not overloaded, and the capacity of the switching elements is reduced to the output g of the inverter circuit.
It is sufficient to determine only by N. Therefore, not only can the device be made smaller, lighter and cheaper, but also a highly efficient device with less internal loss can be obtained. Of course, since the internal loss is small, the amount of heat generated is also reduced, and the devices for cooling these elements can be made smaller.

Furthermore, in the present invention, means for overload prevention,
The output current is adjusted by adjusting the output of the DC power supply, and the frequency control to obtain a frequency corresponding to the resonant frequency of the load is performed by adjusting the operating frequency of the inverter circuit. , the voltage adjustment and frequency adjustment are separate systems, and the only thing they do is send and receive signals that switch the output adjustment system between low output and steady output, which are limited by the presence or absence of a frequency lock signal, so both controls This system provides extremely stable operation without causing interference in the system.

[Brief explanation of the drawing]

1 is a connection diagram showing an embodiment of the present invention, FIG. 2 is a diagram for explaining the state of power loss occurring in the transistor in the device of FIG. 1, and FIG. 3 is a diagram for explaining Fourth
The figure shows a connection diagram showing an example of a conventional device. Figure 5 fa) or cl is a series resonant circuit that configures an inverter when the frequency of the power supply changes from large to small around the resonant frequency of the load. FIG. 6 is a diagram for explaining changes in the current flowing through the switching elements, and is a diagram showing power loss occurring in the switching elements with respect to changes in the operating frequency of the inverter. 2... DC power supply circuit, 3... Inverter circuit, 4...
... Resonant load, 11... Output frequency control circuit, 12.
...First voltage detection circuit, 13...Second output voltage detection circuit, 14...Output current detection circuit, 15...DC power supply control circuit, 16...Drive circuit, 21... Output current control circuit, 3a, 3b, 3c, 3d = Transistor, 3e, 3f, 3g, 3h... Diode, 111.
...Current phase detector, 112...Voltage phase detector, 1
13... Phase comparator, 114... Phase difference setting device, 1
17... Voltage controlled oscillator, 118... Frequency lock detector, 211... Output current detector, 212... Analog switch, 216... Initial voltage setting device agent Patent attorney Hiroshi Nakai No. 3 Figure f, fLf. Frequency (Hz) Figure 6 Scrap wave frequency (Hz) Procedural amendment (method) % formula % 2. Name of the invention High frequency power supply device 3. Relationship with the amended person case Patent applicant Yodoyo-ku, Osaka City 2-1-11 Tanyo (02B) Daihen Co., Ltd. 4, agent address 2-1-1 Tanyo, Yodoyo-ku, Osaka 532
No. 1 No. 5, Date of amendment order September 27, 1988 (
(All sending dates) 6. Drawings subject to correction

Claims (1)

[Claims] 1. A high-frequency power supply device that supplies power at an optimal operating frequency to a load having a resonant frequency, comprising: a DC power supply whose output voltage is adjustable; and an output of the DC power supply that is controlled by switching. A DC/AC conversion circuit converts to alternating current without adjustment, and the output frequency of the DC/AC conversion circuit is monitored and maintained at a target frequency corresponding to the resonant frequency of the load, and it is detected that the target frequency has been reached. The output frequency control circuit of the DC/AC conversion circuit outputs a frequency lock signal by using the output frequency control circuit, and the output voltage of the DC power supply is limited to a low voltage until the frequency lock signal from the output frequency control circuit is input. A high frequency power supply device comprising: an output control circuit that releases the restriction based on a lock signal and adjusts the output of the DC power supply so that the output of the DC/AC conversion circuit matches a predetermined reference value. 2. The output frequency control circuit receives an output voltage phase detection circuit, an output current phase detection circuit, an output of the output voltage phase detection circuit, and an output of the output current phase detection circuit, and calculates the difference between the two output signals. a phase difference calculation circuit for calculation, a phase difference setting circuit, a comparator for obtaining a difference signal between the output of the phase difference setting circuit and the output of the phase difference calculation circuit, and a signal having a frequency according to the output of the comparator. a voltage-controlled oscillator that generates a voltage-controlled oscillator; a drive circuit that drives the DC/AC conversion circuit according to the output of the voltage-controlled oscillator; and an output signal Sr of the phase difference setting circuit and an output S_1 of the phase difference calculation circuit. 2. The high frequency power supply device according to claim 1, comprising a lock detection circuit which detects that the input signal (Sr-S_1) has reached a reference value and outputs a frequency lock signal l.