JPH0131729B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a charge-transfer device.
This invention relates to automatic equalizers using semiconductor delay lines such as devices (hereinafter simply referred to as CTD). In more detail, in order to restore the signal waveform distorted by intersymbol interference in the transmission path to the original waveform, we will introduce a semiconductor delay line with a tap for non-destructive detection of signal delay, each delayed signal and the corresponding weighting coefficient. an acyclic filter composed of a plurality of multipliers that multiply each other, an adder that multiplies the output signals of the multipliers, a circuit that calculates a weighting coefficient correction signal necessary for modifying the weighting coefficient, and the weighting coefficient. The present invention relates to an automatic equalizer composed of a weighting coefficient circuit that corrects and stores .

Conventional serial in/parallel out (hereafter
SI/PO) type automatic equalizer using a CTD semiconductor delay line (hereinafter simply referred to as a conventional automatic equalizer)
The configuration will be explained with reference to FIG. 1 is SI/
PO type CTD semiconductor delay line, 2 is the input part of the CTD 1 that converts input voltage into signal charge, 3-k (k=
1, 2,...N) is a transfer stage that delays the signal charge by a fixed period T, and 4-k (k=1, 2,...N) non-destructively detects the signal charge and transfers the voltage signal xk(k =
1, 2,...N) tap circuit, 5-k
(k=1, 2, . . . N) are tap terminals. 6-
k (k=1, 2,...N) is the xk and the weighting coefficient wk(k
= 1, 2,...N) multiplier, 7
are the output signals from the multiplier 6-k, i.e. xk and wk
The output y of the adder 7 becomes the output signal of the conventional automatic equalizer. It is well known that the above-mentioned components constitute an acyclic filter. 8 is an output terminal of the automatic equalizer, 9 is a subtracter that obtains the difference between a known signal a given from the outside and the output signal y, that is, an error signal e, and 10 is a multiplier for multiplying the error signal e by an attenuation coefficient u. It is a multiplier that performs 11-k (k=1, 2,...N)
is a multiplier that multiplies xk and ue by each other, 12-
k (k=1, 2, . . . N) is a weighting circuit that stores the wk and also calculates and holds a new weighting coefficient to be used in the next cycle. Next, the operation of the conventional automatic equalizer will be briefly explained using FIG. Essentially, pulsed digital signals are subject to intersymbol interference on the transmission path during propagation, resulting in large distortions when they reach the receiving end. An automatic equalizer is a filter that removes the distortion and restores the original signal. After the distorted signal is applied to the input section 2, it is sampled at a constant period T and simultaneously converted into an electric charge. The charge is transferred one stage at a time in the transfer stage 3-k at each constant period T,
It is non-destructively detected by the tap circuit 4-k, converted again into a voltage signal xk, and obtained from the tap terminal 5-k. In the multiplier 6-k, the signal xk is multiplied by the output of the weighting circuit 12-k, that is, the weighting coefficient wk,
The multiplication results xk·wk (k=1, 2, . . . N) are added by the adder 7, and taken out from the terminal 8 as an output y. Whether the output signal y has been completely restored to the original signal is determined by comparing it with the signal a. The output signal of the subtracter 9, that is, the error signal e
If is zero, y has been restored to the original signal.
On the other hand, if e is not zero, e is multiplied by the attenuation coefficient u, and then the output xk of each tap terminal 5-k is multiplied by the multiplier 11-k. Next, the weight circuit 12
−k from the weighting coefficient wk, the multiplication result u・e・
By subtracting xk, a new weighting coefficient after the next fixed period T is calculated and held.

By repeating the signal processing described above, the difference signal e becomes zero or extremely small, and the weighting coefficient wk
When y is corrected and becomes constant or almost constant, the output signal y has been completely or almost completely restored to the original pulse-like signal.

Next, the SI/
The specific configuration of the PO type CTD semiconductor delay line will be explained. A typical conventional SI/PO type CTD is a bucket brigade device with a tap.
Brigade Device (hereinafter simply referred to as BBD) and Charge-Coupled Device (BBD) with a tap.
Device (hereinafter referred to as CCD for simplicity).
FIG. 2 shows one transfer stage, one tap circuit, and tap terminal of the BBD with taps. In the figure, 3-k, 4-k, and 5-k are the k-th transfer stage, the k-th tap circuit, and the k-th transfer stage, respectively.
The tap terminals correspond to the same numbered components shown in FIG. 1, respectively. 101 and 102 are transistors and capacitors, respectively, and common wiring 10
Connected to 3. 104 and 105 are connected to a common wiring 106 through transistors and capacitances, respectively. Two voltage pulses, which are normally turned on and off periodically and whose phases are 180 degrees different from each other, are applied to the wirings 103 and 106, respectively. Now, when the applied pulses to the wirings 103 and 106 are at high level and low level, respectively, the capacitance is 1
Assume that signal charges are accumulated in 02. Next, when the pulse applied to the wiring 103 returns to a low level and at the same time the pulse applied to the wiring 106 becomes high, the transistor 104 becomes conductive.
The signal charges accumulated in the capacitor 102 are transferred to the capacitor 105. Therefore, a potential change occurs at the connection point 107 between the transistor 104 and the capacitance. 108 is a transistor for detecting a potential change at the coupling point 107, and 109 is a transistor used as a load of the transistor 108. Usually, MOS transistors are used for 108 and 109. Terminal 110 is connected to a DC power source.

The major drawback of the BBD with taps shown in Fig. 2 is the transfer efficiency [signal charge is transferred from one storage section (capacitance 102 in Fig. 2) to the next storage section (capacitance 105 in Fig. 2)]. When transferred, the CTD is the ratio of the original charge to the transferred charge.
is an important index indicating the performance of
That is, it is bad and the transfer noise is very large. This is due to the fact that the charge transfer mode of the BBD is an incomplete transfer mode. For the above reasons, the tapped BBD is not suitable for application to systems that require high-precision signal processing, such as automatic equalizers.

Other configurations of conventional CTDs with taps include:
Figure 3 shows a CCD with taps. Here, as an example of a signal charge detection method, a method using floating electrodes will be described. Similar to Figure 2, 3-k, 4-k,
5-k are the constituent elements 3- shown in FIG.
k, 4-k, and 5-k, respectively. 120
are semiconductor substrates, 121, 122, 123, 124
A first phase electrode, a second phase electrode, a third phase electrode, which are regularly arranged through an insulating film (not shown) formed on the semiconductor substrate 120,
This is a floating electrode (fourth phase electrode). 125 is a transistor for periodically presetting the floating electrode 124; Wirings 126, 127, and 129 supply clock pulses that are periodically turned on and off necessary for transferring signal charges, and wirings 128 and 130 supply DC voltage. 4-k
Elements 108, 109, and 110 constituting are exactly the same elements as the elements with the same numbers in FIG. Next, the method for detecting the charge of the CCD with taps will be outlined.
Now, the pulse applied to the wiring 127 is at a high level,
It is assumed that a potential well is formed in the semiconductor substrate 120 directly below the electrode 122, and signal charges are accumulated in the potential well. At this time, when the pulse applied to the wiring 129 temporarily becomes a high level, the transistor 125 becomes conductive, so the floating electrode 124 is set to the DC potential level of the wiring 130, and the pulse applied to the wiring 129 returns to a low level. However, the potential of the floating electrode remains at the level of the DC potential of the wiring 130. In other words, it is in a floating state, and a potential well is formed in the semiconductor substrate 120 below the floating electrode 124. Next, when the pulse of the wiring 127 returns to a low level, the signal charge immediately below the electrode 122 passes through the charge path formed in the semiconductor substrate 120 immediately below the electrode 123, and the potential immediately below the floating electrode 124 decreases. It is transferred to the well where it is accumulated. Therefore, the potential of the floating electrode changes from the DC level (DC level of the wiring 130) when it was previously reset by a value proportional to the amount of the signal charge. The change in potential is detected by the tap circuit 4-k and led to the outside from the tap terminal 5-k.

The biggest drawback of the CCD with floating electrode taps outlined above is that it cannot be driven at high speed. Therefore, it has the disadvantage that it is completely impossible to apply it to systems requiring high-band signal processing. In order to limit the distortion occurring in the output signal of the tapped CCD to a low level, a surface channel must be used as a charge transfer channel. However, in surface channel charge transfer, at the end of the transfer process when the transfer of charge from one potential well to the next potential well is almost complete, charge movement depends only on diffusion, so driving at a high frequency The amount of charge left behind becomes extremely high. That is, there was a serious drawback in that the transfer efficiency described above was extremely degraded. On the other hand, in high-speed driving, it is necessary to use a buried channel in order to prevent deterioration of transfer efficiency. However, in this case, there was a drawback that the linearity of the tap output was severely impaired.

In addition, conventional automatic equalizers that use conventional tapped BBDs as SI/PO type CTD semiconductor delay lines have high precision due to drawbacks caused by tapped BBDs, namely extremely low transfer efficiency and large transfer noise. automatic equalization could not be performed. Furthermore, in conventional automatic equalizers that use a CCD with surface channel type taps as a delay line, the transfer efficiency deteriorates extremely when the automatic equalizer is driven at high speed, so it cannot be applied to high-band automatic equalization. Ta. On the other hand, an automatic equalizer using a CCD with an embedded channel type tap causes large distortion in the tap output.
High-quality automatic equalization was not possible.

An object of the present invention is to provide an automatic equalizer that eliminates the drawbacks of the conventional automatic equalizers.

According to the present invention, a tap circuit includes an input section that converts a voltage signal into a signal charge, an embedded channel type transfer section that transfers the signal charge, and a floating diffusion layer that converts the transferred signal charge into a voltage signal. A total of N charge transfer devices including a first charge transfer device, a second charge transfer device, an Nth (N is an integer) charge transfer device configured, and the transfer of the first charge transfer device is provided. The transfer section includes one transfer stage that delays the signal charge by a certain period of time, the transfer section of the second charge transfer element includes two transfer stages, and the transfer section of the N-th charge transfer element delays the signal charge by a certain period of time. N transfer stages are provided, each of the input parts of each of the charge transfer elements is connected by a common wiring, and each of the charge transfer elements is driven at the same timing, and a semiconductor delay line with a tap is provided for each of the tap circuits. , and N first multipliers that mutually multiply the output signals of the tap circuits and the weighting coefficients, an adder that adds the multiplier output signals, a comparator that quantizes the addition results, and a comparator that quantizes the addition results. a subtracter for obtaining the difference between the results, a multiplier for multiplying the subtraction result and the attenuation coefficient, and a second multiplier provided for each tap circuit and for multiplying the output signal of the tap circuit and the output of the multiplier. and a weighting coefficient circuit provided for each tap circuit, which integrates the output signal of the second multiplier and uses the result as the weighting coefficient. An equalizer is obtained.

According to the present invention, a compact automatic equalizer with high transfer efficiency and high linearity that can be integrated is realized,
In addition, high-band automatic equalization can be performed.

The present invention will be explained below with reference to the drawings.

FIG. 4 shows an example of the configuration of an automatic equalizer according to the present invention. In the figure, reference numeral 20 denotes a semiconductor delay line with taps, which is composed of N (N is an integer) independent CTDs. 21-k (k=1, 2,...N) is the input part of each CTD that converts the voltage signal into signal charge, 2
2-k (k=1, 2,...N) is a transfer unit that transfers the signal charges, and 23-k (k=1, 2,...N) detects the signal charges and generates a voltage signal xk (k= 1, 2,...
24-k (k=
1, 2,...N) are tap terminals. Reference numeral 25 denotes a transfer stage that delays the signal charge by a certain period T, and the transfer section 22-k is composed of k transfer stages 25. Therefore, the k-th CTD composed of 21-k, 22-k, and 23-k delays the input signal by k times the constant period T, and sends the output signal xk from the tap terminal 24-k to the tap terminal 24-k. Semiconductor delay line 2 with
Lead to the outside of 0. 26 and 27 are the input terminal and output terminal of the automatic equalizer of the present invention, respectively. 28-k (k=1, 2,...N) is a first multiplier that multiplies the xk and the weighting coefficient wk (k=1, 2,...N), and 29 is the output of the multiplier 28-k. The output signal y of the adder 29 is an adder that adds together the multiplication results of the signals, ie, xk and wk, and the output signal y of the adder 29 becomes the output signal of the automatic equalizer of the present invention. 130 is a comparator that compares the output signal y with a reference potential supplied from the outside and provides an output a; 131 is a subtracter that obtains the difference between y and a, that is, an error signal e; 132 is a subtracter that obtains the error signal e; This is a multiplier that multiplies the attenuation coefficient u. In addition, 13
The circuit composed of 0, 131, and 132 is called a detection circuit here. 133-k (k=1, 2,...N)
is a second multiplier that multiplies the output signal of the second multiplier 32 by the xk. 134-k (k=1,
2,...N) is a weighting coefficient circuit that stores the wk, calculates a new weighting coefficient to be used in the next cycle after the certain period T, and stores this, and usually an integrator or the like is used.

Next, the specific structure of the tapped semiconductor delay line, which is the main part of the automatic equalizer, will be explained. FIG. 5 shows the specific structure of each CTD shown in FIG. 3, and is a cross-sectional view taken parallel to the direction in which signal charges travel. Here, as an example, a buried channel CCD with two transfer stages and two-phase drive will be described. 30 is a semiconductor substrate, 31 is a buried channel layer formed by diffusing an impurity of a conductivity type opposite to that of the semiconductor substrate 30 into the semiconductor substrate, and 32 is an impurity layer of the same conductivity type as the semiconductor substrate 30 and with a high concentration. It is a barrier area. 33 is a diffusion layer for injecting signal charges, and 34 is a diffusion layer for collecting signal charges, both of which are impurity diffusion layers that have the same conductivity type as the buried layer 31 and have a higher concentration than the buried layer 31. . Both 35 and 36 are input electrodes, and when a charge injection method based on a charge balance method is used, a DC potential is applied to one of the electrodes, and a signal voltage superimposed with a DC potential is applied to the other electrode. At this time, a pulse voltage that periodically turns on and off is applied to the diffusion layer 33. 37
A, 37B are first phase transfer electrodes, 38A, 38B
is a second phase transfer electrode, and the electrodes 37A, 3
7B, 38A, and 38B form a first transfer stage.
Similarly, 39A and 39B are first phase transfer electrodes, 40
A and 40B are second phase transfer electrodes, and these four electrodes form a second transfer stage. Electrodes 37A, 37
B, 39A, 39B are connected to a common wiring 41, and electrodes 38A, 38B, 40A, 40B are connected to a common wiring 42.
are connected to each other by Periodic pulse voltages having phases different from each other by 180 degrees are supplied to the wirings 41 and 42, and charge transfer in the well-known two-phase drive mode is performed. 43 is an output electrode to which a DC potential is supplied. Reference numeral 44 denotes a transistor for periodically presetting the diffusion layer 34, and terminals 47 and 48 are connected to a pulse power source and a DC power source, respectively, which are turned on and off periodically. Reference numeral 45 denotes a transistor for detecting potential changes in the diffusion layer 34, and a DC voltage is supplied from a terminal 49. A transistor 46 is used as a load for the transistor 45, and forms a buffer circuit together with the transistor 45. Note that the electrode 3
5, 36, 37A, 37B, 38A, 38B, 3
9A, 39B, 40A, 40B, and 43 are regularly arranged on an insulating film (not shown) formed on the semiconductor substrate 30. The input section formed by 33, 35, and 36 is the input section 21-k in FIG.
7A, 37B, 38A, 38B or 39A,
The transfer stages 39B, 40A, and 40B are connected to the transfer stage 25 in FIG. 3, and the tap circuits 34, 44, 45, 46, and 47 are connected to the tap circuit 23-k in FIG.
4-k correspond to the tap terminal 24-k in FIG. 3, respectively.

The pulse applied to the wiring 42 is now at a high level,
It is assumed that a potential well is formed in the buried channel layer 31 directly under the electrode 40B, and signal charges are accumulated in the potential well. Next, when the pulse applied to the terminal 47 temporarily becomes a high level and then returns to a low level, the transistor 44 becomes conductive only during the period when the pulse is at a high level, and the floating diffusion layer 34 receives the voltage applied to the terminal 48. After being reset to the specified DC voltage level, it is held at that DC voltage level. When the next applied pulse on the wiring 42 returns to a low level, the electrode 40
The signal charge immediately below B is transferred to the floating diffusion layer 34 through a charge path formed in the buried channel layer 31 immediately below the electrode 43, and is accumulated there. Therefore, the floating diffusion layer 34 produces a potential change proportional to the amount of signal charge from the DC voltage level when it is reset by light. The potential change is detected by the buffer circuit, and the output terminal 2
It is led to the outside from 4-k. Note that the electrode 37
Since there is always a potential gradient in the direction of signal charge transfer in the potential wells formed in the buried channel layer directly below B, 38B, 39B, and 40B, charges are transferred from under one electrode to under the next electrode. When it is done,
Even during the final period of the charge transfer described above, charge movement occurs due to drift. Therefore, high-speed charge transfer is performed and at the same time, no charge is left behind, that is, extremely high transfer efficiency is obtained. This is because a conventional surface channel was used in which charge transfer was performed by diffusion at the end of the transfer process.
This is significantly different from the SI/PO type CCD.

Next, the operation of the automatic equalizer of the present invention will be explained using FIG.

A pulsed digital signal becomes a distorted signal due to intersymbol interference in the transmission path. The automatic equalizer of the present invention is a high-speed, high-bandwidth filter that removes distortion from the signal and restores it to the original pulsed digital signal. The distorted signal applied to the input terminal 26 is sampled at a constant period T by the input section 21-k,
At the same time, it is converted into electric charge. Next, the signal charge is injected into the corresponding transfer section 22-k, and the signal charge moves one step at a time through the transfer stage 25 at a constant period T. For each CTD, the signal charge that reaches the tap circuit 23-k is converted into voltage, and the tap terminal 23-k is converted into a voltage.
4-k to the outside of the CTD 20.
The output signal of the tap terminal 24-k is x(nT-kT)
Then, the output signal of the tap terminal 24-1 is x
(nT-T), and the output signal of the tap terminal 24-N can be written as x(nT-NT). Here, n is the input section 21
−k is the sampling number. Furthermore, the fifth
As explained in the figure, since the tapped semiconductor delay line 20 can be driven at high speed, the constant period T
can be made extremely short. Therefore, the automatic equalizer of the present invention can process an extremely high bit rate (1/T) input signal, that is, a high band signal. The output signal x(nT-kT) is multiplied by the weighting coefficient wk in the first multiplier 28-k, and the multiplication result is added in the adder 29 to become an output signal y, which is sent to the output terminal 27. taken out from The comparator 30 compares the output signal y with a reference potential and generates the output signal a. Next, a subtracter 31 subtracts a from y to obtain an error signal e. When the e becomes zero, the intersymbol interference of the distorted input signal is removed, and the y is completely restored to the original pulsed digital signal. At this time,
The output signal of the weighting circuit 34-k, that is, the weighting coefficient
wk remains a constant value. Conversely, if e is not zero, then e, u, and x(nT−kT)
By subtracting and correcting the multiplication result from the weighting coefficient wk, the weighting coefficient to be used in the next cycle is calculated. By repeating the above modification process, e is set to zero and the modification of the weighting coefficients is completed. As a result, the weighting coefficient of each weighting circuit 34-k is held constant, so that the automatic equalizer of the present invention eliminates intersymbol interference of the distorted input signal and completely restores the original signal.

The structure and operation of the automatic equalizer of the present invention have been described above in detail. According to the invention, the embedded channel type
Since the transfer section of the tapped delay line can be constructed using a CCD, high transfer efficiency can be obtained even in high-speed driving. Therefore, a high bandwidth automatic equalizer is realized. Signal charge detection is performed using a tap circuit using a floating diffusion layer with excellent linearity.
High-precision automatic equalization is achieved. The tapped delay lines, multipliers, adders, comparators, and weight circuits are all process compatible semiconductor devices, e.g. MOS
Since the present invention can be constructed from semiconductor elements having the same structure, the system can be integrated into a single chip, and an automatic equalizer that is small in size, has low power consumption, has a high bandwidth, is highly reliable, and is low in price can be provided.

In the explanation of the semiconductor delay line with taps, an embedded channel CCD was used as an example in which the transfer section of one CTD consists of two transfer stages and is driven by two-phase clock pulses. If this is achieved, it is not limited to this, and the one
The structure and driving method of the CTD transfer section may be used.

[Brief explanation of drawings]

Figure 1 shows the configuration of a conventional automatic equalizer using SI/PO type CTD, Figures 2 and 3 respectively
This is an SI/PO type CTD using BBD and CCD.
FIG. 4 shows an example of an embodiment of the automatic equalizer of the present invention, and FIG. 5 is a sectional view of the semiconductor delay line shown in FIG. 4. In Figure 1, 1 is PI/SO type
CTD, 6-k, 10, and 11-k are multipliers, 7 is an adder, 9 is a subtracter, and 12-k is a weighting circuit. 3-k, 4 in Figures 1, 2, and 3
-k and 5-k are a transfer stage, a tap circuit, and a tap terminal, respectively. In Figures 2 and 3, 10
1,104,108,109,125 are transistors, 102,105 are capacitances, 121,12
2, 123 is a transfer electrode, and 124 is a floating electrode. 4 and 5, 20 is a semiconductor delay line with a tap, 21-k is an input section, 22-k is a transfer section, 23-k is a tap circuit, 24-k is a tap terminal, and 25 is one transfer stage. , 26 is an input terminal, 27 is an output terminal, 28-k is a first multiplier, 29 is an adder, 130 is a comparator, 131 is a subtracter, 132 is a multiplier, 135 is a detector, 133-k is a a second multiplier, 134-k a weight circuit, 30 a semiconductor substrate, 31 a buried channel layer, 32 a barrier,
33, 34 are high concentration impurity diffusion layers, 35, 36,
37A, 37B, 38A, 38B, 39A, 39
B, 40A, 40B, 43 are electrodes, 44, 45,
46 is a transistor.

Claims (1)

[Claims] 1. A tap circuit consisting of an input section that converts a voltage signal into a signal charge, an embedded channel type transfer section that transfers the signal charge, and a floating diffusion layer that converts the transferred signal charge into a voltage signal. 1st charge transfer element, 2nd charge transfer element, ... Nth charge transfer element
(N is an integer) charge transfer elements in total, and the transfer section of the first charge transfer element has one transfer stage that delays signal charges by a certain period of time.
The transfer unit of the second charge transfer element includes two transfer stages, the transfer unit of the N-th charge transfer element includes N transfer stages, and the transfer unit of the N-th charge transfer element includes N transfer stages, Each input section is connected by a common wiring, and each charge transfer element is driven at the same timing, and a semiconductor delay line with a tap is provided for each tap circuit, and the output signal of the tap circuit and the weighting coefficient are multiplied by each other. N first multipliers, an adder that adds the multiplier output signals, a comparator that quantizes the addition result, a subtractor that obtains the difference between the addition result and the quantization result, and a subtraction result and attenuation. a multiplier that multiplies coefficients with each other; N second multipliers that are provided for each tap circuit and that multiply the output signal of the tap circuit and the output of the multiplier; and a weighting coefficient circuit that integrates the output signal of the second multiplier and uses the result as the weighting coefficient.