JPH01317019A - Trapezoidal wave generating circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of the inclination of a trapezoidal wave by generating the trapezoidal wave by a constant current without power source fluctuation and temperature fluctuation. CONSTITUTION:When a reference signal changes from an L to an H level, an output of a NAND circuit 11 changes from an J to an L, a transistor(TR) M6 is turned on, a TR M8 is turned off and a capacitor C1 is charged by a current I1. When the voltage of the capacitor C1 exceeds a voltage VH set by resistors R3 and (R4+R5), the output of a voltage comparator 1 charges from an H to an L level, a clock is inputted to a D-FF 7, the inverse of Q output of the D-FF goes to an L, the NAND circuit 11 is restored to the H level, the charging is finished and the level of the capacitor C1 is held to the VH. When the reference signal changes from H to L, the capacitor C1 is held as the voltage VL as it is. Thus, the potential of the capacitor C1 is changed in a trapezoidal waveform by a constant current with no power source fluctuation and temperature fluctuation charateristic, and a stable output is obtained via a voltage follower circuit 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a trapezoidal wave generating circuit used in a semiconductor integrated circuit, and more particularly to a trapezoidal wave generating circuit used during phase comparison in a PLL circuit.

[Conventional technology]

FIG. 4 shows a trapezoidal wave generating circuit 22 conventionally used in this type of PLL circuit. Invert the digital signal 18
is input to the inverter 19, and is output from the inverter 19, and is connected to an integrating circuit composed of a resistor R7 and a capacitor C3, and a diode Di.
, D2, a trapezoidal wave is generated.

[Problem to be solved by the invention]

The conventional trapezoidal wave generation circuit 22 described above obtains a trapezoidal wave by integrating the digital signal and slicing the upper and lower parts of the waveform using a diode limiter, so the slope of the trapezoidal wave is not a straight line but an exponential function. Since it draws a curve, when the power supply voltage changes, the slope of the sliced trapezoidal wave will change due to the influence of the amplitude of the input digital signal. When using a trapezoidal wave in a PLL circuit, the sample pulse is generated using the reference signal, and the trapezoidal wave is generated using the comparison signal.
If the slope of the trapezoidal wave is not a straight line, an error will occur in the PLL error voltage and it will take time to stabilize. Furthermore, if the slope changes due to power supply voltage or temperature fluctuations, the gain within the PLL loop changes, resulting in a large fluctuation in the steady-state phase error.

[Means to solve the problem]

The present invention provides a constant current circuit that generates a constant current using a reference voltage of a Zener diode, a capacitor whose one terminal is grounded, a current mirror circuit that uses the constant current of the constant current circuit as an input current, and a current mirror circuit. a constant current discharging circuit connected to a constant current circuit via a constant current circuit and conducting in order to discharge the capacitor via the other terminal of the capacitor according to a control signal; and a constant current discharge circuit for charging the capacitor with a constant current according to a control signal. The first one is made by a constant current charging circuit that conducts to a charging voltage detection circuit that sends a control signal to a second threshold charging circuit to stop charging, and further sends a control signal to a constant current discharge circuit to stop discharging when the discharge voltage of the capacitor becomes equal to or less than a second threshold; A Poldisi follower circuit that inputs and outputs the charging voltage of the capacitor, comprising a control circuit that starts operating a constant current charging circuit when a signal rises, and a control circuit that starts operating a constant current discharging circuit when a reference signal falls. have.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

Zener diode ZD is connected to the power supply voltage via resistor R1, and one terminal is grounded.

The output voltage v2 of the Zener diode ZD is applied to the base of the transistor Q1. The emitter of transistor Q1 is connected to ground via resistor R2. The drain and gate of the MoS transistor M1 are connected to the collector of the transistor Q1. Transistor Ml,
M2. M3. M4 and M5 constitute a current mirror circuit. A transistor M6 is connected to the drain of the transistor M3, and a transistor M7 is connected to the drain of the transistor M5. Transistor MS.

One terminal of M7 is connected and connected to ground via capacitor c1. Further, the drain of the transistor M3 is connected to the ground via the transistor M8, and the transistor M5 is connected to the power supply voltage via the transistor M9. The capacitor C1 is input to the opposite phase terminals of the voltage comparators 1 and 2. Further, voltages determined by resistors R3, R4, and R5 are input to voltage comparators 1 and 2. The output of voltage comparator 1 is connected to D-FF via inverter 3.
It is input to the clock terminal of 7. Further, the output of the voltage comparator 2 is inputted to the terminal of the D-FF 8 via inverters 5 and 6. A reference signal that creates a trapezoidal wave is input to the D terminal and clear terminal (active L) of D-F'F7, and an inverted version of the reference signal is input to the D terminal and clear terminal of D-FF8. There is. The output of D-F'F 7 and the reference signal ' are input to the NAND circuit 11 . NA
The output of the ND circuit 11 is input to the gate of the transistor M6, and the output of the NAND circuit 11, which is inverted by the inverter 14, is input to the gate of the transistor M8. On the other hand, the Q output of D-FF8 and the reference signal are connected to NOR circuit 1.
2 is input. The output of the NOR circuit 12 is input to the gate of the transistor M7, and the output inverted by the inverter 15 is input to the gate of the transistor M9. In addition, the output of capacitor C1 is further connected to Poldisi follower circuit 1.
3 is entered. If the temperature characteristics of a Zener diode are the same as those of a diode, then the transistor Q
The emitter voltage of 1 is v1=V2-V□, which does not change with temperature, and the transistor M1 has a voltage of 11=v1/R.
2 flows through the transistor M3.2 due to the current mirror circuit. A current of ■1 is also flowing through M5. When the output of the NAND circuit 11 is in the H1 state and the output of the NOR circuit 12 is in the L state, the transistor M6. M7 is 0FFL, transistors M8 and M9 are ON, and the current flowing to transistor M3 flows to the ground via transistor M8, and current flows from the power supply to transistor M5 via transistor M9, so capacitor C1 is charged and discharged. It has not been. At this time, when the reference signal changes from L to H level, the NAND
The output of the circuit 11 changes from H to L, and the transistor M6
is ONL, transistor M8 is 0FFL capacitor C1
is charged by electric current t. When the voltage of capacitor C1 rises to the voltage vFl set by resistors R3 and R4+R5, the output of voltage comparator 1 changes from H to L, a clock is input to D-FF7, and the output of D-FF becomes L. ,NA
The ND circuit 11 returns to H, charging is completed, and the capacitor C
1 is held as v8.

Next, when the reference signal changes from H to L, the output of the NOR circuit 12 changes from L to H, the transistor M7 is turned ON, the transistor M9 is turned OFF'L, and the capacitor C1 is charged by the current generator. The voltage of capacitor C1 is applied to resistor R5
When the voltage falls below the voltage VL set by R3+R4, the output of the voltage comparator 2 changes from L to H, a clock is input to D-FF8, the Q output of D-FF becomes H, and the NOR circuit 1
2 returns to L, the discharge ends, and capacitor C1 becomes VL.

The value is held as is.

By repeating the above cycle, the potential of the capacitor C1 changes in a trapezoidal waveform, and via the Poldigi follower circuit 13,
Output to the outside.

As described above, by generating a trapezoidal wave with a constant current that is free from power supply fluctuations and temperature fluctuations, fluctuations in the slope of the trapezoidal wave are suppressed.

FIG. 3 is a circuit diagram of a second embodiment of the present invention.

The output of the reference voltage circuit 17, which is free from fluctuations in power supply voltage and temperature, is input to the positive phase terminal of the Poldisi follower constituted by the differential amplifier 16 of the transistor MIO.

The drain of the transistor MIO is connected to a current mirror circuit, the gate is connected to the output of the differential amplifier 16, and the source is connected to the ground via a resistor R6. Furthermore, the source is connected to the anti-phase terminal of the differential amplifier 16. If the voltage generated by the reference voltage generation circuit is VR, then the transistor MIO
The current flowing through is I n ” V n/R6.I
8 charges and discharges the capacitor C1 via a current mirror circuit.

Note that the operation is similar to that of the first embodiment.

〔Effect of the invention〕

As explained above, the present invention allows a capacitor to be charged, discharged, and
By holding, a trapezoidal wave is generated, and by using the trapezoidal wave in the sample and hold circuit of the PLL circuit, a highly stable PLL circuit can be constructed.

[Brief explanation of the drawing]

1 and 3 are the first and second embodiments of the present invention, respectively.
The circuit diagram of the trapezoidal wave generation circuit according to the embodiment of FIG.
FIG. 3 is a waveform diagram of each part of the trapezoidal wave generation circuit shown in the figure. FIG. 4 is a circuit diagram of a conventional trapezoidal wave generating circuit. ■, 2... Voltage comparator, 3, 4, 5, 6, 10
゜14.15,18,19... Inverter, 7
゜8...D-FF, 11...NAND
Circuit, 12...NOR circuit, 13.16...
...Differential amplifier, 17...Reference voltage generation circuit, R...Resistor, C...Capacitor, Q
・・・・・・Bipolar transistor, M・・・・・・
MOSFET) transistor, ZD...Zener diode, D...diode. Agent Patent Attorney Uchihara Sound Diagram Z

Claims (1)

[Claims] A constant current circuit that generates a constant current based on the reference voltage of a Zener diode, a capacitor whose one terminal is grounded, a current mirror circuit that uses the constant current of the constant current circuit as an input current, and a constant current discharge circuit that is connected to a constant current circuit and conducts to discharge the capacitor via the other terminal of the capacitor by a control signal; and a constant current discharge circuit that conducts to charge the capacitor with a constant current by a control signal. a constant current charging circuit, and first and second comparators each having a first and second voltage created by resistance division as threshold voltages, and when the charging voltage of the capacitor exceeds the first threshold, the a charging voltage detection circuit that sends the control signal to the constant current charging circuit to stop charging, and further sends the control signal to the constant current discharge circuit to stop discharging when the discharge voltage of the capacitor becomes equal to or lower than the second threshold; , a first control circuit that starts operating the constant current charging circuit when the reference signal rises, a second control circuit that starts operating the constant current discharging circuit when the reference signal falls, and a charging voltage of the capacitor. further comprising a voltage follower circuit inputting
A trapezoidal wave generating circuit characterized in that the output of the voltage follower circuit is a trapezoidal wave output.