JPH01316870A - Vector register division control system - Google Patents

Abstract

PURPOSE:To run plural operating systems (OS) on a virtual computer without saving/restoring a vector register in parallel by allocating the vector register of a vector processing unit on every different OS. CONSTITUTION:The same data as that in the vector register 1-1 is stored in the vector register 1-2 ordinarily, and the same data is written on the same address even when write is performed. The vector register 1-2 equipped due to insufficient read throughput of the vector register 1-1 is separated logically including a computing pipe, and an address register 3-2 and a write data register 4-2 are separated logically from an address register 3-1 and a write data register 4-1, then, another OS is attached. Also, it is possible to attach a means to divide the vector register into plural ones same in size or to connect it to an arbitrary number.

Description

[Detailed Description of the Invention] [Summary] Regarding efficient resource management technology for virtual computers in vector data processing devices, the present invention relates to efficient resource management technology for virtual computers in vector data processing devices. In order to reduce the time lost due to replacing the contents of registers, it is necessary to provide multiple vector registers or
Alternatively, it may be configured by providing means for dividing the vector registers and allocating them to each operating system.

[Industrial application field]

The present invention relates to efficient virtual machine resource management technology in a vector data processing device.

In recent years, vector computers and data processing devices (so-called supercomputers) have become widely used for high-speed data processing in the fields of science and technology. There is an increasing demand for operations on data processing devices.

On a vector data processing device running a virtual computer,
When a vector data processing unit is shared by different O8s, efficient resource management is required.

[Conventional technology]

FIG. 5 is a diagram explaining the vector data processing unit, in which 51 is a main memory, 52 is a scalar unit, 5
3 is a vector processing unit), 54-1 to 54-n are arithmetic pipelines, and 55 is a vector register (VR
).

In the figure, commands read from main memory 51 are executed by scalar unit 52, but those that perform vector operations are entrusted to vector data processing unit 53.

Vector operations are normally processed as RR-type instructions in a vector processing device having a VR, and in the vector data processing unit 53, the main memory 51
The data loaded into the vector register 55 is processed in parallel by the arithmetic pipelines 54-1 to 54-n, and only the final result is stored in the main memory 51.

The vector register 55 has a much faster access speed than the main memory 51, and since the arithmetic pipeline can be expected to perform very high-speed arithmetic operations as is well known, such a vector data processing unit is By providing this, multiple operations related to vector data can be processed at high speed.

[Problem that the issue is trying to solve]

In an information processing device equipped with a vector data processing unit as described above, when multiple operating systems (hereinafter also referred to as O8) are to be operated in parallel by time sharing using this as a virtual computer, the running O8 Each time the vector register is switched, the contents of the vector register must be saved to main memory, etc., and then reloaded.

Originally, a vector data processing unit processes data read from vector registers with fast access speeds using an arithmetic pipeline, without frequently accessing main memory, which has relatively slow access speeds, and returns the results to vector registers. This also greatly contributed to the increase in calculation speed, as it was only necessary to repeat the operation of returning to main memory and return only the final result to main memory. Processing of saving data to the main memory or the like and reloading (save/restore) will reduce the processing speed of this information processing device. The capacity of the vector register is quite large (for example, Halo 4KB).

In addition, in the past, such vector register save/restore processing was performed by software, resulting in a significant deterioration in the performance of information processing devices, and an improvement was desired.

The present invention has been made in consideration of these conventional problems, and aims to provide a means for configuring and controlling vector registers that allows a plurality of O8s to efficiently use a virtual machine equipped with a vector processing unit. There is.

[Means to solve the problem]

According to the invention, the above-mentioned object is achieved by the means specified in the claims. That is, in a vector data processing unit of a virtual computer that runs a plurality of operating systems simultaneously, the invention of claim 1 provides vector register division control that provides a plurality of vector registers and includes means for allocating different vector registers to each operating system. Further, the invention of claim 2 provides a vector register comprising: means for dividing a vector register into a plurality of vector registers each having the same size; and means for allocating the vector register divided by the above means to each operating system. It is a register control method.

The invention of claim 3 provides means for dividing the vector 1/gister into a plurality of vector registers each having the same size, and a means for connecting an arbitrary number of the divided vector registers for each operating system. A vector register division control system is provided with a means for allocating vector registers divided by a vector register or registers concatenated after division. This is a vector register division control system that includes a vector register address conversion mechanism that includes a conversion table that logically connects discontinuous vector registers.

〔Example〕

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, in which 1-1.1-2 is a vector register;
~2-4 are respectively calculation pipelines, 3-1.3-2
4-1, 4-2 are write data registers, and 5 to 7 are selectors.

In the figure, vector registers 1-2 usually contain
It contains exactly the same data as vector register 1-1, and when writing, exactly the same data is written to the same address. The vector register 1-2 is originally provided because the vector register 1-1 does not have enough slots. In this embodiment, this vector register 1-2 is logically separated including the arithmetic pipe attached to it, that is, the address register 3-2 and the write data register 4-2 are separated from the address register 3-2.
1. Logically separate it from the write data register 4-1 and assign it to another O8. In this way, saving/restoring vector registers is not necessary. This method has the advantage that the capacity of the vector register does not change.

FIG. 2 is a block diagram showing the configuration of a second embodiment of the present invention, and shows a case where one vector register is logically equally divided into several smaller vector registers.

In the figure, 8-1 to 8-4 are address registers (in the figure, the abbreviation is AR), and 9-1 to 9-4 are write data registers (in the figure, the abbreviation is WDR). , 10-1 to l0-4 are vector register banks 1 to 4. 11.13 are crossbar switches, 1
2-1 to 12-4 represent operational pinlines.

Vector data processing devices that are currently commercially available are equipped with vector registers with a capacity that corresponds to their performance depending on the model. That is, the capacity of the vector register is small in the lower model, and larger in the higher model. This difference in capacity is generally dealt with by extending the address of the vector register in the depth direction (register length) instead of extending the address.

That is, the number of elements in one address of the vector register is changed. Generally, the hardware configuration of this element-oriented vector register is divided into a plurality of banks. Therefore, this bank unit can be logically divided into small vector registers each having a register length that is the minimum value allowed by the specifications. In the case of FIG. 2, it is possible to use three types of registers: four small vector registers, two small vector registers, and one vector register. From a hardware perspective, the upper bits of the element's index register can be regarded as the domain address of the virtual machine.

Next, a third embodiment will be described. This is the second
In this embodiment, an arbitrary number of divided small vector registers are connected to form a medium vector register, and the medium vector register is allocated to a virtual machine.

That is, in the case of the configuration shown in FIG. 2, in the method of the second embodiment, it is divided into eight small vector registers, or
There are only four possibilities: dividing it into three small vector registers, dividing it into two small vector registers, or using it as one vector register without dividing it.

Therefore, if the capacity of one bank is, for example, 32 KB, the configuration shown in Table 1 is the only option.

As shown in Table 1, when three vector registers are operated simultaneously, a configuration of 64 KB x 4 must be adopted, leaving 64 KB of vector registers completely unused. In order to solve this problem, this embodiment logically connects a plurality of consecutive banks, and in the above case, it is possible to configure 128 KB x 1 and 64 KB x 2.

In this case, the hardware is exactly the same as in the second embodiment, but the software is implemented by assigning a plurality of small vector registers to one virtual computer domain. However, if the small vector registers to be connected are not physically consecutive, it will be necessary to perform address conversion of the vector registers by software, which may reduce performance.

Such problems can be solved by providing a vector register address translation mechanism as shown in FIG.

In the figure, 14 is a register that stores virtual machine domain information (hereinafter referred to as VM domain), 15 is a register that stores a logical index, 16 is a register that stores a physical index, 17 is a conversion table, and 18 is an adder. It represents.

In this way, a conversion table 17 (consisting of register stutter, RAM, etc.) is prepared that outputs the high-order real index addressed by the VM domain of the register 14, and the conversion table 17 outputs the high-order real index of the VM domain and the real vector register in this conversion table. By registering bit correspondences (which can be freely rewritten by instructions), vector registers can be dynamically reassigned without deteriorating performance.

The third embodiment is equipped with such a vector register address conversion mechanism.

FIG. 4 is a block diagram showing the configuration of a fourth embodiment of the present invention, in which 19 is a register storing a VM domain;
0 is a selector, 21 is a translation table, 22 is an address translation mechanism, 23-1 to 23-8 are decoders, 24-1 to 2
4-8 is a write data register, 25.26-1 to 26
-4 and 27-1 to 27-4 are selectors, 28-1 to
28-4 and 29-1 to 29-4 represent vector register banks 1 to 4 (vector registers are indicated as VR in the figure); group is used as the current vector register 33-1 in normal use, while the vector registers 29-1 to 29-4 (7)! ! H;
! It is used as a vector register 33-2 for copying.

Also, 30-1, 30-2 and 32-1, 32-
2 represents a crossbar switch, and 31-1 to 31-4 represent calculation pipelines.

In this embodiment, as described above, the vector registers 29-1 to 29-'4 are used as vector registers for copying in normal use, thereby improving the vector register throughput.

The vector register 33-1 and the vector register 33-2 for copying each have four banks (28-1 to 28-2).
8-4 and 29-1 to 29-4), and has a hardware address translation mechanism 22.

The vector register 33-1 and the copy vector register 33-2 can be logically separated and assigned to different operating systems.

It is also possible to regard each bank as 8, 4, 2, or 1 small vector registers and allocate a different O8 to each bank.

Furthermore, it is possible to allocate multiple small vector registers that are physically contiguous to one VM domain, and by using a vector register address translation mechanism, it is possible to allocate multiple small vector registers that are physically contiguous to one VM domain. It is possible to allocate any number of small vector registers.

The above-mentioned functions can also be implemented in any combination.

〔Effect of the invention〕

As explained above, according to the present invention, when an information processing device equipped with a vector processing unit is operated in parallel as a virtual computer by multiple operating systems, the vector registers of the vector processing unit are Since multiple operating systems can be run in parallel on a virtual machine without saving/restoring vector registers, there is an advantage that processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a first embodiment of the invention, FIG. 2 is a block diagram showing the configuration of a second embodiment of the invention, and FIG. 3 is an example of a vector register address translation mechanism. FIG. 4 is a block diagram showing the configuration of a fourth embodiment of the present invention, and FIG. 5 is a diagram explaining a vector processing unit. 1-1.1-2.10-1 to 10-4, 28-1 to 2
8-4, 29-1 to 29-4...Vector register, 2-1 to 2-4.12-1 to 12-4.311
~31-4... Arithmetic pipeline, 3-1.3
-2°8-1 to 8-4. ...Address register, 4-1, 4-2. 9-1~9-4.24-1~2
4-8...Write data register, 5, 6, 7
,20°25.26-1~26-4,27-1~27
-4...Selector, 11. 13.30-1
, 14-16. 19...Register, 17.
21...Conversion table, 18...Adder, 30-2.32-1.32-2...Crossbar switch, 33-1...Currently used vector register, 33-2...Vector register for copying

Claims (1)

[Claims] 1. In a vector data processing unit of a computer that has a vector data processing unit and runs multiple operating systems simultaneously, a plurality of vector registers are provided, and means is provided for allocating a different vector register to each operating system. A vector register division control method characterized by: 2. Means for dividing a vector register into a plurality of vector registers of equal size in a vector processing unit of a computer having a vector data processing unit and running multiple operating systems simultaneously. 1. A vector register division control method, comprising means for allocating vector registers. 3. In the vector data processing unit of a computer having a vector data processing unit and running multiple operating systems simultaneously, means for dividing a vector register into a plurality of vector registers each having the same size, and a means for dividing the divided vector register into a plurality of vector registers, each having the same size. A vector register division control method comprising: means for concatenating an arbitrary number of registers; and means for allocating the vector registers divided by the above means or the registers concatenated after division for each operating system. 4. The vector data processing unit according to claim 3, further comprising a vector register address conversion mechanism having a conversion table for logically connecting physically discontinuous vector registers. control method.