JPH0131301B2 - - Google Patents

Info

Publication number
JPH0131301B2
JPH0131301B2 JP56124081A JP12408181A JPH0131301B2 JP H0131301 B2 JPH0131301 B2 JP H0131301B2 JP 56124081 A JP56124081 A JP 56124081A JP 12408181 A JP12408181 A JP 12408181A JP H0131301 B2 JPH0131301 B2 JP H0131301B2
Authority
JP
Japan
Prior art keywords
circuit
substrate
bias voltage
semiconductor integrated
capacitive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56124081A
Other languages
Japanese (ja)
Other versions
JPS5795659A (en
Inventor
Junichi Inoe
Tsuneo Mano
Takashi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56124081A priority Critical patent/JPS5795659A/en
Publication of JPS5795659A publication Critical patent/JPS5795659A/en
Publication of JPH0131301B2 publication Critical patent/JPH0131301B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0214Particular design considerations for integrated circuits for internal polarisation, e.g. I2L

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は基板バイアス電圧の変動が小さい半導
体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device with small fluctuations in substrate bias voltage.

半導体基板を用いて、それにバイアス電圧が与
えられることにより動作する半導体集積回路を形
成せる半導体チツプが配される半導体装置におい
ては、基板電流が回路動作によつて変動するの
で、それによつて基板バイアス電圧が変動し、こ
の変動が大きくなると回路が誤動作を起こすとい
う問題がある。第1図は一例として16Kビツト
MOS RAMについて動作時の基板電流測定の結
果を示したものである。図中、1はRAMを動作
させるために外部から入力するクロツク電圧波形
であり、振幅は5V、周期は1μsである。2は
RAMにクロツク1を入力したときの基板電流で
あり、ピーク値で±5mA程度流れている。この
基板電流の変動によつて、回路動作開始後(クロ
ツク1が低レベル)及び回路動作終了後(クロツ
ク1が高レベル)に基板バイアス電圧が大きく変
動する。この基板バイアス電圧の変動によつて回
路が誤動作する可能性があるので、この変動を小
さくする必要があるが、±5mAもの基板電流の
変動があるので、その基板バイアス電圧の変動を
容量素子により平滑して抑圧しようとすれば、非
常に大きな容量が必要となり、チツプ上に該容量
素子を搭載することは占有面積が大きくなるので
困難である。したがつて、従来は基板バイアス電
圧の変動を抑圧するために、チツプの外に大きい
平滑用容量素子を設けなければならないという欠
点があつた。
In a semiconductor device that uses a semiconductor substrate and includes a semiconductor chip that forms a semiconductor integrated circuit that operates by applying a bias voltage to the semiconductor substrate, the substrate current varies depending on the circuit operation, so the substrate bias There is a problem in that the voltage fluctuates, and if this fluctuation becomes large, the circuit will malfunction. Figure 1 shows 16K bits as an example.
This figure shows the results of measuring the substrate current of MOS RAM during operation. In the figure, 1 is a clock voltage waveform input from the outside to operate the RAM, and has an amplitude of 5V and a period of 1 μs. 2 is
This is the board current when clock 1 is input to the RAM, and the peak value flows around ±5mA. Due to this variation in substrate current, the substrate bias voltage varies greatly after the circuit operation starts (clock 1 is at a low level) and after the circuit operation ends (clock 1 is at a high level). This variation in substrate bias voltage may cause the circuit to malfunction, so it is necessary to reduce this variation, but since there is a variation in substrate current of ±5 mA, the variation in substrate bias voltage can be suppressed by using a capacitive element. If smoothing and suppression is attempted, a very large capacitance is required, and it is difficult to mount such a capacitive element on a chip because it occupies a large area. Therefore, in the past, a large smoothing capacitive element had to be provided outside the chip in order to suppress fluctuations in the substrate bias voltage.

また第2図は半導体集積回路チツプ上に容量を
設けて、それを回路動作に応じて充放電すること
により基板バイアス電圧を抑圧する構成を示した
ものである。図中、10は半導体集積回路チツ
プ、11はチツプ上で回路が構成されている部分
である。半導体集積回路11は外部から端子12
を通してクロツクを入力し動作するが、この回路
動作によつて基板電流が変動するため、基板バイ
アス電圧は回路動作開始時及び回路動作終了後
(プリチヤージ動作開始時)に大きく変動する。
ところで、第1図より、基板電流の変動は回路動
作開始後と終了後とでは、その極性が逆で変動量
はほゞ同じであることが分かる。即ち、基板バイ
アス電圧は回路動作開始時に低下し、終了時(プ
リチヤージ動作開始時)に増加する。そこで、チ
ツプ上に新たに容量素子を設け、これを回路の動
作に応じて充放電させて基板バイアス電圧の変動
を相殺している。
Further, FIG. 2 shows a configuration in which a capacitor is provided on a semiconductor integrated circuit chip and the substrate bias voltage is suppressed by charging and discharging the capacitor in accordance with the circuit operation. In the figure, 10 is a semiconductor integrated circuit chip, and 11 is a portion on which a circuit is constructed. The semiconductor integrated circuit 11 is connected to a terminal 12 from the outside.
The circuit operates by inputting a clock through the circuit, but since the substrate current fluctuates due to this circuit operation, the substrate bias voltage fluctuates greatly at the start of the circuit operation and after the circuit operation ends (at the start of the precharge operation).
By the way, it can be seen from FIG. 1 that the polarity of the fluctuation in the substrate current is opposite after the circuit operation starts and after the circuit operation ends, but the amount of fluctuation is almost the same. That is, the substrate bias voltage decreases at the start of the circuit operation and increases at the end (at the start of the precharge operation). Therefore, a new capacitive element is provided on the chip, and this is charged and discharged according to the operation of the circuit to offset the fluctuations in the substrate bias voltage.

第2図において、13が基板バイアス電圧の変
動を吸収するためにチツプ10上に新たに設けた
容量素子であり、この容量素子13の一端はトラ
ンジスタTR−1,TR−2の接続点に接続され、
他端は半導体集積回路11の基板バイアス供給線
に接続されている。14は容量素子13に充放
電々流を流す回路ブロツクで、インバータI、遅
延回路DL−1,DL−2、トランジスタTR−1,
TR−2より構成される。端子12のクロツクが
低レベルのとき、半導体集積回路11は動作状態
にあり、基板バイアス電圧は減少する傾向にあ
る。この時、トランジスタTR−1がオン、トラ
ンジスタTR−2はオフ状態をとるため、電源
VDDにより容量素子13は充電され、上記基板バ
イアス電圧の低下を保償する。一方、端子12の
クロツクが高レベルのときは、半導体集積回路1
1は動作終了すなわちプリチヤージ動作状態にあ
り、基板バイアス電圧は増加する傾向にある。こ
の時、トランジスタTR−2がオン、トランジス
タTR−1はオフ状態をとるため、容量素子13
の電荷はTR−2を通して放電し、上記基板バイ
アス電圧の増加を保償する。このように、容量素
子13を半導体集積回路11の動作に応じて充放
電させることにより、基板電流の変動が相殺さ
れ、基板バイアス電圧を一定に保つことができ
る。しかし、容量素子13の容量は回路11の中
でプリチヤージ、デイスチヤージ動作を行う部分
の容量の総和に等しい容量をもつていなければな
らず、そのために面積の大きい容量をチツプ上に
搭載する必要があつた。
In FIG. 2, numeral 13 is a capacitive element newly installed on the chip 10 to absorb fluctuations in substrate bias voltage, and one end of this capacitive element 13 is connected to the connection point of transistors TR-1 and TR-2. is,
The other end is connected to the substrate bias supply line of the semiconductor integrated circuit 11. 14 is a circuit block that causes charging and discharging current to flow through the capacitive element 13, and includes an inverter I, delay circuits DL-1, DL-2, transistors TR-1,
It consists of TR-2. When the clock at terminal 12 is at a low level, semiconductor integrated circuit 11 is in an operating state and the substrate bias voltage tends to decrease. At this time, transistor TR-1 is on and transistor TR-2 is off, so the power supply
The capacitive element 13 is charged by V DD to ensure that the substrate bias voltage does not decrease. On the other hand, when the clock at terminal 12 is at a high level, semiconductor integrated circuit 1
1 is in a state where the operation is completed, that is, in a precharge operation state, and the substrate bias voltage tends to increase. At this time, the transistor TR-2 is on and the transistor TR-1 is off, so the capacitive element 13
The charge is discharged through TR-2 to ensure the increase in the substrate bias voltage. In this way, by charging and discharging the capacitive element 13 according to the operation of the semiconductor integrated circuit 11, fluctuations in the substrate current are offset, and the substrate bias voltage can be kept constant. However, the capacitance element 13 must have a capacitance equal to the sum of the capacitances of the parts in the circuit 11 that perform pre-charge and discharge operations, and for this reason, it is necessary to mount a large-area capacitor on the chip. Ta.

本発明は、このような欠点を解決するため、半
導体集積回路のチツプ上の回路を動作タイミング
の異なる複数個の回路ブロツクに分割し、各回路
ブロツクに上記容量素子と同等の働きをさせるよ
うにしたもので、以下図面について詳細に説明す
る。
In order to solve these drawbacks, the present invention divides the circuit on a semiconductor integrated circuit chip into a plurality of circuit blocks with different operation timings, and makes each circuit block function in the same way as the capacitive element described above. The drawings will be described in detail below.

第3図は本発明の実施例を示したもので、チツ
プ10上で半導体集積回路が構成される部分を1
1−A,11−Bの2つの回路ブロツクに分割し
て、端子12に印加するクロツクが低レベルの
時、回路ブロツク11−Aを動作期間、回路ブロ
ツク11−Bをプリジヤージ期間とし、また、端
子12のクロツクが高レベルの時は逆に、回路ブ
ロツク11−Bを動作期間、回路ブロツク11−
Aをプリチヤージ期間としたものである。即ち、
回路ブロツク11−Aの動作開始時の基板電流の
変動は、回路ブロツク11−Bのプリチヤージ開
始時の逆方向の基板電流によつて抑圧し、また回
路ブロツク11−Bの動作開始時の基板電流変動
は回路ブロツク11−Aの逆方向の基板電流によ
つて抑圧するのである。この結果、半導体集積回
路チツプ10としては、第2図のような容量素子
13を搭載することなく回路動作時及びプリチヤ
ージ時の基板電流が抑圧され、基板バイアス電圧
の変動を小さくすることができる。
FIG. 3 shows an embodiment of the present invention, in which a portion of a semiconductor integrated circuit is formed on a chip 10.
The circuit is divided into two circuit blocks 1-A and 11-B, and when the clock applied to the terminal 12 is at a low level, the circuit block 11-A is set as the operating period and the circuit block 11-B is set as the precharge period. Conversely, when the clock at terminal 12 is at a high level, circuit block 11-B is activated during the operation period, and circuit block 11-B is
A is the precharge period. That is,
The fluctuation of the substrate current at the start of the operation of the circuit block 11-A is suppressed by the substrate current in the opposite direction at the start of the precharge of the circuit block 11-B, and the fluctuation of the substrate current at the start of the operation of the circuit block 11-B is suppressed. The fluctuations are suppressed by the substrate current in the opposite direction of circuit block 11-A. As a result, the semiconductor integrated circuit chip 10 can suppress the substrate current during circuit operation and precharge without mounting the capacitive element 13 as shown in FIG. 2, and can reduce fluctuations in the substrate bias voltage.

なお、本発明は第2図と第3図を組合せて実施
してもよく、その場合は、第2図の容量素子13
は一つの回路ブロツクの動作による基板電流を抑
圧すればよいため、第2図のときに必要であつた
容量の1/n(nは回路ブロツクの数)の容量で
足りるという利点がある。
Note that the present invention may be implemented by combining FIG. 2 and FIG. 3, and in that case, the capacitive element 13 in FIG.
Since it is sufficient to suppress the substrate current due to the operation of one circuit block, there is an advantage that a capacitance that is 1/n (n is the number of circuit blocks) of the capacitance required in the case of FIG. 2 is sufficient.

以上説明したように、本発明によれば、回路動
作に合わせて基板電流の変動を抑圧しているの
で、チツプの外に大きな容量素子を設けることな
く、基板バイアス電圧の変動の小さい半導体集積
回路が構成できるという利点がある。
As explained above, according to the present invention, since fluctuations in substrate current are suppressed in accordance with circuit operation, semiconductor integrated circuits with small fluctuations in substrate bias voltage can be realized without providing a large capacitive element outside the chip. It has the advantage of being configurable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体集積回路の動作時の基板電流変
化を説明する図、第2図は従来の構成を示す図、
第3図は本発明の実施例を示す図である。 10……半導体集積回路チツプ、11……回路
構成部、12……クロツク入力端子、13……容
量素子、14……充放電回路。
FIG. 1 is a diagram explaining changes in substrate current during operation of a semiconductor integrated circuit, FIG. 2 is a diagram showing a conventional configuration,
FIG. 3 is a diagram showing an embodiment of the present invention. 10... Semiconductor integrated circuit chip, 11... Circuit component, 12... Clock input terminal, 13... Capacitive element, 14... Charge/discharge circuit.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板を用いてそれにバイアス電圧が与
えられることにより動作する半導体集積回路を形
成せる半導体チツプが配されてなる半導体装置に
おいて、前記半導体集積回路を基板上に偶数個の
回路ブロツクに分割して搭載し、さらに同数の回
路ブロツクになるように2群化して両群間で動作
期間と待機期間を逆相にすることを特徴とする半
導体装置。
1. In a semiconductor device in which a semiconductor chip is arranged to form a semiconductor integrated circuit that operates by applying a bias voltage to a semiconductor substrate, the semiconductor integrated circuit is divided into an even number of circuit blocks on the substrate. What is claimed is: 1. A semiconductor device equipped with a semiconductor device, further divided into two groups so as to have the same number of circuit blocks, and having an operation period and a standby period in opposite phases between the two groups.
JP56124081A 1981-08-10 1981-08-10 Semiconductor device Granted JPS5795659A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56124081A JPS5795659A (en) 1981-08-10 1981-08-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56124081A JPS5795659A (en) 1981-08-10 1981-08-10 Semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP54062534A Division JPS5950225B2 (en) 1979-05-21 1979-05-21 semiconductor equipment

Publications (2)

Publication Number Publication Date
JPS5795659A JPS5795659A (en) 1982-06-14
JPH0131301B2 true JPH0131301B2 (en) 1989-06-26

Family

ID=14876450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56124081A Granted JPS5795659A (en) 1981-08-10 1981-08-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5795659A (en)

Also Published As

Publication number Publication date
JPS5795659A (en) 1982-06-14

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