JPH01312616A - Driving circuit for data bus - Google Patents

Abstract

PURPOSE:To always attain accurate data transfer by turning on first and third transistors only in a data bus write permission period at the time of a test mode, and complementarily turning off second and fourth transistors in correspondence with the signal of data to be written into a data bus. CONSTITUTION:At the test mode, the second and fourth transistors 11 and 14 are complementarily, turned off in correspondence with data to be written into the data bus 2, and the data bus 2 is connected with a power source or a ground, whereby the writing into the data bus 2 is attained. In a period when the writing into the data bus 2 is not permitted at the test mode, the first and third transistors 10 and 13 are turned off, and therefore the data bus 2 can be held in a high impedance state. Thus, accurate data transfer is attained even in the test mode when a cycle time is long.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to data bus driving circuits, and more particularly to integrated circuits that operate with short cycle times in normal mode and long cycle times in test mode. The present invention relates to a circuit for driving a data bus used in a circuit device.

[Prior Art] FIG. 3 is a block diagram showing the general configuration of a conventional semiconductor integrated circuit device and a test device connected thereto. In the figure, an LSI chip 1 is provided with a data bus 2 for transmitting data between each circuit. This data bus 2 includes a data memory 3, an ALU 4, and logic circuits (such as inverters and various gate circuits).
5 etc. are connected. However, this FIG. 3 merely shows an example of an integrated circuit device, and a circuit different from that shown in the figure may be connected to the data bus 2. Further, the LSI chip 1 is provided with a bus drive circuit 6 for driving the data bus 2. Note that the present invention relates to an improvement of this bus drive circuit 6.

In the above configuration, when testing the LSI chip 1, the external test device 7 tests the LSI chip 1.
It is connected to the logic circuit 5 via the input/output pins of.

FIG. 4 is a diagram showing the configuration of a conventional bus drive circuit.

In the figure, the data bus 2 has a parasitic capacitance 8 between it and ground.
have. Furthermore, a P-channel transistor 9 whose drain electrode is connected to the data bus 2 and whose source electrode is connected to the power source Vdd is inserted between the data bus 2 and the power source Vdd. A precharge clock TpC is applied to the gate electrode of this transistor 9.

This transistor 9 is a transistor for precharging the data bus 2, and is therefore hereinafter referred to as a precharging transistor.

Furthermore, two N-channel type transistors 10 and 11 connected in series are inserted between data bus 2 and ground. The transistor 10 has its drain electrode connected to the data bus 2 and its source electrode connected to the drain electrode of the transistor 11. Further, the source electrode of the transistor 11 is grounded. A bus write enable signal TBs is applied to the gate electrode of transistor 10. A latch 1 is connected to the gate electrode of the transistor 11.
2 outputs are given.

This latch 12 holds the data D to be written to the data bus 2.
Holds I.

Next, the operation of the conventional circuit shown in FIG. 4 will be explained.

Since this bus drive circuit employs a data bus precharging method, first, the precharge clock rpc is kept at the "L" level for a certain period of time, and the precharging transistor 9 is made conductive. Therefore, the parasitic capacitance 8 of the data bus 2 is charged from the power supply Vdd, and the data bus 2 is precharged to the "H level."
When the precharge period ends, the write period of data bus 2 begins, and the bus write enable signal Tas remains “ for a certain period of time.
It will be brought to H2 level. Therefore, the transistor 10 is in a conductive state for the certain period of time. At this time, if the output of the latch 12 is 'H' level, the transistor 1
1 becomes conductive, and the charge charged in the parasitic capacitance 8 is drawn out to ground. As a result, the potential of data bus 2 is “L”.
” level. On the other hand, at this time, the output of the latch 12 becomes “L” level.
If so, the transistor 11 is in a non-conductive state, and charge is not extracted from the parasitic capacitance 8. Therefore, the potential of the data bus 2 is held at the H level. Therefore, an inverted signal of the input data DI is output to the data bus 2.

The above operation is the same regardless of the normal mode or the test mode (a mode for testing the LSI chip 1 with the test device 7 as shown in FIG. 3).

[Problems to be Solved by the Invention] Incidentally, in the normal mode, the operating speed, that is, the cycle time, of the LSI chip 1 is extremely high (for example, several ns). In contrast, test mode (i.e.
In the mode in which the test device 7 tests the LSI chip 1 as shown in FIG.
The cycle time of is regulated by its user program. The cycle time according to this user program is generally extremely slow (for example, several μs). Therefore, the period for writing data to data bus 2 becomes longer, but when outputting "H" level to data bus 2 (in this case, transistors 9, 10 and 11
(all of them are in a non-conducting state), the electric charge charged in the parasitic capacitance 8 gradually decreases due to the leakage current flowing through the transistors 10 and 11, and the potential of the data bus 2 gradually decreases from the "H" level. do. As a result, the logical value of the data bus 2, which was originally "H", may be determined to be "L", causing malfunction.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a data bus drive circuit that can perform accurate data transfer even in a test mode with a long cycle time.

[Means for Solving the Problems] A data bus drive circuit according to the present invention includes a precharging transistor inserted between the data bus and the power source, and a precharging transistor connected in series between the data bus and the power source. the first and second transistors inserted in the normal mode, the third and fourth transistors connected in series between the data bus and the ground, and the precharging transistor. means for turning on only the bus precharge period; means for turning on the first and third transistors only during the data bus write period in the normal mode and the data bus write permission period in the test mode; and the fourth transistor is turned on and off in a complementary manner according to the data signal to be written to the data bus.
The device also includes means for turning off the power.

[Function] In the test mode, the second and fourth transistors are turned on and off in a complementary manner according to the data to be written to the data bus, and the data bus is connected to the power supply or ground, thereby preventing writing to the data bus. I try to do it. Furthermore, during a period in which writing to the data bus is not permitted in the test mode, both the first and third transistors are turned off to maintain the data bus in a high impedance state.

[Embodiment] FIG. 1 is a circuit diagram showing an embodiment of the present invention. In this embodiment, the same reference numerals are given to the same parts as in the conventional circuit shown in FIG. 4, and the explanation thereof will be omitted.

In the embodiment shown in FIG. 1, the configuration of the conventional circuit shown in FIG.
P-channel transistors 13 and 14 and an inverter 15 are added. Transistors 13 and 14
are connected in series and inserted between the data bus 2 and the power supply Vdd. The transistor 13 has its drain electrode connected to the data bus 2, and its source electrode connected to the drain electrode of the transistor 14. Further, the source electrode of the transistor 14 is connected to the power supply Vdd. A bus write enable signal Tas is inverted by an inverter 15 and applied to the gate electrode of the transistor 13. Furthermore, the output of the latch 12 is applied to the gate electrode of the transistor 14 . here,
The size (eg, gate width) of transistors 13 and 14 is selected to be smaller than that of precharge transistor 9. This makes it possible to reduce the increase in chip area due to the increase in the number of transistors.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

First, the operation in normal mode will be explained. in this case,
First, the precharge clock TpC is set to “L#” for a certain period of time.
The precharging transistor 9 is made conductive, and the potential of the data bus 2 is charged up to the power supply voltage Vdd.

Thereafter, the precharge clock Tr C is set to "H" level to make the precharge transistor 9 non-conductive, and the bus write enable signal Tas is set to "H" level. Therefore, the transistors 10 and 13 are made conductive. At this time, if the data DI held in the latch 12 is at the "H2 level," the transistor 11 becomes conductive and the transistor 14 becomes non-conductive. As a result, the charge stored in parasitic capacitance 8 is drawn to ground via transistors 10 and 11, and the potential of data bus 2 is brought to the "L" level. On the other hand, if the data DI held in the latch 12 is at "L" level, the transistor 14
is in a conductive state, and the transistor 11 is in a non-conductive state. Therefore, data bus 2 is connected to power supply Vdd via transistors 13 and 14. Therefore, the potential of data bus 2 is kept at "H" level.

Next, the operation in a test mode with a long cycle time will be explained. In this case, precharge clock TP
c is fixed at "H" level. Therefore, precharge transistor 9 is always in a non-conductive state in the test mode, and data bus 2 is not precharged. When writing data to data bus 2, bus write enable signal Tas is set to "H" level. As a result, both transistors 10 and 13 become conductive. Then, transistors 11 and 14 are selectively rendered conductive in accordance with data DI held in latch 12, and data bus 2 is selectively connected to ground and power supply Vdd. That is, when the data DI held in the latch 12 is at "H" level, the transistor 11 becomes conductive, the data bus 2 is connected to the ground, and "L° data is output to the data bus 2. On the other hand, When the data DI held in the latch 12 is at the "L" level, the transistor 14 becomes non-conductive and the data bus 2 is connected to the power supply Vd.
d, and “H” data is output to the data bus 2. Note that, as mentioned above, the transistors 13 and 1
Since the size of the precharge transistor 4 is selected to be smaller than that of the precharge transistor 9, the data bus 2 is charged up more slowly than the charge up by the precharge transistor 9 during normal operation. However, because the cycle time is long in test mode, even if the charge-up operation is delayed a little,
No problem occurs in the operation of the circuit.

As mentioned above, in the embodiment shown in FIG. 1, when writing data to the data bus 2 in the test mode, the data bus 2 and the voltage 1Vdd are directly connected to perform "H" writing. Unlike conventional circuits, the problem of lowering the potential of the data bus 2 due to leakage current does not occur.

By the way, a plurality of bus drive circuits as shown in FIG. 1 are usually connected to one data bus (however,
Only one precharge transistor 9 is required). In such a configuration, if two or more bus drive circuits are operated simultaneously, a large through current will flow between the bus drive circuits, leading to destruction of the device. Therefore, when writing data to the data bus, the bus write permission signal TBS allows only one bus drive circuit to write to the data bus, and two or more bus drive circuits operate at the same time. I try not to. If the bus drive circuit shown in FIG. 1 is not permitted to write to the data bus, the corresponding bus write permission signal 'I'as is set to "L" level. Therefore, for this bus drive circuit, the data bus 2 is kept in a high impedance state, and the latch 12 is kept in a high impedance state.
The data held in the data bus 2 is not written to the data bus 2.

As is clear from the above description, in the test mode, the bus drive circuit shown in FIG.
It has three states: a state where "H" data is output, a state where "L" data is output, and a state where the data bus 2 is kept in a high impedance state, and it operates as a so-called tri-state buffer.

FIG. 2 is a circuit diagram showing another embodiment of the invention.

In this embodiment, an inverter 16 is added to the structure of the embodiment shown in FIG. This inverter 16 is
It is inserted between the output terminal of latch 12 and the gate electrodes of transistors 11 and 14. By providing such an inverter 16, in the embodiment shown in FIG. 2, the logical value of the data DI held in the latch 12 can be output onto the data bus 2 as is.

[Effects of the Invention] As described above, according to the present invention, even when the data bus is driven in a test mode with a long cycle time, the potential of the data bus does not decrease due to leakage current. Therefore, accurate data transfer can always be performed regardless of the normal mode or test mode.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the invention, and FIG. 2 is a circuit diagram showing another embodiment of the invention. FIG. 3 is a block diagram showing the general configuration of a conventional semiconductor integrated circuit and a test circuit connected thereto. FIG. 4 is a circuit diagram showing a conventional bus drive circuit. In the figure, 1 is an LSI chip, 2 is a data bus, 6 is a bus drive circuit, 7 is a test device, 8 is a parasitic capacitance, 9 is a precharge transistor, 10 and 11 are N-channel transistors, 13 and 14 are P A channel type transistor, 12 is a latch, and 15 and 16 are inverters.

Claims (1)

[Claims] A circuit for driving a data bus provided in an integrated circuit device that operates with a short cycle time in a normal mode and with a long cycle time in a test mode, comprising: a precharging transistor inserted between the data bus and the power supply; first and second transistors connected in series and inserted between the data bus and the power supply; and a ground connection between the data bus and the ground. third and fourth transistors connected in series and inserted between the first and third transistors; means for turning on the precharge transistor only during the data bus precharge period in the normal mode; means for turning on the transistor only during the data bus write period in the normal mode and the data bus write permission period in the test mode; A data bus driving circuit comprising means for complementary on/off depending on the signal of the data bus.