JPH01311858A - Gate drive circuit - Google Patents

Abstract

PURPOSE:To prevent elements easily and certainly from being damaged by providing either a normal mode choke coil or a common mode choke coil on a control signal output side of a gate drive circuit for high-speed switching semiconductor elements. CONSTITUTION:A gate drive circuit 9 is composed of a photocoupler 3, transistors(Tr) 4-6 and DC control power devices 7-8. With a switch 1 turned ON across its terminals C-B an FET is caused to be in an ON state, while the FET is set to work in an OFF state when terminals A and C are connected to switch ON. In this connection, normal mode choke coils 10 and 11 and a common mode choke coil 12 are provided. Thus, the control signal output terminals G and S of the gate drive circuit 9 are connected respectively to a gate terminal G and a source terminal S of the FET through the above choke coils 10-12 and the induced voltage or charge current caused by the sudden potential fluctuation in switching can be prevented from running into the above gate drive circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gate drive circuit for high-speed switching semiconductor devices such as MOS-FETs.

[Conventional technology]

As a conventional gate drive circuit of this type, the circuit diagram illustrated in FIG. 2 is known. FIG. 3 is an example of a circuit diagram of a step-down chopper circuit using the gate drive circuit shown in FIG. 2, and FIG. 4 is an operational waveform diagram in FIG. 3.

In Fig. 2, 1 is a switch, and when the terminal C-8 is closed, the DC control power supply 2 is connected and the photocoupler 3 is turned off.
NL, conversely, when the terminal C and A are closed, the power supply 2 is disconnected and the photocoupler 3 is set to 0 and FF,
It equivalently shows the operation of an external switching control circuit. 4 to 6 are transistors, and the photocoupler 3
When is ON, transistor 4 is OFF and transistor 5 is ON.
.

6 is turned off, and the potential of the gate drive output terminal G becomes higher than the potential of the same terminal S. On the contrary, the OF of the photocoupler 3
At F time, the transistor 4 is turned on.

5 is OFF, 6 is ON, and the potential of the terminal G becomes lower than the potential of the terminal S.

Note that 7 and 8 are DC control power supplies, R5-Re is a resistor, and the gate drive circuit 9a is composed of the aforementioned elements 3 to 8 and resistors R1 to R8.

Next, in FIG. 3, 15 is a DC power supply having voltage Edc, 18 is MO3-FET (MO3 type field effect transistor), and D, S, and G are 1MO3-FE, respectively.
The drain terminal, source terminal, and gate terminal of T are ■
4 is its drain current. Further, 16 is a wiring inductance between the positive electrode side of the power supply 15 and the terminal of the MO3-FET, 17 is a snubber diode, 19 is a reactor,
20 is a flywheel diode, 21 is a capacitor,
22 is a load resistance.

Next, FIG. 4 will be explained according to the circuit operation of FIG. 3.

Now, if the terminals C and 8 of the switch are turned on, the potential of the terminal G of the gate drive circuit 9a becomes higher than the potential of the terminal S as described above, the MO3-FET 18 becomes ON, and its drain current becomes 6 increases according to a slope determined by circuit constants.

This state is mode M. At this time, the MO3~FE
The drain voltage Vad and source voltage VaS of T18 are both substantially equal to the voltage Edc of the DC power supply 15.

Next, if the terminals C and -A of the switch 1 are turned on, the state is reversed to the state when the terminal C and -8 are closed, and the terminal G
The potential of the MOS-F becomes lower than the potential of the terminal S, and the potential of the MOS-F
ETI 8 starts OFF operation and its drain current 14
starts to decrease with the initial value immediately before turning ON between the terminals C and A of the switch 1, and eventually becomes zero, and the MO3-FE
TI 8 becomes OFF state. At this time, a part of the initial value current becomes a circulating current Ish in a closed circuit formed by the wiring inductance 1G and the snubber diode 17. At this time, the drain voltage Vad maintains the voltage Edc, and the source voltage Vas changes in the same way as the current Id decreases, and reaches zero. Further, as the voltage Vas decreases, the circulating current 1 due to the release of the stored energy of the reactor 19
fwd is the reactor and flywheel diode 2
0, capacitor 2], and load resistor 22 in the direction of the arrow shown in FIG. This state is mode M2.

Subsequently, when the OFF state of the MOS-FET progresses and the potential difference between its drain and source becomes equal to the voltage Edc, the current I fwd decreases according to the time constant of the closed circuit, and the voltage Vas decreases due to the voltage of the diode. 20
The potential becomes negative by the creeping voltage. This state is mode M.
It is.

Next, when the terminal C-8 of the switch 1 is turned on again and the MO3-FETI 8 is turned on, the MOS-
Since the source voltage Vas of the FET is at a negative potential close to zero as described above, the inrush current of the drain current (4) whose peak value is Ids flows through the wiring inductance 16. Due to the steep fluctuation of the hourly inrush current, its fluctuation rate d1. A large voltage drop proportional to /dt occurs in the wiring inductance 16, and the drain voltage Vad rapidly decreases due to this voltage drop.

This state is mode M4.

Next, the fluctuation rate d1 due to the end of the rush state of the drain current I4. With the disappearance of /dt, both the drain voltage Vad and the source voltage Vas rapidly recover to reach the voltage Edc, and thereafter enter a steady state. This state is mode M.

[Problem to be solved by the invention]

However, as mentioned above, when controlling the gate of a high-speed switching element such as a MOS-FET, the gate drive circuit according to the conventional method outputs the gate drive signal at its gate drive signal output terminal at the time of transition from mode M4 to mode M as shown in FIG. S undergoes a sudden change in potential, and due to the dielectric voltage based on the potential change, the photocoupler at the input section of the gate drive circuit also receives a sudden change in its emitter potential and enters the OFF state. Therefore, the high-speed switching element, which had once entered the ON state, is again reversed to the OFF state as an abnormal operation, and the smooth 0N-OFF
Control could be impaired. Incidentally, the potential fluctuation reaches 2000 V/μS.

In view of the above, the present invention provides a gate drive circuit that can perform normal gate drive control of a switching element even when a rapid potential fluctuation occurs at a control signal output terminal connected to the main circuit of a high-speed switching element to be controlled. For the purpose of providing.

[Means to solve the problem]

In order to achieve the above object, the gate drive circuit of the present invention receives a control signal via a photocoupler or the like and outputs a gate signal for ON or OFF operation of the semiconductor element for high-speed switching. In this method, both or one of a normal mode choke coil and a common mode choke coil are provided on the output side of the gate drive circuit, and the output gate signal is applied to the semiconductor element via the installed choke coil. .

[Effect]

As mentioned above, the cause of the malfunction of the gate drive circuit of a semiconductor device for high-speed switching is that the control output terminal of the gate drive circuit connected to the main circuit of the semiconductor device inevitably occurs due to the high-speed switching operation of the semiconductor device. Directly affected by rapid potential fluctuations, the dielectric voltage or charging current generated through the stray capacitance of each component of the gate drive circuit due to the potential fluctuation may disturb the normal voltage/current relationship of each component of the gate drive circuit. ,
It was there.

Therefore, in the present invention, a normal mode choke coil and/or a common mode choke coil is provided between the control signal output terminal of the gate drive circuit and the main circuit connection point of the semiconductor element to which the output terminal is connected. This is to prevent malfunction of the gate drive circuit by inserting one of them and preventing the effects of rapid potential fluctuations occurring in the main circuit from reaching the inside of the gate drive circuit.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a gate drive circuit showing an embodiment of the present invention. In FIG. 1, the same reference numerals are given to components having the same functions as in the prior art embodiment shown in FIG. 2. Furthermore, the connection relationship between the step-down chopper circuit shown in FIG. 3 and the circuit shown in FIG. 1 is the same as that between FIG. 3 and FIG. 2.

FIG. 1 shows the circuit diagram shown in FIG. 2 except that normal mode choke coils 10 and 11 and a common mode choke coil 12 are provided.

Note that the mark shown on the choke coil 12 indicates the winding polarity between the two windings.

Therefore, the control signal output terminals G and S of the gate drive circuit 9 are connected to the third
It will be connected to the gate terminal G and source terminal S of MOS-FETI 8 in the figure, respectively.
This prevents dielectric voltage or charging current from flowing into the gate drive circuit 9 due to rapid potential fluctuations on the source side of the S-FETI 8 during switching.

〔Effect of the invention〕

According to this invention, by providing both or either one of a normal mode choke coil and a common mode choke coil on the control signal output side of a gate drive circuit for a high-speed switching semiconductor device using a photocoupler or the like as a control input receiving element. , preventing the influence of rapid potential fluctuations of the semiconductor element main circuit from reaching the inside of the gate drive circuit, and easily preventing malfunction of the drive circuit and destruction of the semiconductor element due to abnormal switching caused by the malfunction; Moreover, it is possible to reliably prevent this.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the prior art, and FIG. 3 is a step-down chopper circuit combined with the circuit shown in FIG. 1 or 2. Figure, 4th
This figure is an operation waveform diagram of the circuit shown in FIG. 3 when the circuit shown in FIG. 2 is used. DESCRIPTION OF SYMBOLS 1... Switch, 2... DC control power supply, 3... Photocoupler, 4-6... Transistor, 7.8... DC control power supply, 9, 9a... Gate drive circuit, 10. 1
1... Normal mode choke coil, 12... Common mode choke coil, 15... DC power supply, 16
... Wiring inductance, 17 ... Snubber diode, 18 ... MOS-FET, 19 ... Reactor, 20 ... Flywheel diode, 21 ... Capacitor, 22 ... Load resistance, R1 ... Rs...Resistance. ψ Ihe~ni sui-/'1-1 fwd Figure 4

Claims (1)

[Claims] 1) In the gate drive circuit for the semiconductor device, which receives a control signal via a photocoupler or the like and outputs a gate signal for ON or OFF operation of the semiconductor device for high-speed switching,
The gate drive circuit is characterized in that both or one of a normal mode choke coil and a common mode choke coil is provided on the output side of the gate drive circuit, and the output gate signal is applied to the semiconductor element via the installed choke coil. Gate drive circuit.