JPH01309434A - Line simulator - Google Patents

Abstract

PURPOSE:To test the behavior and performance of a communication equipment against a communication fault occurred actually in an actual transmission line by giving a parameter such as a bit error rate and generating a noise based on a random number. CONSTITUTION:A parameter setting device 1 inputs a parameter such as a bit error rate to generate a noise occurred in the communication line to a simulator main body 3 via a bus 2. The simulator main body 3 holds the parameter set by the parameter setting device 1, and an error signal generating means generates an error signal decided by the setting parameter from a random number generated from a random number generating means. While the error signal is generated, a line section adds a noise decided by a parameter set by the parameter setting means to the signal inputted externally and the result is outputted. Thus, the operation of the communication equipment against the communication fault is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line simulator that simulates noise phenomena that may occur in communication signals for purposes such as performance testing of communication equipment.

[Prior Art] In recent years, with the development of digital communication technology, LSIs with built-in various communication procedures have been actively developed.
In order to test and evaluate LSIs developed for communication, it is necessary to incorporate phenomena that may occur in actual communication channels. In particular, noise is inherent in actual communication channels,
Errors due to noise occur in the transmitted signal. Therefore, communication LSIs must be designed taking into consideration the noise that may occur in the communication path. Therefore, in order to test a communication LSI when it is prototyped, a device is known that applies a certain amount of noise and measures the error rate (occurrence rate).

[Problem to be solved by the invention] However, in the conventional error rate measurement device, the noise given to the communication LSI is analog noise generated by an electrostatic noise generator, and its pattern is fixed to a constant one. Therefore, there was a problem in that it did not reflect noise and other phenomena that could actually occur, and it was not possible to measure error rates for various types of noise.

The present invention has been made in view of these problems, and when developing a communication LSI etc., it is possible to generate noise that can actually occur in a communication line in a simulated manner, and it is possible to repeatedly execute a specific noise generation procedure. The purpose is to provide a line simulator that allows reproducible tests by doing this.

[Means for Solving the Problems] The present invention is a line simulator that simulates an actual communication line, and includes parameter setting means for variably setting the parameters of an error signal for generating noise that may occur on the communication line. , a random number generating means for generating random numbers; a signal generating means for generating an error signal determined from the random number generated by the random number generating means according to parameters set by the parameter setting means; a line section that adds noise based on the parameters set by the parameter setting means to the input signal and outputs the resultant signal; and a random number initial value setting means for giving the initial value of the random number generated by the random number generating means to the parameter setting means. The random number generating means is preset by a signal given from the random number initial value setting means.

[Operation] In the line simulator of the present invention, parameters such as pit error rate are set in advance by the parameter setting means. The parameter setting means can also set the initial value of the random number generated by the random number generation means. The error signal generating means generates an error signal determined by the setting parameters from the random number generated by the random number generating means. While this error signal is generated, the line section adds noise determined by the parameters set by the parameter setting means to the signal input from the outside and outputs the added signal. This makes it possible to test the operation of the communication device against communication failures. At this time, by keeping the initial value of the random number constant, it is possible to repeatedly generate noise based on a specific random number and repeatedly test for a specific defect.

[Embodiment] FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a communication system to which a line simulator of the embodiment is connected. The line simulator shown in the figure consists of a parameter setting device 1, a simulator main body 3, and a line section 4.

The parameter setting device 1 inputs parameters such as pit error rate for generating noise that may occur in the communication line to the simulator main body 3 via the bus 2.
A microcomputer can be used as this parameter setting device.

The simulator main body 3 holds the parameters set by the parameter setting device 1, and generates a bit error signal by selecting a random number generated by a circuit described later according to the above parameters, and generates a bit error signal according to the various types shown in FIG. It includes a register file 7 made up of registers, a signal generating section 8 that generates a bit error signal, and a clock generating circuit 9 that supplies lock signals necessary for the operation of each circuit section.

In the communication system shown in FIG. 2, the line simulator of the present invention simulates a plurality of lines (three in this case), so the simulator body 3 includes a plurality of line units 4A, 4.
B and 4C are connected. Each line section includes a transmission line 6A connecting a plurality of communication devices 5A, 5B, and 5C in a loop;
Connected to 6B and 6C. When in use, bit error signals generated in the simulator body 3 are transmitted to the line sections 4A, 4.
B, 4C, and each transmission line 6A, 6B in each line section.
, 6C, and outputs the processed signal by adding noise to it. Therefore, each communication device 5A, 5B,
By checking the output of 5C, it is possible to test noise resistance, etc.

The configuration and operation of the line simulator shown in FIG. 1 will be explained below.

First, the register file 7 functions as a holding means for holding the parameters set by the parameter setting device 1, and includes a random number initial value setting register 11, a bit error rate setting register 12, a bit error pulse width setting register 13, a pit Error mode setting register 14, rising delay setting register 15, falling delay setting register 1
6, and a line disconnection register 17.

The random number initial value setting register 11 is a register for setting an initial value of a pseudo random number generation circuit 21, which will be described later. By writing an initial value into this register, the pseudo random number generation circuit 21 is directly preset. Furthermore, if a certain initial value is set in this register, the same bit error pattern can be generated from the pseudo-random number generation circuit 21, making it possible to perform repeated tests.

The P/I error rate setting register 12 is set to B.

This is a register for setting the error rate, and it is possible to set an error rate of approximately 10-3 to 10-8 times/bit per line. Each line generates bit errors at the same bit error rate. Further, by using this register, it is possible to set whether a bit error occurs or not for each line.

The bit error pulse width setting register 13 is a register that sets the pulse width when a bit error occurs, which will be described later. The setting range is 0 to FFFF, and the setting value n generates a pulse width of n to (n+1) gsec.

As described later, the bit error mode setting register 14 sets the type of bit error (Normal, High) added as noise to the signal input from the transmission path to the line section 4.
h, Low, or inverted). If this is set to "Normal", the signal input to the line section 4 will not change even when a bit error occurs, which will be described later. However, when set to "old gh", the input signal changes to H level and is output from the line section 4 when a bit error occurs, and when set to "Low", the input signal changes to L level when a bit error occurs. will be changed and output. Furthermore, when the inversion mode is set, the input signal is inverted and output when a bit error occurs. This pit error mode setting register 14 can be set separately for a plurality of lines.

The rise and fall delay setting registers 15 and 16 are registers for individually setting the rise time delay and fall time delay that occur in the actual transmission path.

When the clock frequency generated by the clock generation circuit 9 is set to 16 times the baud rate, a delay in units of 1/1B data bit time can be set. The delay times can also be set separately for multiple lines using these registers.

The line disconnection register 17 is a register for connecting and disconnecting the transmission path to the line section, and can make the output from the line section 4 high impedance.

Next, the signal generation section 8 is a section that generates an error signal for simulating phenomena that may occur in an actual communication line, and includes a pseudo random number generation circuit 21, a bit error generation circuit 22, and a bit error pulse width generation circuit. Consists of 23. .

As shown in FIG. 3, the pseudo-random number generation circuit 21 includes 32 D flip-flops D1 to D32 and 13 E+rc
It consists of a lusive OR circuit El-E13 and generates pseudo-random numbers according to a linear equation.

X32+X2G+X23+X22+XIG+X12+X
11+X10+X8 +X7 +X5 +X4 +X2
+X1 +1 That is, the exclusive OR circuit E is connected between the sequentially connected D flip-flops D1 to D32.
1"'E13, each flip-flop D32~
Pseudo-random numbers are generated by changing the outputs X32 to x1 of D1. The pseudorandom number generation circuit itself having such a configuration is well known.

The clock frequency supplied to this pseudo-random number generation circuit 21 is in the range of IMHz to 31.25 KHz, and is usually matched to the communication speed (baud rate). However, by setting it to a value different from the communication speed, the pit error rate can be changed significantly. For example, when operating with an IMHz clock, the cycle is approximately 1.2 hours.

In this pseudo-random number generation circuit 21, in order to set the initial value of the random number to be generated, each of the D flip-flops D1 to D32 has a set terminal, into which the output signal of the random number initial value setting register 11 is inputted. This puts the D flip-flop in the set state. That is, by writing an initial value into the random number initial value setting register 11, the register output is applied to the set terminals of the D flip-flops D1 to D32, and the initial value of the pseudo random number generation circuit 21 can be preset.

Next, as shown in FIG. 4, the bit error generation circuit 22 includes a decoder 31 that decodes the bit error signal from the bit error rate setting register 12, and a signal from the decoder 31 to generate a pseudo-random number generation circuit 21. It consists of a data selector 32 that outputs only the signal to be used from among the pseudo-random numbers generated in , and an AND circuit 33 that outputs a bit error occurrence signal when all the signals output from the data selector 32 are H. As a result, if the number of random number signals selected by the data selector 32 is n, then
A bit error occurrence signal is output with a probability of 1/2'.

Further, the bit error pulse width generation circuit 23 includes a timer 34 and an RS flip-flop 35, as shown in FIG. During operation, as shown in FIG. 6, the timer 34 is started using the output (bit error generation signal) from the bit error generation circuit 22 as a start signal, and the RS flip-flop 35 is set to generate a bit error pulse. do. After counting the pulse width set in the bit error pulse width setting register 13, the timer 34 resets the RS flip-flop 35. This results in a bit error of the set pulse width. The pulse width is n~(n+1) for the set value n.
It becomes μsec. If the next signal comes before the bit error pulse ends, the pulse width is further extended by the set value from that point onwards.

When a plurality of line sections 4A, 4B, and 4C are connected as shown in FIG. 2, this pit error pulse width generation circuit 23 is designed to generate noise with a different pulse width in each line section. There will be a number of locations.

The clock generation circuit 9 has a constant frequency (for example, 16 MHz).
) is frequency-divided from the output signal from the crystal oscillation module, and generates lock signals necessary for each of the above-mentioned circuits.

Next, the line section 4 is a section that processes the input signal according to the parameters given from the simulator main body 3 and outputs it, and also performs line disconnection. It is also possible to monitor or simulate by connecting an external device such as a protocol analyzer.

In detail, as shown in FIG. 7, the line section 4 includes a receiver 41 that converts the level of the signal input from the transmission line, a rising edge detection circuit 42 that detects the rising edge of the input signal, and timers 43 and 44. , a fall detection circuit 45 that detects the fall of an input signal, an RS flip-flop 46, a noise addition circuit 47, and a driver 48 that converts the level of its output signal and outputs it to a transmission line. Each detection circuit 42
45 is a D flip-flop, and each of the timers 43 and 44 is a down counter.

In operation, the detection circuits 42, 45 start the timers 43, 44 when they detect the rising or falling edge of the input signal. Each of the timers 43 and 44 changes its output after a delay time determined by a signal (rise and fall delay values) sent from the rise and fall delay setting registers 15 and 16 of the register file 7, respectively. RS flip flop 46
is set by a change in the output of the rising delay timer 43, and is reset by a change in the output of the falling delay timer 44. As a result, as shown in FIG.
A signal with a falling delay is output.

In this way, the detection circuits 42, 45 and the timers 43 and 44
and the RS flip-flop 46 are used to adjust the rising and falling times of the signal input from the transmission line within a range of less than 1 digital bit time (until immediately before the next signal change).
It constitutes a waveform conversion circuit that can be delayed by .

When the set value is n and the period of the clock used in this circuit is T, the delay time is nT to (n+1)T.

The clock signal supplied to the timers 43 and 44 is as follows:
Typically, a frequency of 16 times the baud rate is used, but a clock with a lower frequency can also be used to create longer delays. In this case, the rising delay time is until immediately before the next rising edge, and the falling delay time is until immediately before the next falling edge.

The waveform conversion circuit described in 2 above can change the duty ratio of the input signal by individually setting the rise/fall delay times. Furthermore, by changing each delay value, jitter (waveform fluctuation) can be caused.

Next, the noise output circuit 47 of the line section 4 applies the error mode (Normal, High, Low, or inverted) specified by the output from the bit error mode setting register 14 to the signal output from the RS flip-flop 46.
When a bit error does not occur (when the bit error pulse is L), the input signal is output as is regardless of the error mode, but when a bit error occurs, the input signal is output as is. (Bit error pulse is H
), the input signal is changed and output according to the error mode.

In other words, if the error mode is fixed to Low, the output will be Low regardless of the input while a bit error occurs.
If the error mode is fixed to the old GH, the output will be High regardless of the input while a bit error occurs.
It becomes h. Similarly, when the error mode is inversion, the output is the inversion of the input while a bit error occurs. When the error mode is Normal, even if a bit error occurs, the input signal is output as is (no noise is added).

The output signal from the noise addition circuit 47 is transmitted to the driver 4
The signal is level-converted at step 8 and output to the transmission line, but the driver 48 is closed by the line disconnection signal from the line disconnection register 17 described above. That is, when the line disconnection register 17 outputs a line disconnection signal, the output side of the driver 48 becomes high impedance, and the transmission line can be substantially disconnected.

Thus, the line simulator of the embodiment generates a preset bit error based on random numbers, and makes it possible to test the response of a communication device to this error. It is also possible to simulate waveform distortion that may occur in a communication line and disconnect the line, making it possible to comprehensively test the performance of a communication device.

Although the present invention has been described above with reference to the embodiments, the present invention is not limited thereto, and each circuit section of the line simulator can be configured with any circuit as long as it has the above-mentioned functions.

[Effects of the Invention] As described above, according to the present invention, noise based on random numbers is generated by giving parameters such as bit error rate, thereby eliminating communication failures that tend to occur on actual transmission paths. It is possible to test the behavior and performance of communication equipment. In particular, specific noise can be repeatedly generated by providing initial values of random numbers, and the cause of communication errors can be investigated by retesting.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a communication system to which the line simulator of the present invention is connected, FIG. 3 is an explanatory diagram of a pseudo-random number generation circuit, Figure 4 is a configuration diagram of the bit error generation circuit, Figure 5 is a configuration diagram of the bit error pulse width generation circuit, Figure 6 is a waveform diagram showing the signal input to the bit error pulse width generation circuit and its output signal, and Figure 6 is a waveform diagram showing the signal input to the bit error pulse width generation circuit and its output signal. FIG. 7 is a configuration diagram of the line section, and FIG. 8 is a waveform diagram showing signals input to the waveform conversion circuit of the line section and their output signals. 1-111 parameter setting device, 2-111 bus, 3--m-simulator main body, 4--line section, 5A, 5B, 5C----1 communication device, 6A, 6B
, 6C---1 transmission line, 7---register file, 8-111 signal generation section, 9-111 clock generation circuit.

Claims (1)

[Scope of Claims] Parameter setting means for variably setting parameters of an error signal for generating noise that may occur in a communication line; Random number generation means for generating random numbers; and Generating the parameters from the random numbers generated by the random number generation means. a signal generating means for generating an error signal determined by a parameter set by the setting means; and while the error signal is being generated, adding noise based on the parameter set by the parameter setting means to an externally input signal. the parameter setting means includes a random number initial value setting means for giving an initial value of the random number generated by the random number generating means, and the random number generating means outputs a random number from the random number initial value setting means. A line simulator characterized in that it is configured to be preset according to a given signal.