JPH01307275A - Semiconductor non-volatile memory - Google Patents
Semiconductor non-volatile memoryInfo
- Publication number
- JPH01307275A JPH01307275A JP63138732A JP13873288A JPH01307275A JP H01307275 A JPH01307275 A JP H01307275A JP 63138732 A JP63138732 A JP 63138732A JP 13873288 A JP13873288 A JP 13873288A JP H01307275 A JPH01307275 A JP H01307275A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- floating gate
- control gate
- region
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000010408 film Substances 0.000 abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、コンピュータなどの電子機器に用いられて
いる半導体不揮発性メモリに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor nonvolatile memory used in electronic equipment such as computers.
この発明は、浮遊ゲート型半導体不揮発性メモリにおい
て、制御ゲート領域を基板表面に設けることにより、浮
遊ゲート電極をポリサイド、あるいは、シリサイド、あ
るいは、金属で形成して、高速で読み出し動作する半導
体不揮発性メモリを実現するものである。The present invention provides a floating gate type semiconductor nonvolatile memory in which a control gate region is provided on the substrate surface, and a floating gate electrode is formed of polycide, silicide, or metal, thereby achieving a semiconductor nonvolatile memory that performs high-speed read operations. It realizes memory.
従来、第一２図に示すように、浮遊ゲート電極７の上に
、熱酸化により形成された制御ゲート酸化 □膜
１６を介して一御ゲート電極１５を設けた半導
、′体不揮発性メモリが知られていた０例えば、Ｊ。Conventionally, as shown in FIG. 12, a semiconductor has been manufactured in which a control gate electrode 15 is provided on a floating gate electrode 7 through a control gate oxide film 16 formed by thermal oxidation.
For example, J.
ＨｉＶａｌＯｔＯｅｔ ａビ＾ｎ ＥＸＨｒｉｌｌｅｎ
ｔａｌ ５Ｖ ０ｎｌｙ ２５６ ′にｂｉｔ
ＣｌＯ２ＥＥ、ＰＲＯＨｗｉｔｈ ａ旧ｏｈ Ｐｅｒｆ
ｏｒｍａｎｃｅ ’５ｉｎｏｌｅ ＰｏＬｙｓｉ
ｌｉｃｏｎ Ｃｅ１ｌ ” ＩＥＥＥ Ｊｏｕｒｎａｌ
ｏｆＳｏｌｉｄ ５ｔａｔｅ Ｃ１ｒｃｕｉｔｓ、ｖ
ｏｌ、 ５Ｃ−２１，Ｎｏ、５，０ＣＴＯＢＥＲ’１９
８６１）Ｅ１８５２−８６０．に開示されている。HiValOtOet abi^n EXHrillen
tal 5V 0nly 256' bit
ClO2EE, PROH with a old oh Perf
ormance '5inole PoLysi
licon Ce1l ” IEEE Journal
ofSolid 5tate C1rcuits,v
ol, 5C-21, No, 5,0CTOBER'19
861) E1852-860. has been disclosed.
しかし、従来の半導体不揮発性メモリは、浮遊
゛ゲート電極７から制御ゲートな極１５への電荷の揮発
を即ぐため仲、品質の良い薄い制御ゲート酸化膜゛１６
を必要とし、その結果、浮遊ゲート電極７は、酸化しや
すい多結晶シリコン膜で形成せざるをえなかった。その
ため、メモリアレイ及び、Ｙの制御回路の配線も多結晶
シリコンが用いられており、メモリの高速化を防げてい
た。However, conventional semiconductor non-volatile memory
``In order to quickly volatilize the charge from the gate electrode 7 to the control gate pole 15, a thin control gate oxide film of good quality is provided'' 16.
As a result, the floating gate electrode 7 had to be formed of a polycrystalline silicon film that is easily oxidized. Therefore, polycrystalline silicon is also used for the wiring of the memory array and the Y control circuit, which prevents the memory from increasing in speed.
そこで、この発明は、従来のこのような欠点を解決する
ために、浮遊ゲート電極を、抵抗率の小さいポリサイド
、あるいは、シリサイド、あるいは、金属で形成するこ
とにより、高速な半導体不揮発性メモリを得ることを目
的としている。Therefore, in order to solve these conventional drawbacks, the present invention obtains a high-speed semiconductor nonvolatile memory by forming the floating gate electrode with polycide, silicide, or metal having low resistivity. The purpose is to
上記課題を解決するために、この発明は、制御ゲート領
域を浮遊ゲート電極の下に設ｊすることにより、浮遊ゲ
ート電極上の熱酸化膜で形成されていた制御ゲート酸化
膜を除いた構造にして、浮遊ゲート電極として、熱酸化
に弱いポリサイド、あるいは、シリサイド、あるいは、
金属を用いて高速半導体不揮発性メモリを可能にした。In order to solve the above problems, the present invention provides a structure in which the control gate oxide film, which is formed of a thermal oxide film on the floating gate electrode, is removed by providing the control gate region under the floating gate electrode. Therefore, as a floating gate electrode, polycide or silicide, which is susceptible to thermal oxidation, or
Made high-speed semiconductor non-volatile memory possible using metal.
以下に、この発明の実施例を、図面にもとづいて説明す
る。Ｎ型の浮遊ゲート電極タイプの半導体不揮発性メモ
リの場合について説明する。第１図に示すように、Ｐ型
のシリコン基板１の表面に、Ｎ＋型ソース領域２、ドレ
イン領域３及び制御ゲート領域５が設けられており、ソ
ース領域２とドレイン領域３との間の基板１の表面であ
るチャネル領域上には、ゲート酸化膜４が設けられてい
る。Embodiments of the present invention will be described below based on the drawings. The case of an N-type floating gate electrode type semiconductor nonvolatile memory will be described. As shown in FIG. 1, an N+ type source region 2, a drain region 3, and a control gate region 5 are provided on the surface of a P-type silicon substrate 1, and a substrate between the source region 2 and the drain region 3 is provided. A gate oxide film 4 is provided on the channel region, which is the surface of the semiconductor device 1 .
制御ゲート領域５の上には、制御ゲート酸化膜６が形成
されている。ゲート酸化１５！４の上には、浮遊ゲート
電極７が設けられており、さらに、浮遊ゲート電極７は
制御ゲート酸化ＷＡ６上まで延びている。制御ゲート領
域５は、浮遊ゲート電極７の電位を効率良く制御するた
めに、制御ゲート酸化。A control gate oxide film 6 is formed on control gate region 5 . A floating gate electrode 7 is provided above the gate oxide 15!4, and the floating gate electrode 7 further extends onto the control gate oxide WA6. The control gate region 5 is subjected to control gate oxidation in order to efficiently control the potential of the floating gate electrode 7.
膜６を介して浮遊ゲート電極７と強く容量結合している
。It is strongly capacitively coupled to the floating gate electrode 7 via the film 6 .
本発明の半導体不揮発性メモリの読み出しは、浮遊ゲー
ト電極７の中の電荷量に対応して、制御ゲート領域５に
対するチャネル領域のコンダクタンスが変化することに
より、情報の読み出しができる。また、情報の記憶は、
ドレイン領域３近傍でのホットエレクトロンを注入する
方法、あるいは、浮遊ゲート電極７の周囲の一部に約１
００人程度の非常に薄いトンネル絶縁膜を設けて、強電
界により、トンネル電流を流すことによりできる。Information can be read from the semiconductor nonvolatile memory of the present invention by changing the conductance of the channel region with respect to the control gate region 5 in accordance with the amount of charge in the floating gate electrode 7. In addition, the memory of information is
A method of injecting hot electrons near the drain region 3, or a method of injecting hot electrons into a part of the periphery of the floating gate electrode 7.
This can be done by providing a very thin tunnel insulating film with a thickness of approximately 0.00 mm and causing a tunnel current to flow using a strong electric field.
情報の消去は、紫外線、あるいは、トンネル電流により
、浮遊ゲート電極７の中の電子を外へ抜き出すことによ
りできる。Information can be erased by extracting electrons in the floating gate electrode 7 to the outside using ultraviolet rays or tunnel current.
本発明の半導体不揮発性メモリの浮遊ゲート電極７は、
ポリサイド、あるいは、シリサイド、あるいは、金属で
形成されている。従って、従来の多結晶シリコン膜に比
べ、抵抗率を電析以上低くすることができる。浮遊ゲー
ト電極７の上に、薄い絶縁膜を介して他の電極が設けら
れていないために、浮遊ゲート電極として、熱酸化に弱
い薄膜・を用いることができる０例えば、ポリサイドは
、熱酸化により、機械的なはがれという問題点があるが
、本発明のメモリでは、浮遊ゲート電極７の上にＣＶＤ
法により形成される厚い中間絶縁膜８゛を設けられるた
め、ポリサイドを・浮遊ゲート電極７に用いることがで
きる。また、浮遊ゲート電極として、アルミニウム、タ
ングステン、チタンなどの金属を用いることもできる。The floating gate electrode 7 of the semiconductor nonvolatile memory of the present invention is
It is made of polycide, silicide, or metal. Therefore, compared to conventional polycrystalline silicon films, the resistivity can be lowered by more than electrodeposition. Since no other electrode is provided on the floating gate electrode 7 via a thin insulating film, a thin film that is susceptible to thermal oxidation can be used as the floating gate electrode. , there is a problem of mechanical peeling, but in the memory of the present invention, CVD is applied on the floating gate electrode 7.
Since a thick intermediate insulating film 8' formed by a method can be provided, polycide can be used for the floating gate electrode 7. Furthermore, metals such as aluminum, tungsten, and titanium can also be used as the floating gate electrode.
金属であるために、その配線ド抗は、従来の多結晶シリ
コンに比べ２桁以上減少できる。従って、高速半導体不
揮発性メモリができる。Because it is a metal, its wiring resistance can be reduced by more than two orders of magnitude compared to conventional polycrystalline silicon. Therefore, a high speed semiconductor non-volatile memory can be created.
また、本発明の半導体不揮発性メモリは、今よ・で説明
したように、浮遊ゲート電極を多結晶シリコン薄膜以外
の薄膜で形成できるために、メモリの周辺制御回路のト
ランジスタのゲート電極と浮遊ゲート電極とを同一工程
で形成できる。即ち、製造工程が簡単になる。最近では
、高速化のために、トランジスタのゲート金属として、
ポリサイド、シリサイドあるいは、金属のように抵抗率
の低い材料が用いられるようになってきているが、本発
明のメモリの場合、これらの高速用ゲート金属を浮遊ゲ
ート電極に用いることができる。In addition, in the semiconductor non-volatile memory of the present invention, as explained in Imayo, the floating gate electrode can be formed of a thin film other than a polycrystalline silicon thin film. The electrodes can be formed in the same process. That is, the manufacturing process is simplified. Recently, in order to increase speed, it has been used as a gate metal for transistors.
Materials with low resistivity such as polycide, silicide, or metal have come to be used, and in the case of the memory of the present invention, these high-speed gate metals can be used for the floating gate electrode.
この発明は、以上説明したように、制御ゲート領域を基
板内に設け、浮遊ゲート電極をポリサイド、シリサイド
、あるいは、金属いづれかの低抵抗率の薄膜を用いるこ
とにより、半導体不揮発性メモリを高速化するとともに
、製造工程をも簡単にする効果がある。As explained above, this invention speeds up semiconductor nonvolatile memory by providing a control gate region in a substrate and using a thin film of low resistivity of polycide, silicide, or metal as a floating gate electrode. This also has the effect of simplifying the manufacturing process.
第１図は、本発明の半導体不揮発性メモリの断面図であ
り、第２図は、従来の半導体不揮発性メモリの断面図で
ある。
５・・・制御ゲート領域
７・・・浮遊ゲート電極
以上
出願人 セイコー電子工業株式会社
代理人 弁理士 林 敬 之 幼牛導体Ｔ−７１
ｉｋ発斗生、ンモリの直面図心１ 図
従来ρ牛導イ本干撲１１生メモリの−面糺呂第２図FIG. 1 is a sectional view of a semiconductor nonvolatile memory according to the present invention, and FIG. 2 is a sectional view of a conventional semiconductor nonvolatile memory. 5... Control gate area 7... Floating gate electrode and above Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Takayuki Hayashi Young cow conductor T-71
ik Hatsuo, Nmori's Face Jushin 1 Diagram Conventional ρ Gyudou I Honken Tournament 11 Raw Memory - Mendori Diagram 2
Claims (1)
のソース領域、ドレイン領域及び制御ゲート領域と、前
記ソース領域と前記ドレイン領域間の前記半導体基板表
面であるチャネル領域と、前記チャネル領域上に形成さ
れたゲート絶縁膜と、前記制御ゲート領域上に形成され
た制御ゲート絶縁膜と、前記ゲート絶縁膜と前記制御ゲ
ート絶縁膜との上に橋渡すごとく設けられた浮遊ゲート
電極とから成るとともに、前記浮遊ゲート電極がポリサ
イド、あるいは、シリサイド、あるいは、金属であるこ
とを特徴とする半導体不揮発性メモリ。A source region, a drain region, and a control gate region of a second conductivity type provided on a surface of a semiconductor substrate of a first conductivity type, a channel region on the surface of the semiconductor substrate between the source region and the drain region, and the channel region. a gate insulating film formed above, a control gate insulating film formed on the control gate region, and a floating gate electrode provided as a bridge over the gate insulating film and the control gate insulating film. A semiconductor nonvolatile memory characterized in that the floating gate electrode is made of polycide, silicide, or metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138732A JP2779623B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor nonvolatile memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63138732A JP2779623B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor nonvolatile memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01307275A true JPH01307275A (en) | 1989-12-12 |
| JP2779623B2 JP2779623B2 (en) | 1998-07-23 |
Family
ID=15228871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63138732A Expired - Lifetime JP2779623B2 (en) | 1988-06-06 | 1988-06-06 | Semiconductor nonvolatile memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2779623B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101030667B1 (en) * | 2007-10-10 | 2011-04-20 | 주식회사 하이닉스반도체 | Method of forming semiconductor memory device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5197345A (en) * | 1975-01-17 | 1976-08-26 | ||
| JPS5978576A (en) * | 1982-10-27 | 1984-05-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
-
1988
- 1988-06-06 JP JP63138732A patent/JP2779623B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5197345A (en) * | 1975-01-17 | 1976-08-26 | ||
| JPS5978576A (en) * | 1982-10-27 | 1984-05-07 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS6317544A (en) * | 1986-07-10 | 1988-01-25 | Seiko Instr & Electronics Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101030667B1 (en) * | 2007-10-10 | 2011-04-20 | 주식회사 하이닉스반도체 | Method of forming semiconductor memory device |
| US7960231B2 (en) | 2007-10-10 | 2011-06-14 | Hynix Semiconductor Inc. | Method of forming a semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2779623B2 (en) | 1998-07-23 |
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