JPH01305737A - Auxiliary signal transmission device - Google Patents

Abstract

PURPOSE:To attain the high quality-transmission of auxiliary signal data which is synchronized with the integer rate of a main signal data speed in a transmission system in which a speed conversion rate is non-integer by generating two clock which are synchronized with the integer rate of a main signal clock and whose phases respectively differ and reproducing auxiliary signal data. CONSTITUTION:An encoding means 4 encodes main signal data/clock from a speed conversion means 1, samples auxiliary signal data S2 from a PCM sound coder 3 by a redundant bit generated in the means 1 and transmits it through a transmission line 5. A decoding means 6 reproduces the main signal data/clock and separates auxiliary signal data S4. Since the speed conversion rate of a signal S4 is non-integer-fold, a bit width becomes uneven and it has a jitter. Thus, clock signals S5 and S6 whose phases respectively differ by 180 deg. from the main clock is generated in a clock generator 8 and an auxiliary signal reproduction circuit 9 selects an adequate method, whereby auxiliary signal data whose width is means and which do not include the jitter are reproduced. Consequently, high quality transmission is attained.

Description

[Detailed description of the invention] [Industrial application field]

The present invention utilizes redundant bits generated as a result of the speed conversion in a code conversion transmission system that performs speed conversion to increase the transmission speed on digitally configured main signal data, then converts the code and transmits the code. The present invention relates to a sub-signal transmission device for transmitting sub-signal data, and particularly to a sub-signal transmission device for transmitting sub-signal data synchronized with an integer ratio of a main signal data rate with high quality.

[Conventional technology]

FIG. 5 is a block diagram showing a sub-signal transmission device using a conventional code conversion transmission system. In the figure, 1 is a speed conversion means which receives main signal data and a main signal clock as input, Generate redundant bits by converting higher. 4 is an encoding means which encodes the main signal data whose speed has been converted in the speed converting means 1, and samples the sub signal data to be described later, which is supplied to the sub signal data input terminal, at multiple points in the redundant bits. By doing this, a transmission line signal in which the sub signal data is multiplexed with the main signal data is generated. 5 is a transmission line for transmitting the transmission line signal outputted from the encoding means 4 to the receiving side, and 6 is a decoding means, which decodes the transmission line signal supplied via the transmission line 5 and also decodes redundant bits. The sub-signal data that is multiplexed and sent is separated by being sampled by the sub-signal data. 7 is speed converting means, and decoding means 6
The original main signal data and main signal clock are recovered by applying a speed conversion inverse to the speed conversion in the speed conversion means 1 constituting the transmission side to the decoded signal. These speed conversion means 1. Encoding means 4. Transmission line 5. The decoding means 6 and the rate conversion means 7 constitute a code conversion transmission system 15. 11 is a clock generator that generates a sub-signal clock by frequency-dividing the main signal clock, which has been speed-converted by the speed conversion means 1, by an integer ratio; 12 is the clock generator 1;
The ΔM coder is a modulation means for generating sub-signal data synchronized with the sub-signal clock outputted from the sub-signal clock output from the sub-signal clock, and the generated sub-signal data is supplied to the sub-signal data input terminal of the encoding means 4. 13 is a clock generator that generates a sub-signal clock by dividing the decoded transmission line clock output from the decoding means 6 by the same integer ratio as the clock generator 11; 14 is the clock generator 13; The 6M decoder is a demodulating means for demodulating the sub-signal data separated by the decoding means 6 based on the sub-signal clock output from the decoding means 6. Next, the operation will be explained. In the sub signal transmission device configured in this way, when main signal data and a main signal clock are supplied, the speed conversion means 1 in the code conversion transmission system 15 increases the transmission speed of the main signal data and main signal clock. By converting the speed in this way, redundant bits are generated and supplied to the encoding means 4. On the other hand, the clock generator 11 generates a sub-signal clock synchronized with the speed-converted main signal clock by frequency-dividing the transmission lock output from the speed conversion means 1 by a predetermined integer ratio. and supplies it to the ΔM coder 12. The ΔM coder 12 modulates the sub signal with the sub signal clock supplied from the clock generator 11 to generate sub signal data and supplies it to the sub signal data input terminal of the encoding means 4. The encoding means 4 encodes the speed-converted main signal data and main signal clock supplied from the speed converting means 1, and also encodes the sub-signal data supplied from the ΔM coder 12. By sampling with redundant bits generated during speed conversion, a transmission line signal in which sub signal data is multiplexed with main signal data is generated. The transmission line signal generated by the encoding means 4 is transmitted to the receiving side via the transmission line 5. On the receiving side, the decoding means 6 decodes the transmission line signal sent via the transmission line and supplies it to the speed conversion means 7. Further, the decoding means 6 uses the redundant bits to separate the encoded and sent sub-signal data, and supplies the separated sub-signal data to the 6M decoder 14. The speed conversion means 7 converts the signal supplied from the decoding means 6 to a speed opposite to the speed conversion in the speed conversion means 1 on the transmission side, that is, returns the speed and removes redundant bits, thereby converting the signal to the original signal. Regenerate main signal data and main signal clock. On the other hand, the clock generator 13 generates a sub-signal clock by frequency-dividing the transmission lock output from the decoding means 6 by the same value as the frequency division value in the transmitting-side clock generator 11. The signal is supplied to the 6M decoder 14. Therefore, the 6M decoder 14 reproduces the sub-signal by demodulating the sub-signal data separated by the decoding means 6 based on this sub-signal clock. For example, in a digital optical transmission system that performs long-distance communication, (1) ease of clock configuration on the receiving side, (2) transmission path monitoring, and (3) sub-signal data transmission such as supervisory control signals, etc. ,
Encoding means 4 and decoding means 6, such as mBnB code, which convert binary m bits into n bits (generally n=m+1) are used. In general, in transmission systems of 100 Mb/s or more, the conversion ratio between the main signal data rate and the transmission line speed is a non-integer ratio of less than 2 in order to suppress the increase in circuit cost due to the use of high-speed circuit elements. The transmission line code is used.

[Problem to be solved by the invention]

Since the conventional sub-signal transmission device is configured as described above, when code conversion is performed, the speed conversion ratio becomes a non-integer, and in order to transmit sub-signal data synchronized with the integer ratio of the original main signal data, it is necessary to Even if multi-point sampling is performed, only very low-speed sub-signal data in which data width and jitter are not a problem can be transmitted. In addition, to transmit audio sub-signals, a ΔM modulation audio cog that can change the sampling frequency is used, but it can only transmit sub-signal data that is synchronized with an integer ratio of the transmission line speed. There were problems such as. This invention was made to solve the above-mentioned problems, and if the average sampling number is 2 or more, it is possible to transmit sub-signal data synchronized with an integer ratio of the main signal data rate with high quality. The purpose is to obtain a sub-signal transmission device.

[Means to solve the problem]

The sub signal transmission device according to the present invention includes a first speed converting means for converting main signal data and a main signal clock so that the transmission speed becomes faster in the speed converting means to generate redundant bits, and the first speed converting means. code converting means for converting the code of the output and transmitting it; decoding means for decoding the transmitted signal after code conversion; In a code conversion transmission system that is provided with a second speed conversion means for regenerating the original main signal data and main signal clock by speed conversion, an integer ratio (1/L) of the main signal clock is provided on the transmitting side.
) is provided, and the sub-signal data generated in synchronization with the sub-signal Cook generated from the first clock generator is encoded in the code conversion transmission system. By sampling with the redundant bits, the data is multiplexed with the main signal data and transmitted, and on the receiving side, the data is transmitted in different phases synchronized with the integer ratio (1/L) of the received main signal clock. A second clock generator that generates two types of clocks, and a sub-signal data regeneration circuit that receives as input the two types of clock signals having different phases output from the second clock generator and the received sub-signal data. , the sub-signal data reproducing circuit generates sub-signal data having a uniform width and no jitter, and a sub-signal clock synchronized with the sub-signal data, from the received sub-signal data having a non-uniform width and containing jitter. .

[Effect]

In the sub-signal transmission device of the present invention, when the sub-signal data is encoded in the encoding means constituting the transmitting side, the sub-signal data is sampled in a state where the data width is non-uniform and includes jitter, and is converted into a transmission line signal. Also, the received sub-signal data separated by the decoding means constituting the receiving side is regenerated into jitter-free sub-signal data with uniform data width in the sub-signal reproducing circuit, so the speed conversion ratio is a non-integer. Even in a digital transmission system, it is possible to transmit sub-signal data synchronized with an integer ratio of the main signal data rate.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a block diagram for explaining the sub signal transmission method according to the present invention, in which the speed of main signal data is 97.728.
Mb/s, main signal clock frequency 97.728M
Hz, and the transmission line signal speed is 111.689 Mb/s.
, the frequency of the transmission line clock is set to 111.689 MHz. In the figure, reference numeral 1 denotes a speed conversion means, which converts the main signal data and the main signal clock as described above.
Redundant bits are generated by rate conversion to 144/126 as a non-integer multiple. A clock generator 2 generates a 64 KHz sub-signal clock Sl by dividing the main signal clock by 1527 before speed conversion. 3 is a PCM audio coder as a modulation means, which converts the sub signal into a sub signal clock S.
1 to generate sub-signal data S2 of 54 KHz. 4 is an encoding means which encodes the main signal data and the main signal clock after speed conversion, and also encodes the 6 4 Kb/s sub signal data S supplied from the PCM audio coder 3.
By sampling 2 at multiple points using redundant bits, a transmission line signal in which sub signal data is multiplexed with main signal data is generated and supplied to the transmission line 5. 6 is a decoding means which decodes the transmission line signal supplied via the transmission line 5, and separates the multiplexed sub signal data sent by sampling with redundant bits;
This separated sub-signal data is output as received sub-signal data S4. 7 is speed converting means, and decoding means 6
The speed of the main signal data and main signal clock supplied from the main signal clock is converted to a non-integer multiple of 126/144, which is the opposite of the conversion ratio in the speed converting means 1. 8 is obtained by dividing the main signal clock output from the speed converting means 7 by 1527 in the same way as the clock generator 2 on the transmitting side.
Two types of clock signals with different phases of 4KHz35.36
9 is a sub-signal reproducing circuit which converts the received sub-signal data S4 separated in the decoding means 6 into sub-signal data S7 having a uniform data width and no jitter.
and outputs it together with a sub-signal clock S8 synchronized with the regenerated sub-signal data. Reference numeral 10 denotes a PCM audio decoder serving as demodulation means for generating a sub signal by inputting sub signal data S7 and sub signal clock S8 generated from the sub signal reproducing circuit 9. FIG. 2 is a waveform diagram showing the operation of each part of the block diagram shown in FIG. 1, and the operation will be explained below using FIG. In the sub signal transmission device configured in this way, when main signal data and a main signal clock are supplied, the speed conversion means 1 in the code conversion transmission system 15 increases the transmission speed of the main signal data and main signal clock. By converting the speed in this way, redundant bits are generated and supplied to the encoding means 4. On the other hand, the clock generator 2 divides the main signal clock before speed conversion by 1527 to generate a 54 KHz sub-signal clock S1 shown in FIG. It is supplied to the audio coder 3. In the PCM audio coder 3, by modulating the sub signal with the sub signal clock S1 supplied from the clock generator 2, as shown in FIG. 2(b), sub signal data S2 synchronized with the sub signal clock S1 is generated. is generated and supplied to the sub-signal data input terminal of the encoding means 4. The encoding means 4 encodes the speed-converted main signal data and main signal clock supplied from the speed converting means 1, and also encodes the sub-signal data supplied from the PCM audio coder 3. The transmission path signal S3 shown in FIG. 2(c) is generated by sampling with the redundant bits generated during speed conversion. In this embodiment, the sub signal data S2 is sampled every 576 bits of the transmission line signal S3.
The average number of samples is 3.03. In other words, for 1-bit sub-signal data S2, there are cases where the number of samplings is three and four times. The transmission line signal S3 generated by the encoding means 4 is transmitted to the receiving side via the transmission line 5. On the receiving side, the decoding means 6 decodes the transmission line signal sent via the transmission line and supplies it to the speed conversion means 7. The speed conversion means 7 converts the signal supplied from the decoding means 6 to a speed opposite to the speed conversion in the speed conversion means 1 on the transmission side, that is, returns the speed and removes redundant bits, thereby converting the signal to the original signal. Regenerate main signal data and main signal clock. Further, the decoding means 6 separates the signal sampled by the redundant bits and sent, and outputs the separated signal as received sub-signal data S4. Here, the received sub-signal data S4 separated from the transmission signal S3 by the decoding means 6 is as shown in FIG. 2(d).
A bit B that is wider than the other bit widths will occur and have jitter. Therefore, if the main signal clock reproduced in the speed conversion means 7 is divided into the same frequency as that on the transmitting side to generate a sub-signal clock, and the received sub-signal data S4 is waveform-shaped using this generated sub-signal clock, the original This means that the sub-signal is reproduced. However, since the phase of the sub-signal clock generated on the receiving side cannot be specified for the received sub-signal data S4, if a sub-signal clock with timing near the logic change point in the received sub-signal data S4 is generated. In this case, the logical identification becomes uncertain and normal reproduction of the sub-signal cannot be performed. For this purpose, the clock generator 8 divides the main signal clock output from the speed converting means 7 by 1527 in the same way as the clock generator 2 on the transmitting side, so that the clock signal shown in FIGS. 64KHz
Two types of clock signals S5 whose phases differ by 180° from each other
．． Generate and output S6. One of the clock signals 35 and S6 generated in this manner has a timing appropriate for the received sub-signal data S4. In other words, if bit B of the received sub-signal data S4 shown in FIG. 2(d) is sampled at the rising edge of the clock signal S5 shown in FIG. 2(e), bit B will be sampled twice. In some parts, the original sub-signal data cannot be reproduced. On the other hand, if the received sub-signal data S4 is sampled using the rising edge of the clock signal S6 shown in FIG. l-
Sampling is performed once for each of A to D, and as shown in FIG. 2(g), sub signal data S7 matching the original sub signal data S2 is reproduced. In this way, the clock signals S5, which have different phases from each other, are applied to the received sub-signal data S4, which has non-uniform width and includes jitter.
By selecting and using the appropriate one from 36,
The sub-signal reproducing circuit 9 reproduces the sub-signal data S7, which has a uniform width and does not contain jitter, and outputs it together with the sub-signal clock S8. The sub signal data S7 and the sub signal clock S8 generated from the sub signal reproducing circuit 9 are
By being supplied to the CM audio decoder 10, the sub signal is reproduced. Note that in the above embodiment, the PCM audio coder and the PC
Although the case has been described in which the M audio decoder is used as the audio codec, audio codecs based on ADM or ADPCM modulation methods may also be used. Furthermore, the present invention is not limited to audio codecs, and any sub-signal data synchronized with an integer ratio of the main signal clock can be transmitted. FIG. 3 is a circuit diagram showing a specific example of the sub-signal reproducing circuit shown in FIG. 1. In the figure, 16 is a data change point detection circuit, which is composed of a delay line 16a that delays the received sub-signal data S4, and an exclusive OR gate 16b that receives the received sub-signal data S4 and the output of the delay line 16a. It is configured. Reference numeral 17 denotes a phase determination/control circuit, which is constituted by a flip-flop circuit 17a at J-, which inputs the change point detection pulse S9 outputted from the data change point detection circuit 16 to J. Reference numeral 18 denotes a selection circuit which outputs clock signals S5. S6 is selected, and the selected clock signal is output as the sub-signal clock S8. Reference numeral 19 denotes an identification circuit, which is constituted by one D flip-flop circuit NI having received sub-signal data S4 as a D input and sub-signal clock S8 outputted from the selection circuit 18 as a T input. The operation of the sub-signal regeneration circuit with the above configuration will be explained below in Fig. 4 (
This will be explained using the waveform diagrams shown in a) to (g). First, as shown in FIG. 4(a), when received sub-signal data S4 with jitter is supplied, the delay circuit 16a constituting the data change point detection circuit 16 converts this received sub-signal data S4 by Δ. delay over time. The received sub-signal data delayed in this delay circuit 16a and the original received sub-signal data S4 are supplied to an exclusive OR gate 16b. As a result, the exclusive OR gate 16b generates a change point detection pulse S9 shown in FIG. supply Here, the delay time Δt is determined in consideration of the magnitude of sick, etc., and is usually set to 2 or less with respect to the period T of the received sub-signal data S4. The selection circuit 18 receives two types of clock signals S5. S6 is selected depending on the logic state of the output signal SIO of the phase determination/control circuit 17 inputted to the control terminal Y, and the selected clock signal is output as the sub-signal clock S8. In other words, if the logic state of the output signal 310 is "0", the clock signal S5
is selected, and if the logic state is “loo”, the clock signal S
Select 6. Then, this selected clock signal is outputted as a sub-signal clock S8 as shown in FIG. 4(e). The flip-flop circuit 17a constituting the phase determination/control circuit 17 receives the change point detection pulse S9 supplied from the data change point detection circuit 16. It is input to both K terminals. Therefore, when the sub-signal clock S8 selected in the selection circuit 18 is supplied to the T terminal, a toggle operation is possible during the period in which the change point detection pulse S9 is "1°", and in that state, the sub-signal clock S8 is supplied to the T terminal. If clock S8 has a rising edge,
The output signal 510 output from the Q terminal changes as shown in FIG. 4(f). Further, the change point detection pulse S9
Even if the sub-signal clock S8 rises during the period in which the input to the re-input terminal J is "0", that is, the input to the re-input terminal is "0", the logic state of the output signal SIO is as shown in FIG. The output signal of the phase determination/control circuit 17 output in this manner is supplied to the control signal terminal Y of the selection circuit 18 to control the phase of the sub-signal clock S8 supplied to the identification circuit 19. Here, the identification circuit 19 is constituted by a D-type flip-flop circuit, and at the rising point of the sub-signal clock S8 output from the selection circuit 18, the received sub-signal data S4 supplied to the D terminal is is read and outputted as sub-signal data S7 as shown in FIG.
It is necessary to avoid the vicinity of such a change point of the received sub-signal data S4 and to locate the rising point of the sub-signal clock S8 in an interval where the logic level is stable. Therefore, during the period when the change point detection pulse is "loo", that is, the received sub signal data S4
In a period that is inappropriate for sampling J
-, the flip-flop circuit 17a is enabled for toggle operation. For example, like the period up to point a shown in Figure 4,
When the unsuitable lock signal S5 is selected, a phase suitability determination is made at the rising point a, and J
- The logic of the output signal SIO output from the flip-flop circuit (14) is inverted and the change point detection pulse S9 does not rise during the period of "1°" from point b shown in FIG. Signal S6 is the selection circuit 18
By selecting the sub signal clock S8, the sub signal clock S8 is outputted as the sub signal clock S8. Therefore, after the 0 point shown in FIG. 4, J of the flip-flop circuit 17a becomes J-. The logic of the change point detection pulse S9 input to both K terminals is
Since the selected sub-signal clock S8 rises in the state of 0"', the flip-flop circuit 1 is connected to J-.
The logic state of the output signal SIO output from the Q terminal of 7a does not change, and accordingly, stable timing can be ensured. Note that the change point detection circuit for detecting the change point of the received sub-signal data is not limited to the above configuration (any circuit may be used as long as it generates a pulse having a constant time width at the change point). It is also possible to use a logic gate, a mono-multi-by-break, etc. in place of the delay line 16a. [Effects of the Invention] As described above, according to the present invention, the main signal data and the main signal clock can be A first speed converting means converts the transmission speed so that the transmission speed becomes high (in the speed converting means) and generates redundant bits; a code converting means converts the code of the output of the first speed converting means and transmits the code; a decoding means for decoding the transmission signal transmitted by the decoding means; and a speed converting means for converting the decoded signal in the decoding means so that the transmission speed becomes the original speed, thereby regenerating the original main signal data and the main signal clock. In a code conversion transmission system provided with a second speed conversion means, an integer ratio (1/L) of the main signal clock is set on the transmitting side.
A first clock generator is provided which generates a sub-signal Cook in synchronization with the sub-signal Cook, and the sub-signal data generated in synchronization with the sub-signal Cook generated from the first clock generator is encoded by the encoding means in the code conversion transmission system. A second clock that is sampled and transmitted using the redundant bits by supplying the second clock to a generator, and a sub-signal data reproducing circuit which receives as input two types of clock signals having different phases outputted from the second clock generator and the received sub-signal data, and the sub-signal data reproducing circuit has a width. From the received sub-signal data which is non-uniform and contains jitter, sub-signal data having a uniform width and not including jitter and a sub-signal clock synchronized with this sub-signal data are generated. As a result, when the sub-signal data is encoded in the encoding means that constitutes the transmitting side, even if the data width is non-uniform and contains jitter and is sampled and converted to a transmission path signal, the receiving side The received sub-signal data separated in the decoding means is regenerated into jitter-free sub-signal data with a uniform data width in the sub-signal regeneration circuit, so even in a digital transmission system where the speed conversion ratio is a non-integer, This has the effect of highly accurate transmission of sub signal data synchronized with the integer ratio of the main signal data rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a sub-signal transmission device according to an embodiment of the present invention, FIGS. 2(a) to (g) are waveform diagrams showing operation waveforms of each part of the block diagram shown in FIG. 1, and FIG. is a circuit diagram showing a specific example of the sub-signal regeneration circuit shown in Fig. 1, and Fig. 4 (
a) to (g) are waveform diagrams showing operation waveforms of each part of the circuit shown in FIG. 3, and FIG. 5 is a block diagram showing a conventional sub-signal transmission device. 1.7 is a speed conversion means, 2.8 is a clock generator, 4 is a code conversion means, 5 is a transmission line, 6 is a decoding means, 9 is a sub-signal reproducing circuit, 16 is a data change point detection circuit, and 17 is a A phase determination/control circuit, 18 a selection circuit, and 19 an identification circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 1) , 0 0 °C tl −■ν
,+--++'- Figure 4ryS +:' Procedural amendment (voluntary) Heisei 1.1.18 Heisei ← Year Month Date

Claims (1)

[Claims] a first speed converter that converts main signal data and a main signal clock so that the transmission speed becomes faster in the speed converter to generate redundant bits; and a code that converts the output of the first speed converter and transmits the code. a converting means, a decoding means for decoding the transmitted signal after code conversion on the receiving side, and a decoding means for decoding the signal decoded by the decoding means so that the transmission speed becomes the original speed. In a sub-signal transmission device equipped with a code conversion transmission system constituted by main signal data and a second speed conversion means for reproducing the main signal clock, an integer ratio (1/ L) generates a sub-signal cook synchronized with the sub-signal cook, supplies the sub-signal data generated using the sub-signal cook to the encoding means, samples it with the redundant bits, and multiplexes it with the main signal data. a first clock generator for transmitting the clock;
The integer ratio (1
/L); a second clock generator that generates two types of clock signals having different phases and synchronized with the second clock generator; two types of clock signals output from the second clock generator; and a decoding means in the code conversion transmission system. The received sub-signal data separated at is input, and from the received sub-signal data with non-uniform width and jitter, sub-signal data with uniform width and no jitter and a sub-signal clock synchronized with this sub-signal data are obtained. A sub-signal transmission device comprising: a sub-signal reproducing circuit for reproducing a sub-signal.