JPH01305714A - Digital filter - Google Patents

Abstract

PURPOSE:To eliminate S/P conversion and to reduce a circuit area even in a high-order digital filter by serially accumulating and adding the multiplied result of digital data which are serially inputted and a filter coefficient. CONSTITUTION:Data rate conversion circuits 3a-3d multiply digital data which have serially been inputted and the filter coefficient and generate serial outputs by the conversion of the data rate of digital data. Digital data are serially accumulated and added by one bit adders 4a and 4b, and accumulated data are serially accumulated and added by a one bit adder 4c. The digital filter serially operates the sum of products by using digital data which have serially been inputted and the filter coefficient shown by 2<m>.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital filter, and particularly to a digital filter to which digital data is serially input.

[Conventional technology]

FIG. 3 shows a conventional FIR (Finite Impu
FIG. 2 is a block system diagram showing an example of a configuration of a digital filter of the type digital filter. In Figure 3,
1 is an input terminal to which digital data is manually entered, 2 is an output terminal to which cumulative results are output, 10a to 10d are input terminals to which filter coefficients aw and d are input, 20 is a digital filter, and 21 is a serial-parallel conversion circuit. , 22a~
22c is an n-bit register, 23a to 23d are mxn-bit multipliers, and 24 is an accumulator.

In FIG. 3, n-bit digital data serially input from the input terminal 1 is converted into n-bit parallel digital data by a serial-parallel conversion circuit 21. In FIG. The output of the serial-parallel conversion circuit 21 is applied to a digital filter 20 in parallel. This digital filter 20 includes n-bit registers 22a to 22.
It is comprised of multipliers 23a to 23d that perform multiplication of C and m-bit filter coefficients, and an accumulator 24 that cumulatively adds the multiplication results, and performs a product-sum operation of digital data.

Each of the n-bit registers 22a to 22c delays input digital data by one sample period, and is connected in cascade to the output of the serial-parallel conversion circuit 21. Each of the multipliers 238 to 23d receives the output of the serial-parallel conversion circuit 21, the output of the n-bit register 22a, the output of the n-bit register 22b, and the output of the n-bit register 22c at one input thereof, and receives the output from the n-bit register 22c at the other input. receives m-bit filter coefficients a, b, c, and d input from input terminals 10a to 10d. Each of the multipliers 23a to 23d multiplies the negative input data by the other input data, and by changing the filter coefficients a, b, c, and d, the filter characteristics of the digital filter 20 can be changed. I can do it.

The cumulative adder 24 cumulatively adds the outputs of the multipliers 23a to 23d, and the cumulative result is serially output from the output terminal 2 as the output of the digital filter 20.

The transfer function H (Zl
is as shown in the following equation (11).In addition, Z−n in the following equation (1)
represents a delay of n sample periods.

H(z)=a +b Z-"+c Z-"+d Z-'
+ ・・・・・・(1) Figure 4 shows the filter coefficient a,
F when b, c, d are expressed as powers of 2
1 is a block system diagram showing an example of the configuration of an IR type digital filter. FIG. In the same figure, 21.22a to 22c are the same as those in FIG. 3, and their explanation will be omitted. 31a-3
1d is an N-bit register for performing multiplication with a filter coefficient represented by 2''. Here, the multiplication of the filter coefficient of 2'' and digital data is performed by shifting the digital data by m bits. I can do it.

The cumulative adder 24 includes the N-bit registers 31a to 31d.
The cumulative sum of the outputs of is performed, and the cumulative result is serially outputted from the output terminal 2 as the output of the digital filter 20.

[Problem to be solved by the invention]

Conventional digital filters in which digital data is serially input are configured as described above, so the digital data must be serial-parallel converted, and the accumulation is performed according to the multiplication result of the digital data and filter coefficients. Since an adder is required, when attempting to realize a high-order digital filter, there is a problem that the multiplication results are output in the same number as the order of the filter, and the circuit area of the cumulative adder 24 increases.

The present invention has been made in view of these points, and its purpose is to perform product-sum operations on digital data serially and to reduce the circuit area of the cumulative adder even in high-order digital filters. The goal is to obtain a digital filter.

[Means to solve the problem]

In order to solve such problems, the digital filter according to the present invention includes a data rate conversion circuit that serially outputs digital data shifted according to a filter coefficient at a different data rate, and an output of this data rate conversion circuit. The first step is to cumulatively add the received digital data serially.
a 1-bit adder, a second 1-bit adder that receives the output of the first 1-bit adder and serially adds accumulated data, and a carry output of the first and second 1-bit adders. A 1-bit register is provided for this purpose.

[Effect]

The digital filter according to the present invention multiplies serially input digital data by shifting it according to the filter coefficient, and also converts the data rate so that the number of data is the same as the output data of the digital filter. A 1-bit adder and a 1-bit register are used to perform cumulative addition.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a digital filter according to the present invention. In the figure, ■ is an input terminal for serially inputting digital data, 2 is an output terminal for serially outputting the output data of the digital filter, and 3a to 3d are serially inputted digital data and filter coefficients. 4a and 4b receive the output of the data rate conversion circuit and serially cumulatively add the digital data. Bit adder, 4c is the above 1
1-bit adders 5a to 5 for receiving the outputs of the bit adders 4a and 4b and serially adding cumulative data;
C is a 1-bit register for the carry output of the 1-bit adder. This digital filter serially performs a product-sum operation using serially input digital data and a filter coefficient expressed by 2 degrees.

The data rate conversion circuits 33 to 3d delay the serially input digital data by one sample, and perform multiplication by shifting m bits according to the filter coefficient represented by 2'', and output data from the digital filter. It converts the data rate so that it has the same number of data and outputs it serially, and is connected in cascade to input terminal 1. Then, 1-bit adder 4
The cumulative output of C is serially output from output terminal 2 as the output of the digital filter. Further, the 1-bit registers 5a to 5c are reset to zero after the cumulative addition for one sample is completed.

Next, FIG. 2 shows the data rate conversion circuit 3 shown in FIG.
It is a block system diagram showing an example of a composition of a-3d. Here, it is assumed that the serially input digital data is n bits, the output data of the digital filter is N bits, and the coefficient of the filter is represented by 21.

In FIGS. 2(a) and (b), lla and llb are input terminals for serially inputting n-bit input data, 12a and 12b are output terminals for serially outputting n-bit input data, 13a and 13b are output terminals for serially outputting N-bit digital data at different data rates; 14a and 14b are n-bit registers; and 15a and 15b are N-bit registers.

Next, the operation will be explained with reference to FIG. 2 (al). First,
N-bit input data is serially input from the input terminal 11a to the n-bit register 14a.

Next, the register output of each bit of the n-bit register 14a is shifted by m bits according to the filter coefficient represented by 2'' and inputted to the N-bit register 15a.

Here, m-bit shift of digital data means multiplication by 21 filter coefficients. FIG. 2 (the example of al is the case where the filter coefficient is 2°, and the n-bit register 14a
The digital data of N-bit register 1 is not shifted.
'5a is input. Here, it is assumed that zero is input to the upper (N-n) bits of the N-bit register.

Then, the N bit register 15a receives N/ of the input data.
Serially output N-bit digital data at n times the data rate.

In addition, the example shown in FIG.
The data is bit-shifted and input to the N-bit register 15b. Here, zero is input to the lower m bits of the N-bit register 15b.

In this way, by changing the shift amount when inputting the register output of each bit of the n-bit registers 14a, 14b to the N-bit registers 15a, 15b, the filter coefficient can be changed, and the filter characteristics of the digital filter can be changed. be able to.

〔Effect of the invention〕

As explained above, the digital filter according to the present invention is
By serially cumulatively adding the multiplication results of serially input digital data and filter coefficients, there is no need for serial-parallel conversion. Since this also becomes unnecessary, the circuit area of the cumulative adder can be reduced even in high-order digital filters.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram showing an embodiment of a digital filter according to the present invention, FIG. 2 is a block system diagram showing an example of the configuration of a data rate conversion circuit constituting the digital filter of FIG. FIG. 4 is a block system diagram showing a conventional digital filter. 1...Input terminal, 2...Output terminal, 33~3d...
- Data rate conversion circuit, 4a to 4C...1 bit adder, 5a to 5C...1 bit register.

Claims (1)

[Claims] A digital filter to which digital data is input serially includes a data rate conversion circuit that serially outputs digital data shifted according to a filter coefficient at a different data rate, and a data rate conversion circuit that receives the output of this data rate conversion circuit and converts the digital data into a first 1-bit adder that serially adds cumulative data; a second 1-bit adder that receives the output of the first 1-bit adder and serially adds cumulative data; and a 1-bit register for the carry output of the 1-bit adder.