JPH01305589A - Working method for electrode wiring - Google Patents
Working method for electrode wiringInfo
- Publication number
- JPH01305589A JPH01305589A JP13551688A JP13551688A JPH01305589A JP H01305589 A JPH01305589 A JP H01305589A JP 13551688 A JP13551688 A JP 13551688A JP 13551688 A JP13551688 A JP 13551688A JP H01305589 A JPH01305589 A JP H01305589A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode
- electrode wiring
- item
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000005520 cutting process Methods 0.000 claims description 17
- 239000011521 glass Substances 0.000 claims description 10
- 238000003672 processing method Methods 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims 1
- 230000002265 prevention Effects 0.000 claims 1
- 230000002093 peripheral effect Effects 0.000 abstract 2
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007790 scraping Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電極加工法に係り特に静電対策や断線欠陥対策
等に用いた共通電極配線の用済み後の切削除去法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrode processing method, and more particularly to a method for cutting and removing a common electrode wiring after its use, which is used as a countermeasure against static electricity or a disconnection defect.
[従来の技術〕
第3図(a)、(b)はこの発明にかかわるマトリクス
型液表示装置の平面、断面の外観図である。組立は第3
図(b)の様にT P T電極基板1と共通電極基板2
を一定間隙に保ち組み立て、液晶を充填する注入孔を除
いて周囲を接着剤でシールする。次に注入孔より液晶材
を充填し、その注入孔を封孔し、偏光板を貼付けして、
液晶パネルが完成する。TPT電極基板1の内部の詳細
回路は第4図に示すとうりである。番号3はTFT電極
基板1外部に設けられたゲート電極4ならびにソース電
極5のり−1・を短絡したショー1へリングて’]’
F T電極基板1の外周に形成したものである。[Prior Art] FIGS. 3(a) and 3(b) are plan and cross-sectional external views of a matrix liquid display device according to the present invention. Assembly is the third step
As shown in figure (b), T P T electrode substrate 1 and common electrode substrate 2
Assemble them with a certain gap between them, and seal the entire area with adhesive except for the injection hole where the liquid crystal will be filled. Next, fill the liquid crystal material through the injection hole, seal the injection hole, and attach a polarizing plate.
The LCD panel is completed. The detailed circuit inside the TPT electrode substrate 1 is as shown in FIG. Number 3 is a short circuit between the gate electrode 4 and the source electrode 5 provided on the outside of the TFT electrode substrate 1.
It is formed on the outer periphery of the F T electrode substrate 1.
なお第4図においては表示部の四隅(四表示素子分)の
みを示したが、実際には縦方向及び横方向に合計数百本
(敵方素子)が存在し、その省略部を点線にて表示して
いる。一般にT P T電極基板1はラビンタ工程で静
電気を帯電しやすいが、第3図(a)の様にゲーh電極
及びソース電極が端子部で短絡されてるショートリンク
3となっておりTPTが損傷されることはない。この液
晶表示パネルをモジュールに組み込むため、従来の加工
法は、特開昭61−59475に述へられているが第3
図(a)の−点鎖線部分を切断することにより開放する
方法である。Although only the four corners (four display elements) of the display section are shown in Figure 4, there are actually several hundred in total (enemy elements) in the vertical and horizontal directions, and their omitted parts are shown as dotted lines. is displayed. Generally, the TPT electrode substrate 1 is easily charged with static electricity during the ravinta process, but as shown in Fig. 3(a), the gate electrode and the source electrode are short-circuited at the terminal part, forming a short link 3, which can damage the TPT. It will not be done. Conventional processing methods for incorporating this liquid crystal display panel into a module are described in Japanese Patent Application Laid-Open No. 61-59475.
This is a method of opening by cutting the - dotted chain line portion in Figure (a).
」二記TFT電極基板]のショー1−リンク3を開放す
るためダイシングソーによりガラス基板を切断する方法
は、切断のためTPT電極基板1の切りしるが必要とな
り、基板サイズを太きくしなければならないこと。また
切断作業において切断部がチッピング等を生し、基板自
体に歪みが入り相立て時において破壊を生ずるおそれが
ある。さらにTFT電極基板1の電極端子部へファイン
ピッチコネクタを接続した際、ファインピッチコネクタ
が基板のカットコーナ部に接触した損傷するおそれがあ
る。またTFT電極基板1のショートリング3の結線部
をホ1−エツチングで除去する方法があるが最終工程で
プロセスが繁雑となりロス1〜高となる。The method of cutting the glass substrate with a dicing saw to open the link 3 in Show 1 of ``TFT Electrode Substrate 2'' requires cutting the TPT electrode substrate 1 for cutting, and the substrate size must be made thicker. Things that must not happen. Furthermore, there is a risk that chipping may occur at the cut portion during the cutting operation, and the substrate itself may be distorted, resulting in breakage during assembly. Furthermore, when the fine pitch connector is connected to the electrode terminal portion of the TFT electrode substrate 1, there is a risk that the fine pitch connector may contact the cut corner portion of the substrate and be damaged. There is also a method of removing the connecting portion of the short ring 3 of the TFT electrode substrate 1 by hole-etching, but the process becomes complicated in the final step, resulting in a loss of 1 to high.
本発明の目的は上記TPT電極基板のショート電極作用
済み後の除去に当り基板の切断しろをなくすることおよ
び基板切断による組立時の損傷がないよう容易に作業が
行なえるようにすることである。The purpose of the present invention is to eliminate the margin for cutting the TPT electrode substrate when removing the TPT electrode substrate after the short electrode function has been completed, and to facilitate the work so that there is no damage during assembly due to cutting the substrate. .
本発明はTPT電極基板の切りしろをとらないでショー
1ヘトリング開放のため、ショートリングをTPT電極
基板周辺に配置し、基板コーナ部を基板面に対し角度0
−20°〜90°で切削する。In order to open the short ring without taking the cut margin of the TPT electrode substrate, the present invention arranges a short ring around the TPT electrode substrate, and sets the corner part of the substrate at an angle of zero to the substrate surface.
Cut at -20° to 90°.
切削法としては、タラインダ、エアーブラシブ等による
。The cutting method is by using a tarinder, airbrushing, etc.
上記切削作業で、TPT電極基板上周辺のショーミーリ
ングは、基板を削ると同時に除去される。In the above cutting operation, the show milling around the top of the TPT electrode substrate is removed at the same time as the substrate is cut.
したがってショー1−リングは各電極端子先端部より切
除され、各端子間は分離されることになる。Therefore, the show 1-ring is cut off from the tip of each electrode terminal, and each terminal is separated.
以下本発明について実施例を用いて説明する。 The present invention will be explained below using examples.
ショート電極3の加工を必要とするアクティダマ1〜リ
クス液晶デイスプレィ基板6の平面を第1図に示す。構
成はアクティブマトリクスTPT電極基板下板1の表面
のゲートとソース電極端子7゜8をTFT電極基板1の
周辺に引き出し、それぞれTPTの静電気破壊防止用と
して端子接続電極9によりショート電極3に繋がれてい
る。また共通電極基板2の上板にはカラーフィルタが形
成され、」二板と下板の間に液晶が封入されアクティブ
マI〜リクスディスプレイ基板6を構成している。FIG. 1 shows a plan view of the Actidama 1-RIX liquid crystal display substrate 6 that requires processing of the short electrode 3. As shown in FIG. The configuration is such that the gate and source electrode terminals 7.8 on the surface of the active matrix TPT electrode substrate lower plate 1 are drawn out around the TFT electrode substrate 1, and each is connected to the short electrode 3 by a terminal connection electrode 9 to prevent electrostatic damage of the TPT. ing. Further, a color filter is formed on the upper plate of the common electrode substrate 2, and a liquid crystal is sealed between the second plate and the lower plate to constitute an active matrix display substrate 6.
第」図はTPT電極基板1下板の中央部を共通電極基板
2上板でカバーしており、共通電極基板2で覆われてる
下基板については、第4図で述べたT P T電極基板
と同じ素子構成であり、ソース線及びソース線のり−l
−電極5形成時にソース線を延長し、同時にこのソース
線のリード電極に接続するショート電極3を’I’ F
T電極基板1面の外周部にポリシリコン膜によって形
成し、その後ケー1へ電極およびグー1〜線のリード線
形成時に、やはリグ−1−線を延長させてショート電極
3と接続させる。このように、ショート電極3を形成し
た後、ショート電極3を電気的に接地してラビング法等
の液晶配向処理を実施し製作している。In Figure 4, the central part of the lower plate of the TPT electrode substrate 1 is covered by the upper plate of the common electrode substrate 2, and the lower substrate covered by the common electrode substrate 2 is the same as the TPT electrode substrate described in Figure 4. It has the same element configuration as , and the source line and source line glue -l
- When forming the electrode 5, extend the source line and at the same time connect the short electrode 3 to the lead electrode of this source line by 'I' F.
A polysilicon film is formed on the outer periphery of the T-electrode substrate 1 surface, and then when forming the electrode and the lead wire of the wire 1 to the case 1, the wire 1 is extended and connected to the short electrode 3. After forming the short electrode 3 in this manner, the short electrode 3 is electrically grounded and a liquid crystal alignment process such as a rubbing method is performed to manufacture the liquid crystal.
次に第2図に示すように7トリクス型液晶デイスプレィ
基板6を真空吸着等の基板固定機構を備えたXY移動台
10に取り付ける。基板6のコーナ部加工は、T P
T電極基板6の表面に対して角度0=45°とし、棒状
のグラインダ」1の回転軸12に連結するモータ13を
駆動させることによって行う。加工領域は第1図におけ
るデイスプレィ基板6の外周より一点鎖線部までとする
加工によって1”FT電極基板1表面のショート電極3
はグー1〜電極、ソース電極端子7,8の端子接続電極
部9より切除され、ゲート電極端子7とソース電極端子
8は分離される。電極として800人厚さのアルミニウ
ム電極の加工性はゲート、ソース電極端子7,8の線幅
150μmに対しショート電極を繋ぐ端子接続用電極9
の線幅を157z m円部に電極に削りクズの付着を完
全に無くすことができる。Next, as shown in FIG. 2, the 7-trix type liquid crystal display substrate 6 is attached to an XY moving table 10 equipped with a substrate fixing mechanism such as vacuum suction. The corner portion of the board 6 is processed by T P
This is performed by setting an angle of 0=45° to the surface of the T-electrode substrate 6 and driving a motor 13 connected to a rotating shaft 12 of a rod-shaped grinder 1. The processing area extends from the outer periphery of the display substrate 6 to the dashed-dotted line in FIG.
is removed from the terminal connection electrode portion 9 of the goo 1 to electrode and source electrode terminals 7 and 8, and the gate electrode terminal 7 and source electrode terminal 8 are separated. The workability of an 800 mm thick aluminum electrode is that the line width of the gate and source electrode terminals 7 and 8 is 150 μm, while the terminal connection electrode 9 connects the short electrode.
With a line width of 157 zm, it is possible to completely eliminate the adhesion of shavings to the electrode.
第5図は本発明第2の実施例を説明する図である。TP
T電極基板1上に第1の多結晶シリコンを形成し、その
」二にゲート酸化膜を形成する。第1の多結晶シリコン
はグー1〜電極ライン14を構成し、その片側(左側)
の信号入力端子は相互に短絡され共通電極15となる。FIG. 5 is a diagram illustrating a second embodiment of the present invention. T.P.
A first polycrystalline silicon film is formed on a T electrode substrate 1, and a gate oxide film is formed on the second polycrystalline silicon film. The first polycrystalline silicon constitutes the electrode line 14, and one side (left side)
The signal input terminals of are short-circuited to each other to form a common electrode 15.
一方、ソース電極ライン16の片側(下側)も全て短絡
する。これは断線欠陥の検査を行うためでテスターの一
方の電極を共通電極15に接続し、他方の電極をソース
またはグー1〜電極信号入力端子の短絡してない側に順
次接触させ、各信号線の抵抗を測定し検査するものであ
る。本発明はこのように利用した共通電極15用済み後
に除去する場合にも役立つ。On the other hand, one side (lower side) of the source electrode line 16 is also all short-circuited. This is to test for disconnection defects, so one electrode of the tester is connected to the common electrode 15, and the other electrode is sequentially contacted with the source or the non-shorted side of the electrode signal input terminal from Goo 1 to each signal line. It measures and inspects the resistance of The present invention is also useful when the common electrode 15 used in this manner is removed after use.
加工領域は、TPT電極電極基板部線部一点鎖線A−A
’ 、B−B’部までTPT電極基板面と切削角0−3
0°で基板を削った場合である。この結果、共通電極1
5を除去することができ、ゲート電極ライン、ソース電
極ラインはそれぞれ開放され、端子部分が独立分離でき
、支障ない7トリクス基板が得られる。The processing area is the one-dot chain line A-A of the TPT electrode electrode substrate part.
', TPT electrode substrate surface and cutting angle 0-3 to B-B' part
This is a case where the substrate is shaved at 0°. As a result, common electrode 1
5 can be removed, the gate electrode line and the source electrode line are each opened, and the terminal portions can be independently separated, resulting in a trouble-free 7-trix substrate.
アクティブマトリクスデイスプレィ装置組立のために、
実施例]1,2によってTPT電極基板1上に形成した
ソースおよびゲート電極端子7(8)とコネクタ17の
接続は、第6図の断面のとうりになる。ただし、1.8
.19はコネクタ樹脂部、コネクタ半田部である。本発
明の特長点として、従来法で述べた共通電極切断のため
基板サイズを必要以上に大きくする必要のないことのほ
か点円内に示すようにTPT電極基板1の加工したコー
ナ部とTFT電極基板上の端子部に接着したコネクタ1
7との面には、小さく一定の角度が付けられ、コネクタ
17が多少曲っても余裕ができ、TFT電極基板コーナ
部においてコネクタが極端に電極せずコネクタの摩耗等
の損傷が少ない。For active matrix display device assembly,
Embodiment] The connection between the source and gate electrode terminals 7 (8) formed on the TPT electrode substrate 1 in accordance with 1 and 2 and the connector 17 is as shown in the cross section of FIG. However, 1.8
.. 19 is a connector resin part and a connector solder part. As a feature of the present invention, there is no need to make the substrate size larger than necessary due to the cutting of the common electrode as described in the conventional method. Connector 1 glued to the terminal part on the board
7 is formed at a small constant angle, so that there is a margin even if the connector 17 is bent to some extent, and the connector does not form an extreme electrode at the corner of the TFT electrode substrate, thereby reducing damage such as wear of the connector.
また第7図でTPT電極基板等の基板として使用する基
板コーナ部分にテーパー状の面取り部20を設けた例を
説明する。コーナ部を面取りした基板21に製造工程の
最初からショート電極3を形成した基板を使用するかプ
ロセスの途中で面取り部にショート電極3を形成して使
用する。このようにすると電極端子22分離工程におい
て、ガラス基板の切削量を少なくでき作業が容易となる
。Further, in FIG. 7, an example will be described in which a tapered chamfered portion 20 is provided at a corner portion of a substrate used as a substrate such as a TPT electrode substrate. A substrate 21 with chamfered corners on which short electrodes 3 are formed from the beginning of the manufacturing process is used, or short electrodes 3 are formed on the chamfered parts during the process. In this way, in the step of separating the electrode terminals 22, the amount of cutting of the glass substrate can be reduced and the work becomes easier.
したがって、基板として本発明を考慮し、あらかじめ基
板コーナ部分を面取りした基板を製品として準備してお
くことができる。Therefore, considering the present invention as a substrate, a substrate whose corner portions are chamfered in advance can be prepared as a product.
本発明によればガラス基板周辺エッヂ部を削ることだけ
の簡単な作業でガラス基板周辺に引き出した端子を連結
するショートリングを加工性よく分離除去でき、ショー
1−リング切り離しのためにガラス基板にあらかじめ切
りしろ幅を設けなくとも遜色ない電極基板を形成できア
クティブマ1−リクスディスプレイ等の組み込みによっ
ても特性維持ができる。さらに加えてガラス基板のエッ
ヂ部の面取りをすることで端子ボンディング等に当り基
板エッヂ部からのクラックを入りに<<シ、ガラス基板
上の電極端子部に接続するファインピッチコネクタの損
傷を軽減し、接続後の信頼性を向上させる。According to the present invention, the short ring connecting the terminals pulled out around the glass substrate can be easily separated and removed by simply scraping the edge portion around the glass substrate, and the short ring connecting the terminal pulled out around the glass substrate can be easily separated and removed. A comparable electrode substrate can be formed without providing a cutting margin in advance, and characteristics can be maintained even when an active matrix display or the like is incorporated. In addition, chamfering the edges of the glass substrate prevents cracks from entering the edges of the substrate during terminal bonding, etc., and reduces damage to fine pitch connectors that connect to electrode terminals on the glass substrate. , improve reliability after connection.
第1図は本発明の第1実施例の平面説明図、第2図は本
発明によるガラス基板の加工方法の説明図、第3図は従
来の説明図、第4図はTPTガラス基板上の素子および
配線構成図、第5図は本発明の第2実施例の平面説明図
、第6図は本発明による基板の電極端子とコネクタの接
続図、第7図は本発明の詳細な説明図である。
1・TPT電極基板、3 ショート電極、7・ゲ−l−
電極端子、8 ソース電極端子、9 ・端子接続電極、
15・・共通電極、20 面取り部、21II−
=470−FIG. 1 is an explanatory plan view of the first embodiment of the present invention, FIG. 2 is an explanatory diagram of the method of processing a glass substrate according to the present invention, FIG. 3 is an explanatory diagram of the conventional method, and FIG. Element and wiring configuration diagram, FIG. 5 is a plan view of the second embodiment of the present invention, FIG. 6 is a connection diagram of the electrode terminal of the board and connector according to the present invention, and FIG. 7 is a detailed explanatory diagram of the present invention. It is. 1.TPT electrode substrate, 3. Short electrode, 7.Ge-l-
Electrode terminal, 8 Source electrode terminal, 9 ・Terminal connection electrode,
15... Common electrode, 20 Chamfered portion, 21II- =470-
Claims (11)
通電極配線の加工法において、該共通電極配線を該絶縁
基板の周辺部に設け、該絶縁基板のコーナ部分を切削す
る時に該絶縁基板上の共通電極配線を端子部より削除し
、端子部を分離することを特徴とする電極配線加工法。1. In a method of processing a common electrode wiring that connects terminals of circuits formed on an insulating substrate, the common electrode wiring is provided on the periphery of the insulating substrate, and when cutting a corner portion of the insulating substrate, the common electrode wiring is provided on the insulating substrate. An electrode wiring processing method characterized by removing the common electrode wiring from the terminal part and separating the terminal part.
極配線として、アクティブマトリクス基板上の静電気破
壊対策用および断線検索用の共通電極配線除去法に適用
することを特徴とする電極配線加工法。2. The electrode wiring processing method according to item 1, characterized in that it is applied to a common electrode wiring removal method for electrostatic damage prevention and disconnection detection on an active matrix substrate as a common electrode wiring connecting terminal parts of circuits and the like.
工傾斜角を20゜〜90゜とすることを特徴とする電極
配線加工法。3. An electrode wiring processing method according to item 1, characterized in that the processing inclination angle with respect to the substrate surface is 20° to 90°.
とを特徴とする電極配線加工法。4. An electrode wiring processing method characterized in that a grinder is used as the processing means according to item 1.
ことを特徴とする電極配線加工法。5. An electrode wiring processing method characterized in that an airbrush sib is used as the processing means according to item 1.
するためコーナ部を面取りしたことを特徴とする基板。6. A board characterized in that corner portions are chamfered to facilitate terminal division by removing the common electrode wiring as described in item 1.
を特徴とする基板。7. A substrate characterized in that a short electrode is provided on the chamfered portion of the substrate according to item 6.
対して直角に位置させ、砥石軸をガラス基板面に対し角
度θとし、回転砥石が基板の辺に平行に基板または回転
砥石を移動させながら基板コーナを削ることを特徴とす
る装置。8. In the processing method of item 1, the rotary whetstone is positioned perpendicular to the side of the glass substrate, the whetstone axis is at an angle θ to the glass substrate surface, and the whetstone moves the substrate or the rotary whetstone parallel to the side of the substrate. A device characterized by cutting the corners of a board.
とを特徴とする装置。9. An apparatus characterized in that the corner cutting of the substrate according to item 8 is performed by airbrushing.
ィスプレイTFT電極基板等の加工したコーナ部と該電
極基板上の端子部に接着するコネクタとの面間に小さい
角度θが設けられ、コネクタがエッヂ部で摩耗しにくい
ことを特徴とする電極基板。10. A small angle θ is provided between the processed corner portion of the active matrix display TFT electrode substrate etc. manufactured in accordance with item 1 and the connector bonded to the terminal portion on the electrode substrate, so that the connector wears out at the edge portion. An electrode substrate characterized by being difficult to clean.
り、端子ボンディング等でクラックが入りにくいことを
特徴とする電極基板。11. 10. The electrode substrate according to item 10, wherein the edge portion of the substrate is chamfered to prevent cracks from forming during terminal bonding or the like.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13551688A JPH01305589A (en) | 1988-06-03 | 1988-06-03 | Working method for electrode wiring |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13551688A JPH01305589A (en) | 1988-06-03 | 1988-06-03 | Working method for electrode wiring |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01305589A true JPH01305589A (en) | 1989-12-08 |
Family
ID=15153590
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13551688A Pending JPH01305589A (en) | 1988-06-03 | 1988-06-03 | Working method for electrode wiring |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01305589A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6043390A (en) * | 1983-08-05 | 1985-03-07 | ダブリユ−・ア−ル・グレイス・アンド・カンパニ− | Production of l-amino acid from alpha-keto acid |
JPS61177790A (en) * | 1985-02-01 | 1986-08-09 | 日本電気株式会社 | Printed wiring board and manufacture thereof |
-
1988
- 1988-06-03 JP JP13551688A patent/JPH01305589A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6043390A (en) * | 1983-08-05 | 1985-03-07 | ダブリユ−・ア−ル・グレイス・アンド・カンパニ− | Production of l-amino acid from alpha-keto acid |
JPS61177790A (en) * | 1985-02-01 | 1986-08-09 | 日本電気株式会社 | Printed wiring board and manufacture thereof |
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